9338DMQB [NSC]
8-Bit Multiple Port Register; 8位的多端口寄存器
| 型号： | 9338DMQB |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit Multiple Port Register |
| 文件： | 总6页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1989
9338/DM9338 8-Bit Multiple Port Register
General Description
The DM9338 is an 8-bit multiple port register designed for
high speed random access memory applications where the
ability to simultaneously read and write is desirable. A com-
mon use would be as a register bank in a three address
computer. Data can be written into any one of the eight bits
and read from any two of the eight bits simultaneously.
Connection Diagrams
Dual-In-Line Package
TL/F/9794–1
Order Number 9338DMQB, 9338FMQB or DM9338N
See NS Package Number J16A, N16E or W16A
Pin Names
Description
Write Address Inputs
A0–A2
D
Data Input
A
B0–B2
C0–C2
CP
B Read Address Inputs
C Read Address Inputs
Clock Pulse Input (Active Rising Edge)
Slave Enable Input (Active LOW)
B Output
SLE
Z
Z
B
C
C Output
FASTÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9794
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
5.5V
Operating Free Air Temperature Range
Military
Commercial
b
b
a
55 C to 125 C
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
Military
Commercial
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
IH
0.8
0.8
V
IL
b
b
0.8
16
I
I
0.8
16
125
mA
mA
OH
OL
b
T
A
55
0
70
C
§
t
t
(H)
20
20
12
s
ns
ns
ns
ns
ns
(L)
D
A
to CP
12
0
s
t
t
(H)
(L)
Hold Time HIGH or LOW
to CP
0
h
b
b
D
A
8.0
8.0
h
t
t
(H)
(L)
Setup Time HIGH or LOW
to CP
10
10
10
s
A
n
10
s
t
t
(H)
(L)
Hold Time HIGH or LOW
to CP
0
0
0
0
h
A
n
h
t
t
(H)
(L)
CP Pulse Width HIGH or LOW
23
13
23
13
w
w
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
12 mA
Max
V
V
I
CC
I
High Level Output Voltage
V
V
OH
CC
OH
2.4
3.4
0.2
e
Max
IL
e
e
V
OL
Low Level Output Voltage
V
V
Min, I
Max
5.5V
CC
OL
0.4
V
e
Min
IH
@
Input Current Max
e
e
I
I
V
CC
Max, V
I
1
mA
Input Voltage
e
e
e
e
e
I
I
I
High Level Input Current
Low Level Input Current
V
V
V
Max, V
Max, V
Max
2.4V
0.4V
MIL
27
mA
IH
CC
CC
CC
I
b
1.1
mA
IL
I
b
b
b
b
Short Circuit
10
10
70
70
OS
mA
mA
Output Current
(Note 2)
COM
e
CC
I
Supply Current
V
Max
135
CC
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time.
CC
A
2
Switching Characteristics
5.0V, T
e a
e a
25 C (See Section 1 for waveforms and load configurations)
V
CC
§
A
e
C
15 pF
L
Symbol
Parameter
9338 (MIL)
DM9338 (COM)
Units
Min
Max
Min
Max
t
t
Propagation Delay
or C to Z
40
35
13
18
40
35
PLH
ns
ns
ns
B
PHL
n
n
n
t
t
Propagation Delay
to Z
45
50
25
25
45
50
PLH
D
A
PHL
n
t
t
Propagation Delay
CP to Z
35
30
18
13
35
30
PLH
PHL
n
Functional Description
The 9338 8-bit multiple port register can be considered a 1-
bit slice of eight high speed working registers. Data can be
written into any one and read from any two of the eight
locations simultaneously. Master/slave operation eliminates
all race problems associated with simultaneous read/write
activity from the same location. When the clock input (CP) is
data during the read operation. The state of each slave is
determined by the state of the master selected by its associ-
ated set of read address inputs.
The method of parallel expansion is shown in Figure a. One
9338 is needed for each bit of the required word length. The
read and write input lines should be connected in common
on all of the devices. This register configuration provides
two words of n-bits each at one time, where n devices are
connected in parallel.
LOW data applied to the data input line (D ) enters the
A
selected master. This selection is accomplished by coding
the three write input select lines (A0–A2) appropriately.
Data is stored synchronously with the rising edge of the
clock pulse.
Logic Symbol
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0–B2 and
C0–C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (Z and Z ).
C
B
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The data
flows into the device, is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch. The eight latches function as masters and store the
input data. The two output latches are slaves and hold the
TL/F/9794–2
e
e
V
Pin 16
CC
GND
Pin 8
TL/F/9794–4
FIGURE a. Parallel Expansion
3
Logic Diagram
TL/F/9794–3
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 9338DMQB
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM9338N
NS Package Number N16E
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 9338FMQB
NS Package Number W16A
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