93L14 [NSC]
Quad Latch; 四锁存
| 型号： | 93L14 |
| 厂家： | 
National Semiconductor |
| 描述： | Quad Latch |
| 文件： | 总6页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1989
93L14 Quad Latch
General Description
Features
Y
Can be used as single input
latches
D
latches or set/reset
The 93L14 is a multifunctional 4-bit latch designed for gen-
eral purpose storage applications in high speed digital sys-
tems. All outputs have active pull-up circuitry to provide high
capacitance drive and to provide low impedance in both
logic states for good noise immunity.
Y
Active low enable gate input
Y
Overriding master reset
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL/F/9612–2
e
e
V
Pin 16
CC
GND
Pin 8
TL/F/9612–1
Order Number 93L14DMQB or 93L14FMQB
See NS Package Number J16A or W16A
Pin Names
Description
E
Enable Input (Active LOW)
Data Inputs
D0–D3
S0–S3
MR
Set Inputs (Active LOW)
Master Reset Input (Active LOW)
Latch Outputs
Q0–Q3
C
1995 National Semiconductor Corporation
TL/F/9612
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
5.5V
Operating Free Air Temperature Range
MIL
b
b
a
55 C to 125 C
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
93L14 (MIL)
Units
Symbol
Parameter
Min
4.5
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
IH
0.7
V
IL
b
I
I
400
mA
mA
OH
OL
4.8
b
T
A
55
125
C
§
t
t
(H)
10
s
ns
ns
(L)
D
n
to E
20
s
t
t
(H)
(L)
Hold Time HIGH or LOW
to E
0
h
h
D
n
10
t
t
t
t
t
(H)
(L)
(L)
(L)
Setup Time HIGH, D to S
n
15
5
ns
ns
ns
ns
ns
s
n
Hold Time LOW, D to S
n
h
n
E Pulse Width LOW
30
25
5
w
w
MR Pulse Width LOW
Recovery Time, MR to E
rec
2
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
10 mA
V
V
I
CC
I
High Level Output Voltage
V
V
Max,
Min
2.4
OH
CC
OH
e
e
Max, V
IL
IH
e
e
V
OL
Low Level Output Voltage
V
V
Min, I
Max,
CC
OL
0.3
V
e
e
Min, V
Max
IH
IL
@
Input Current Max
e
e
I
I
V
Max, V
5.5V
I
CC
I
1
mA
mA
Input Voltage
e
e
e
e
High Level Input Current
V
CC
Max, V
2.4V
0.3V
Inputs
20
30
IH
IL
I
D
n
e
b
I
Low Level Input Current
V
V
Max, V
Max
Inputs
400
600
CC
I
mA
b
D
n
I
I
Short Circuit
OS
CC
CC
b
b
2.5
25
16.5
mA
mA
Output Current
(Note 2)
e
Max (Note 3)
Supply Current
V
CC
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
CC
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: I is measured with all outputs open and all inputs grounded.
A
CC
Switching Characteristics
5.0V, T
e a
e a
25 C (See Section 1 for waveforms and load configurations)
V
CC
§
A
e
C
L
15 pF
Symbol
Parameter
Units
Min
Max
t
t
Propagation Delay
45
36
PLH
ns
ns
E to Q
PHL
n
t
t
Propagation Delay
to Q
30
30
PLH
D
n
PHL
n
t
t
Propagation Delay, MR to Q
30
33
ns
ns
PLH
PHL
n
Propagation Delay, S to Q
n
n
3
Functional Description
Truth Table
The 93L14 consists of four latches with a common active
LOW Enable input and active LOW Master Reset input.
When the Enable goes HIGH, data present in the latches is
stored and the state of the latch is no longer affected by the
MR
E
D
S
Q
Operation
n
H
H
H
L
L
L
H
X
L
L
X
L
D Mode
L
S
n
and D inputs. The Master Reset when activated over-
n
H
Q
n
b
1
rides all other input conditions forcing all latch outputs LOW.
Each of the four latches can be operated in one of two
modes:
H
H
H
H
H
L
L
L
L
H
L
H
L
L
L
L
H
L
R/S Mode
H
H
X
D-TYPE-LATCHÐFor D-type operation the S input of a
latch is held LOW. While the common Enable is active the
latch output follows the D input. Information present at the
latch output is stored in the latch when the Enable goes
HIGH.
H
X
Q
Q
b
n
1
1
b
n
L
X
X
X
L
RESET
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
SET/RESET LATCHÐDuring set/reset operation when the
common Enable is LOW a latch is reset by a LOW on the D
input, and can be set by a LOW on the S input if the D input
is HIGH. If both S and D inputs are LOW, the D input will
dominate and the latch wil be reset. When the Enable goes
HIGH, the latch remains in the last state prior to disable-
ment. The two modes of latch operation are shown in the
Truth Table.
X
Q
Q
e
Previous Output State
Present Output State
b
n
n
1
e
Logic Diagram
TL/F/9612–3
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L14DMQB
NS Package Number J16A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 93L14FMQB
NS Package Number W16A
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