ADC0820CIWM
更新时间：2024-09-18 02:06:26
品牌：NSC
描述：8-Bit High Speed レP Compatible A/D Converter with Track/Hold Function
概述
数据手册ADC0820CIWM 概述
8-Bit High Speed レP Compatible A/D Converter with Track/Hold Function 8位高速レP兼容A / D转换器，带有采样/保持功能
ADC0820CIWM 数据手册
通过下载ADC0820CIWM数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载June 1999
ADC0820
8-Bit High Speed µP Compatible A/D Converter with
Track/Hold Function
General Description
Features
n Built-in track-and-hold function
n No missing codes
By using
a half-flash conversion technique, the 8-bit
ADC0820 CMOS A/D offers a 1.5 µs conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bit ADC and
a least significant 4-bit ADC.
n No external clocking
n Single supply — 5 VDC
n Easy interface to all microprocessors, or operates
stand-alone
n Latched TRI-STATE® output
n Logic inputs and outputs meet both MOS and T2L
voltage level specifications
The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external
sample-and-hold for signals moving at less than 100 mV/µs.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or I/O port
without the need for external interfacing logic.
n Operates ratiometrically or with any reference value
equal to or less than VCC
n 0V to 5V analog input voltage range with single 5V
supply
Key Specifications
n No zero or full-scale adjust required
n Overflow output available for cascading
n 0.3" standard width 20-pin DIP
n 20-pin molded chip carrier package
n 20-pin small outline package
n Resolution
8 Bits
2.5 µs Max (RD Mode)
1.5 µs Max (WR-RD Mode)
75 mW Max
n Conversion Time
n Low Power
n 20-pin shrink small outline package (SSOP)
n Total Unadjusted
1
±
±
⁄2 LSB and 1 LSB
Error
Connection and Functional Diagrams
Dual-In-Line, Small Outline
and SSOP Packages
Molded Chip Carrier
Package
DS005501-1
DS005501-33
Top View
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS005501
www.national.com
Connection and Functional Diagrams (Continued)
DS005501-2
FIGURE 1.
Ordering Information
Part Number
Total
Package
Temperature
Range
Unadjusted Error
ADC0820BCV
V20A — Molded Chip Carrier
0˚C to +70˚C
1
±
ADC0820BCWM
ADC0820BCN
ADC0820CCJ
ADC0820CCWM
ADC0820CIWM
ADC0820CCN
⁄
2
LSB
M20B — Wide Body Small Outline
N20A — Molded DIP
0˚C to +70˚C
0˚C to +70˚C
−40˚C to +85˚C
0˚C to +70˚C
−40˚C to +85˚C
0˚C to +70˚C
J20A — Cerdip
M20B — Wide Body Small Outline
M20B — Wide Body Small Outline
N20A — Molded DIP
±
1 LSB
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2
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
300˚C
215˚C
220˚C
Supply Voltage (VCC
)
10V
−0.2V to VCC +0.2V
−0.2V to VCC +0.2V
−65˚C to +150˚C
875 mW
Operating Ratings (Notes 1, 2)
Logic Control Inputs
Voltage at Other Inputs and Output
Storage Temperature Range
Temperature Range
ADC0820CCJ
T
MIN≤TA≤TMAX
−40˚C≤TA≤+85˚C
−40˚C≤TA≤+85˚C
0˚C≤TA≤70˚C
0˚C≤TA≤70˚C
0˚C≤TA≤70˚C
4.5V to 8V
=
Package Dissipation at TA 25˚C
ADC0820CIWM
Input Current at Any Pin (Note 5)
Package Input Current (Note 5)
ESD Susceptability (Note 9)
1 mA
ADC0820BCN, ADC0820CCN
ADC0820BCV
4 mA
1200V
ADC0820BCWM, ADC0820CCWM
VCC Range
Lead Temp. (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
260˚C
Converter Characteristics
=
=
=
=
The following specifications apply for RD mode (pin 7 0), VCC 5V, VREF(+) 5V,and VREF(−) GND unless otherwise speci-
=
=
fied. Boldface limits apply from TMIN to TMAX; all other limits TA Tj 25˚C.
Parameter
Conditions
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820BCWM
ADC0820CCWM, ADC0820CIWM
Limit
Units
ADC0820CCJ
Typ
Tested
Limit
(Note 7)
8
Design
Limit
Typ
Tested
Limit
Design
Limit
(Note 6)
(Note 6)
(Note 8)
(Note 7)
(Note 8)
Resolution
8
8
Bits
LSB
LSB
LSB
LSB
kΩ
1
1
±
±
Total Unadjusted
Error
ADC0820BCN, BCWM
ADC0820CCJ
⁄
2
⁄
2
±
1
±
±
(Note 3)
ADC0820CCN, CCWM, CIWM,
ADC0820CCMSA
1
1
1
1
±
±
Minimum Reference
Resistance
2.3
2.3
1.00
6
2.3
2.3
1.2
Maximum Reference
Resistance
5.3
6
kΩ
V
Maximum VREF(+)
Input Voltage
Minimum VREF(−)
Input Voltage
Minimum VREF(+)
Input Voltage
Maximum VREF(−)
Input Voltage
Maximum VIN Input
Voltage
VCC
VCC
VCC
GND
GND
GND
V
VREF(−)
VREF(+)
VCC+0.1
GND−0.1
VREF(−)
VREF(+)
VCC+0.1
GND−0.1
VREF(−)
VREF(+)
VCC+0.1
GND−0.1
V
V
V
Minimum VIN Input
Voltage
V
=
CS VCC
Maximum Analog
Input Leakage
Current
=
VIN VCC
3
0.3
3
µA
µA
=
VIN GND
−3
−0.3
−3
1
1
1
=
±
±
±
±
±
±
Power Supply
Sensitivity
VCC 5V 5%
1/16
⁄
4
1/16
⁄
4
⁄
4
LSB
3
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DC Electrical Characteristics
=
The following specifications apply for VCC 5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other
=
=
limits TA TJ 25˚C.
Parameter
Conditions
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820BCWM
ADC0820CCWM, ADC0820CIWM
Limit
Units
ADC0820CCJ
Typ
Tested
Limit
(Note 7)
2.0
Design
Limit
Typ
Tested
Limit
(Note 7)
2.0
Design
Limit
(Note 8)
2.0
(Note 6)
(Note 6)
(Note 8)
=
VIN(1), Logical “1”
Input Voltage
VCC 5.25V
CS , WR , RD
V
V
Mode
3.5
3.5
3.5
=
VIN(0), Logical “0”
Input Voltage
VCC 4.75V
CS , WR , RD
Mode
0.8
0.8
0.8
V
1.5
1.5
1.5
V
=
IIN(1), Logical “1”
Input Current
VIN(1) 5V; CS , RD
0.005
0.1
1
0.005
0.1
1
µA
µA
µA
µA
=
VIN(1) 5V; WR
3
0.3
3
=
VIN(1) 5V; Mode
50
200
−1
50
170
200
−1
=
IIN(0), Logical “0”
Input Current
VIN(0) 0V; CS , RD , WR ,
−0.005
−0.005
Mode
=
=
VOUT(1), Logical “1”
Output Voltage
VCC 4.75V, IOUT −360 µA;
2.4
4.5
0.4
2.8
4.6
2.4
4.5
0.4
V
V
V
DB0–DB7, OFL , INT
=
=
VCC 4.75V, IOUT −10 µA;
DB0–DB7, OFL , INT
=
=
VOUT(0), Logical “0”
Output Voltage
IOUT, TRI-STATE
Output Current
ISOURCE, Output
Source Current
ISINK, Output Sink
Current
VCC 4.75V, IOUT 1.6 mA;
0.34
DB0–DB7, OFL , INT , RDY
=
VOUT 5V; DB0–DB7, RDY
0.1
−0.1
−12
−9
3
−3
−6
−4.0
7
0.1
−0.1
−12
−9
0.3
−0.3
−7.2
−5.3
8.4
3
−3
−6
−4.0
7
µA
µA
=
VOUT 0V; DB0–DB7, RDY
=
VOUT 0V; DB0–DB7, OFL
mA
mA
mA
INT
=
VOUT 5V; DB0–DB7, OFL ,
14
14
INT , RDY
=
=
=
ICC, Supply Current
CS WR RD 0
7.5
15
7.5
13
15
mA
AC Electrical Characteristics
=
= =
=
=
=
The following specifications apply for VCC 5V, tr tf 20 ns, VREF(+) 5V, VREF(−) 0V and TA 25˚C unless otherwise speci-
fied.
Typ
Tested
Limit
Design
Limit
Parameter
Conditions
Pin 7 0, Figure 2
(Note 6)
Units
(Note 7)
(Note 8)
2.5
=
tCRD, Conversion Time for RD
Mode
1.6
µs
ns
=
t
ACC0, Access Time (Delay from
Pin 7 0, Figure 2
tCRD+20
tCRD+50
1.52
Falling Edge of RD to Output
Valid)
=
=
t
CWR-RD, Conversion Time for
Pin 7 VCC; tWR 600 ns,
µs
=
tRD 600 ns; Figures 3, 4
WR-RD Mode
=
tWR, Write Time
Min
Max
Min
Pin 7 VCC; Figures 3, 4
600
600
ns
µs
ns
(Note 4) See Graph
50
=
t
RD, Read Time
Pin 7 VCC; Figures 3, 4
(Note 4) See Graph
=
<
Pin 7 VCC, tRD tI; Figure 3
t
ACC1, Access Time (Delay from
=
Falling Edge of RD to Output
Valid)
CL 15 pF
190
210
280
320
ns
ns
=
CL 100 pF
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4
AC Electrical Characteristics (Continued)
=
= =
=
=
=
The following specifications apply for VCC 5V, tr tf 20 ns, VREF(+) 5V, VREF(−) 0V and TA 25˚C unless otherwise speci-
fied.
Typ
Tested
Limit
Design
Limit
Parameter
Conditions
(Note 6)
Units
(Note 7)
(Note 8)
=
>
Pin 7 VCC, tRD tI; Figure 4
tACC2, Access Time (Delay from
Falling Edge of RD to Output
Valid)
=
CL 15 pF
70
90
30
120
150
ns
ns
ns
=
CL 100 pF
= =
RPULLUP 1k and CL 15 pF
t
ACC3, Access Time (Delay from
Rising Edge of RDY to Output
Valid)
=
tI, Internal Comparison Time
Pin 7 VCC; Figures 4, 5
800
100
1300
200
ns
ns
=
CL 50 pF
= =
RL 1k, CL 10 pF
t
1H, t0H, TRI-STATE Control
(Delay from Rising Edge of RD to
Hi-Z State)
= =
Pin 7 VCC, CL 50 pF
t
INTL, Delay from Rising Edge of
>
WR to Falling Edge of INT
tRD tI; Figure 4
tI
ns
ns
ns
<
tRD tI; Figure 3
tRD+200
125
tRD+290
225
t
INTH, Delay from Rising Edge of
RD to Rising Edge of INT
INTHWR, Delay from Rising Edge of
Figures 2, 3, 4
=
CL 50 pFc
=
t
Figure 5, CL 50 pF
175
270
ns
WR to Rising Edge of INT
tRDY, Delay from CS to RDY
=
=
0
Figure 2, CL 50 pF, Pin 7
50
20
100
50
ns
ns
ns
t
t
ID, Delay from INT to Output Valid
RI, Delay from RD to INT
Figure 5
=
<
Pin 7 VCC, tRD tI
200
290
Figure 3
tP, Delay from End of Conversion
to Next Conversion
Figures 2, 3, 4, 5
(Note 4) See Graph
500
ns
Slew Rate, Tracking
0.1
45
5
V/µs
pF
C
C
C
VIN, Analog Input Capacitance
OUT, Logic Output Capacitance
IN, Logic Input Capacitance
pF
5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4: Accuracy may degrade if t
WR
or t
RD
is shorter than the minimum value specified. See Accuracy vs t
and Accuracy vs t
graphs.
>
V ) the absolute value of current at that pin should be limited to
WR
RD
−
+
<
Note 5: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN IN
V or V
IN
1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four.
Note 6: Typicals are at 25˚C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF discharaged through a 1.5 kΩ resistor.
5
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TRI-STATE Test Circuits and Waveforms
t1H
DS005501-4
DS005501-3
=
t
20 ns
r
t0H
DS005501-6
=
t
20 ns
r
DS005501-5
Timing Diagrams
DS005501-7
Note: On power-up the state of INT can be high or low.
FIGURE 2. RD Mode (Pin 7 is Low)
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6
Timing Diagrams (Continued)
DS005501-8
<
FIGURE 3. WR-RD Mode (Pin 7 is High and tRD tI)
DS005501-9
>
FIGURE 4. WR-RD Mode (Pin 7 is High and tRD tI)
DS005501-10
FIGURE 5. WR-RD Mode (Pin 7 is High)
Stand-Alone Operation
7
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Typical Performance Characteristics
Logic Input Threshold
Voltage vs Supply Voltage
Conversion Time (RD Mode)
vs Temperature
Power Supply Current vs
Temperature (not including
reference ladder)
DS005501-34
DS005501-35
DS005501-36
Accuracy vs tWR
Accuracy vs tRD
Accuracy vs tp
DS005501-39
DS005501-37
DS005501-38
Accuracy vs VREF
[VREF=VREF(+)-VREF(-)]
tI, Internal Time Delay vs
Temperature
Output Current vs
Temperature
DS005501-42
DS005501-40
DS005501-41
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8
Description of Pin Functions
Pin Name
INT
Function
9
WR-RD Mode
Pin Name
Function
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT will go
=
1
2
3
4
5
6
VIN
Analog input; range GND≤VIN≤VCC
DB0
DB1
DB2
DB3
TRI-STATE data output — bit 0 (LSB)
TRI-STATE data output — bit 1
TRI-STATE data output — bit 2
TRI-STATE data output — bit 3
WR-RD Mode
z
low, 800 ns (the preset internal time
out, tI) after the rising edge of WR (see
Figure 4 ); or INT will go low after the
falling edge of RD , if RD goes low prior
to the 800 ns time out (see Figure 3).
INT is reset by the rising edge of RD or
CS (see Figures 3, 4 ).
WR
/RDY
WR: With CS low, the conversion is
started on the falling edge of WR.
Approximately 800 ns (the preset internal
time out, tI) after the WR rising edge, the
result of the conversion will be strobed
into the output latch, provided that RD
does not occur prior to this time out (see
Figures 3, 4 ).
RD Mode
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT is reset
by the rising edge of RD or CS (see
Figure 2 ).
RD Mode
10 GND
Ground
RDY: This is an open drain output (no
internal pull-up device). RDY will go low
after the falling edge of CS; RDY will go
TRI-STATE when the result of the
conversion is strobed into the output
latch. It is used to simplify the interface
to a microprocessor system (see Figure
2 ).
11
V
REF(−)
The bottom of resistor ladder, voltage
range: GND≤VREF(−)≤VREF(+) (Note 5)
12
V
REF(+)
The top of resistor ladder, voltage range:
VREF(−)≤VREF(+)≤VCC (Note 5)
13 CS
CS must be low in order for the RD or
WR to be recognized by the converter.
14 DB4
15 DB5
16 DB6
17 DB7
18 OFL
TRI-STATE data output — bit 4
TRI-STATE data output — bit 5
TRI-STATE data output — bit 6
TRI-STATE data output — bit 7 (MSB)
7
8
Mode
RD
Mode: Mode selection input — it is
internally tied to GND through a 50 µA
current source.
RD Mode: When mode is low
WR-RD Mode: When mode is high
WR-RD Mode
Overflow output — If the analog input is
higher than the VREF(+), OFL will be low
at the end of conversion. It can be used
to cascade 2 or more devices to have
more resolution (9, 10-bit). This output is
always active and does not go into
TRI-STATE as DB0–DB7 do.
With CS low, the TRI-STATE data
outputs (DB0-DB7) will be activated
when RD goes low (see Figure 5 ). RD
can also be used to increase the speed
of the converter by reading data prior to
19 NC
20 VCC
No connection
z
the preset internal time out (tI, 800 ns).
Power supply voltage
If this is done, the data result transferred
to output latch is latched after the falling
edge of the RD (see Figures 3, 4 ).
RD Mode
With CS low, the conversion will start
with RD going low, also RD will enable
the TRI-STATE data outputs at the
completion of the conversion. RDY going
TRI-STATE and INT going low indicates
the completion of the conversion (see
Figure 2 ).
1.0 Functional Description
1.1 GENERAL OPERATION
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The ADC0820 uses two 4-bit flash A/D converters to make
an 8-bit measurement (Figure 1 ). Each flash ADC is made
up of 15 comparators which compare the unknown input to a
reference ladder to get a 4-bit result. To take a full 8-bit read-
ing, one flash conversion is done to provide the 4 most sig-
nificant data bits (via the MS flash ADC). Driven by the 4
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
9
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by connecting the second input on each capacitor and open-
ing all of the other switches (S switches). The change in volt-
age at the inverter’s input, as a result of the change in charge
on each input capacitor, will now depend on both input signal
differences.
1.0 Functional Description (Continued)
ladder for the A/D as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
which most closely approximates the analog input. In addi-
tion, the “sampled-data” comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.
1.2 THE SAMPLED-DATA COMPARATOR
Each comparator in the ADC0820 consists of a CMOS in-
verter with a capacitively coupled input (Figures 6, 7 ). Ana-
log switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverter’s input and out-
put. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the com-
parator, and another for making the comparison.
DS005501-12
=
• V
V
B
=
O
• V on C V1−V
B
=
=
• C
stray input node capacitor
inverter input bias voltage
S
B
• V
Zeroing Phase
In the first cycle, one input switch and the inverter’s feedback
switch (Figure 6 ) are closed. In this interval, C is charged to
the connected input (V1) less the inverter’s bias voltage (VB,
approximately 1.2V). In the second cycle (Figure 7 ), these
two switches are opened and the other (V2) input’s switch is
closed. The input capacitor now subtracts its stored voltage
from the second input and the difference is amplified by the
inverter’s open loop gain. The inverter’s input (VB') becomes
FIGURE 6. Sampled-Data Comparator
DS005501-13
and the output will go high or low depending on the sign of
VB'−VB.
The actual circuitry used in the ADC0820 is a simple but im-
portant expansion of the basic comparator described above.
By adding a second capacitor and another set of switches to
the input (Figure 8 ), the scheme can be expanded to make
dual differential comparisons. In this circuit, the feedback
switch and one input switch on each capacitor (Z switches)
are closed in the zeroing cycle. A comparison is then made
Compare Phase
FIGURE 7. Sampled-Data Comparator
DS005501-45
DS005501-14
FIGURE 8. ADC0820 Comparator (from MS Flash ADC)
1.3 ARCHITECTURE
after at least 600 ns, the output from the first set of compara-
tors (the first flash) is decoded and latched. At this point the
two 4-bit converters change modes and the LS (least signifi-
cant) flash ADC enters its compare cycle. No less than 600
ns later, the RD line may be pulled low to latch the lower 4
data bits and finish the 8-bit conversion. When RD goes low,
the flash A/Ds change state once again in preparation for the
next conversion.
In the ADC0820, one bank of 15 comparators is used in each
4-bit flash A/D converter (Figure 12 ). The MS (most signifi-
cant) flash ADC also has one additional comparator to detect
input overrange. These two sets of comparators operate al-
ternately, with one group in its zeroing cycle while the other
is comparing.
When a typical conversion is started, the WR line is brought
low. At this instant the MS comparators go from zeroing to
comparison mode (Figure 11 ). When WR is returned high
Figure 11 also outlines how the converter’s interface timing
relates to its analog input (VIN). In WR-RD mode, VIN is mea-
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10
conversion time is desired, the processor need not wait for
INT and can exercise a read after only 600 ns (Figure 9 ). If
this is done, INT will immediately go low and data will appear
at the outputs.
1.0 Functional Description (Continued)
sured while WR is low. In RD mode, sampling occurs during
the first 800 ns of RD. Because of the input connections to
the ADC0820’s LS and MS comparators, the converter has
the ability to sample VIN at one instant (Section 2.4), despite
the fact that two separate 4-bit conversions are being done.
More specifically, when WR is low the MS flash is in compare
mode (connected to VIN), and the LS flash is in zero mode
(also connected to VIN). Therefore both flash ADCs sample
VIN at the same time.
1.4 DIGITAL INTERFACE
The ADC0820 has two basic interface modes which are se-
lected by strapping the MODE pin high or low.
RD Mode
DS005501-17
With the MODE pin grounded, the converter is set to Read
mode. In this configuration, a complete conversion is done
by pulling RD low until output data appears. An INT line is
provided which goes low at the end of the conversion as well
as a RDY output which can be used to signal a processor
that the converter is busy or can also serve as a system
Transfer Acknowledge signal.
<
FIGURE 9. WR-RD Mode (Pin 7 is High and tRD tI)
RD Mode (Pin 7 is Low)
DS005501-18
>
FIGURE 10. WR-RD Mode (Pin 7 is High and tRD tI)
Stand-Alone
For stand-alone operation in WR-RD mode, CS and RD can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WR’s rising
edge.
DS005501-16
When in RD mode, the comparator phases are internally trig-
gered. At the falling edge of RD, the MS flash converter goes
from zero to compare mode and the LS ADC’s comparators
enter their zero cycle. After 800 ns, data from the MS flash is
latched and the LS flash ADC enters compare mode. Follow-
ing another 800 ns, the lower 4 bits are recovered.
WR-RD Mode (Pin 7 is High) Stand-Alone Operation
WR then RD Mode
With the MODE pin tied high, the A/D will be set up for the
WR-RD mode. Here, a conversion is started with the WR in-
put; however, there are two options for reading the output
data which relate to interface timing. If an interrupt driven
scheme is desired, the user can wait for INT to go low before
reading the conversion result (Figure 10 ). INT will typically
go low 800 ns after WR’s rising edge. However, if a shorter
DS005501-19
11
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1.0 Functional Description (Continued)
DS005501-20
Note: MS means most significant
LS means least significant
FIGURE 11. Operating Sequence (WR-RD Mode)
OTHER INTERFACE CONSIDERATIONS
Since the MS flash ADC enters its zeroing phase at the end
of a conversion (Section 1.3), a new conversion cannot be
started until this phase is complete. The minimum spec for
this time (tP, Figures 2, 3, 4, 5 ) is 500 ns.
In order to maintain conversion accuracy, WR has a maxi-
mum width spec of 50 µs. When the MS flash ADC’s
sampled-data comparators (Section 1.2) are in comparison
mode (WR is low), the input capacitors (C, Figure 8 ) must
hold their charge. Switch leakage and inverter bias current
can cause errors if the comparator is left in this phase for too
long.
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12
Detailed Block Diagram
DS005501-15
FIGURE 12.
13
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The equivalent input circuit of the ADC0820 is shown in Fig-
ure 14. When a conversion starts (WR low, WR-RD mode),
all input switches close, connecting VIN to thirty-one 1 pF ca-
pacitors. Although the two 4-bit flash circuits are not both in
their compare cycle at the same time, VIN still sees all input
capacitors at once. This is because the MS flash converter is
connected to the input during its compare interval and the LS
flash is connected to the input during its zeroing phase (Sec-
tion 1.3). In other words, the LS ADC uses VIN as its
zero-phase input.
2.0 Analog Considerations
2.1 REFERENCE AND INPUT
The two VREF inputs of the ADC0820 are fully differential and
define the zero to full-scale input range of the A to D con-
verter. This allows the designer to easily vary the span of the
analog input since this range will be equivalent to the voltage
difference between
V
IN(+) and VIN(−). By reducing
=
V
REF(VREF VREF(+)−VREF(−)) to less than 5V, the sensitivity
=
of the converter can be increased (i.e., if VREF 2V then 1
The input capacitors must charge to the input voltage
through the on resistance of the analog switches (about 5 kΩ
to 10 kΩ). In addition, about 12 pF of input stray capacitance
must also be charged. For large source resistances, the ana-
log input can be modeled as an RC network as shown in Fig-
ure 15. As RS increases, it will take longer for the input ca-
pacitance to charge.
=
LSB 7.8 mV). The input/reference arrangement also facili-
tates ratiometric operation and in many cases the chip power
supply can be used for transducer power as well as the VREF
source.
This reference flexibility lets the input span not only be varied
but also offset from zero. The voltage at VREF(−) sets the in-
put level which produces a digital output of all zeroes.
Though VIN is not itself differential, the reference design af-
fords nearly differential-input capability for most measure-
ment applications. Figure 13 shows some of the configura-
tions that are possible.
In RD mode, the input switches are closed for approximately
800 ns at the start of the conversion. In WR-RD mode, the
time that the switches are closed to allow this charging is the
time that WR is low. Since other factors force this time to be
at least 600 ns, input time constants of 100 ns can be ac-
commodated without special consideration. Typical total in-
put capacitance values of 45 pF allow RS to be 1.5 kΩ with-
out lengthening WR to give VIN more time to settle.
2.2 INPUT CURRENT
Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The A/D’s sampled-data com-
parators take varying amounts of input current depending on
which cycle the conversion is in.
External Reference 2.5V Full-Scale
Power Supply as Reference
Input Not Referred to GND
DS005501-21
DS005501-22
DS005501-23
FIGURE 13. Analog Input Options
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14
2.4 INHERENT SAMPLE-HOLD
2.0 Analog Considerations (Continued)
Another benefit of the ADC0820’s input mechanism is its
ability to measure a variety of high speed signals without the
help of an external sample-and-hold. In a conventional SAR
type converter, regardless of its speed, the input must re-
1
main at least
⁄2 LSB stable throughout the conversion pro-
cess if full accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally
sampled, and held stationary during the conversion.
Sampled-data comparators, by nature of their input switch-
ing, already accomplish this function to a large degree (Sec-
tion 1.2). Although the conversion time for the ADC0820 is
1
1.5 µs, the time through which VIN must be
⁄2 LSB stable is
much smaller. Since the MS flash ADC uses VIN as its “com-
pare” input and the LS ADC uses VIN as its “zero” input, the
ADC0820 only “samples” VIN when WR is low (Sections 1.3
and 2.2). Even though the two flashes are not done simulta-
neously, the analog signal is measured at one instant. The
value of VIN approximately 100 ns after the rising edge of
WR (100 ns due to internal logic prop delay) will be the mea-
sured value.
DS005501-24
FIGURE 14.
Input signals with slew rates typically below 100 mV/µs can
be converted without error. However, because of the input
time constants, and charge injection through the opened
comparator input switches, faster signals may cause errors.
Still, the ADC0820’s loss in accuracy for a given increase in
signal slope is far less than what would be witnessed in a
conventional successive approximation device. An SAR type
converter with a conversion time as fast as 1 µs would still
not be able to measure a 5V 1 kHz sine wave without the aid
of an external sample-and-hold. The ADC0820, with no such
help, can typically measure 5V, 7 kHz waveforms.
DS005501-25
FIGURE 15.
2.3 INPUT FILTERING
It should be made clear that transients in the analog input
signal, caused by charging current flowing into VIN, will not
degrade the A/D’s performance in most cases. In effect the
ADC0820 does not “look” at the input when these transients
occur. The comparators’ outputs are not latched while WR is
low, so at least 600 ns will be provided to charge the ADC’s
input capacitance. It is therefore not necessary to filter out
these transients by putting an external cap on the VIN termi-
nal.
15
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3.0 Typical Applications
8-Bit Resolution Configuration
DS005501-26
9-Bit Resolution Configuration
DS005501-27
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16
3.0 Typical Applications (Continued)
Telecom A/D Converter
Multiple Input Channels
DS005501-28
=
±
•
•
•
VIN 3 kHz max 4VP
No track-and-hold needed
Low power consumption
DS005501-29
8-Bit 2-Quadrant Analog Multiplier
DS005501-30
17
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3.0 Typical Applications (Continued)
Fast Infinite Sample-and-Hold
DS005501-31
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18
3.0 Typical Applications (Continued)
19
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Physical Dimensions inches (millimeters) unless otherwise noted
Hermetic Dual-In-Line Package (J)
Order Number ADC0820CCJ
NS Package Number J20A
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20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
SO Package (M)
Order Number ADC0820BCWM, ADC0820CCWM or ADC0820CIWM
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number ADC0820BCN or ADC0820CCN
NS Package Number N20A
21
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Chip Carrier Package (V)
Order Number ADC0820BCV
NS Package Number V20A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
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Email: sea.support@nsc.com
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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