ADC12130_06
更新时间：2024-09-18 06:51:38
品牌：NSC
描述：Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
概述
数据手册ADC12130_06 概述
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold 自校准12位加符号位串行I / OA / D转换器，带有MUX和采样/保持
ADC12130_06 数据手册
通过下载ADC12130_06数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载April 2006
ADC12130/ADC12132/ADC12138
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
General Description
NOTE: All versions of the ADC12132 are obsolete and
shown here for reference only.
Features
n Serial I/O (MICROWIRE, SPI and QSPI Compatible)
n Power down mode
n Programmable acquisition time
The ADC12130, ADC12132 and ADC12138 are 12-bit plus
sign successive approximation A/D converters with serial I/O
and configurable input multiplexer. The ADC12132 and
ADC12138 have a 2 and an 8 channel multiplexer, respec-
tively. The differential multiplexer outputs and A/D inputs are
available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2
pins. The ADC12130 has a two channel multiplexer with the
multiplexer outputs and A/D inputs internally connected. The
ADC12130 family is tested and specified with a 5 MHz clock.
On request, these A/Ds go through a self calibration process
that adjusts linearity, zero and full-scale errors to typically
less than 1 LSB each.
n Variable digital output word length and format
n No zero or full scale adjustment required
n 0V to 5V analog input range with single 5V power
supply
Key Specifications
Resolution
12-bit plus sign
8.8 µs (max)
j
j
j
j
j
12-Bit plus sign conversion time
12-Bit plus sign throughput time
Integral Linearity Error
Single Supply
14 µs (max)
2 LSB (max)
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-
differential modes. A fully differential unipolar analog input
range (0V to +5V) can be accommodated with a single +5V
supply. In the differential modes, valid outputs are obtained
even when the negative inputs are greater than the positive
because of the 12-bit plus sign output data format.
3.3V or 5V 10%
Power Consumption
+3.3V
15 mW (max)
40 µW (typ)
+3.3V power down
+5V
33 mW (max)
100 µW (typ)
The ADC12132 is obsolete and described in this document
for reference only.
+5V power down
The serial I/O is configured to comply with NSC MICROW-
™
IRE . For voltage references, see the LM4040, LM4050 or
Applications
n Pen-based computers
n Digitizers
LM4041.
n Global positioning systems
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
™
COPS microcontrollers, HPC and MICROWIRE are trademarks of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS012079
www.national.com
ADC12138 Simplified Block Diagram
01207901
Connection Diagrams
20-Pin SSOP Package
16-Pin Dual-In-Line and
Wide Body SO Packages
01207902
Top View
01207947
Device Obsolete. Shown for reference only.
Top View
www.national.com
2
Connection Diagrams (Continued)
28-Pin Dual-In-Line, SSOP and
Wide Body SO Packages
01207903
Top View
Ordering Information
Industrial Temperature Range
−40˚C ≤ TA ≤ +85˚C
ADC12130CIN
NS Package Number
N16E, Dual-In-Line
M16B, Wide Body SO
M16B, Wide Body SO - Tape & Reel
MSA20, SSOP
ADC12130CIWM
ADC12130CIWMX
ADC12132CIMSA *
ADC12132CIMSAX *
ADC12138CIN
MSA20, SSOP - Tape & Reel
N28B, Dual-In-Line
ADC12138CIWM
M28B
ADC12138CIWMX
ADC12138CIMSA
ADC12138CIMSA
M28B - Tape & Reel
MSA28, SSOP
MSA28, SSOP - Tape & Reel
* The ADC12132 is obsolete and shown in this document for reference only.
and the mode of operation for the A/D. With CS
Pin Descriptions
low, the falling edge of SCLK shifts the data
resulting from the previous ADC conversion out
on DO, with the exception of the first bit of data.
When CS is low continuously, the first bit of the
data is clocked out on the rising edge of EOC
(end of conversion). When CS is toggled, the
falling edge of CS always clocks out the first bit
of data. CS should be brought low when SCLK
is low. The rise and fall times of the clock edges
should not exceed 1 µs.
CCLK
The clock applied to this input controls the suc-
cessive approximation conversion time interval
and the acquisition time. The rise and fall times
of the clock edges should not exceed 1 µs.
SCLK
This is the serial data clock input. The clock
applied to this input controls the rate at which
the serial data exchange occurs. The rising
edge loads the information at the DI pin into the
multiplexer address and mode select shift reg-
ister. This address controls which channel of
the analog input multiplexer (MUX) is selected
3
www.national.com
(Table 4) such as 12-bit conversion, Auto Cal,
Auto Zero etc. When this pin is high the ADC is
placed in the read data only mode. While in the
read data only mode, bringing CS low and puls-
ing SCLK will only clock out on DO any data
stored in the ADCs output shift register. The
data on DI will be neglected. A new conversion
will not be started and the ADC will remain in
the mode and/or configuration previously pro-
grammed. Read data only cannot be performed
while a conversion, Auto-Cal or Auto-Zero are
in progress.
Pin Descriptions (Continued)
DI
This is the serial data input pin. The data ap-
plied to this pin is shifted at the rising edge of
SCLK into the multiplexer address and mode
select register. Table 2 through Table 4 show
the assignment of the multiplexer address and
the mode select data.
DO
The data output pin. This pin is an active push/
pull output when CS is low. When CS is high,
this output is TRI-STATE®. The A/D conversion
result (DB0–DB12) and converter status data
are clocked out at the falling edge of SCLK on
this pin. The word length and format of this
result can vary (see Table 1). The word length
and format are controlled by the data shifted
into the multiplexer address and mode select
register (see Table 4).
PD
This is the power down pin. When PD is high
the A/D is powered down; when PD is low the
A/D is powered up. The A/D takes a maximum
of 700 µs to power up after the command is
given.
CH0–CH7 These are the analog inputs of the MUX. A
channel input is selected by the address infor-
mation at the DI pin, which is loaded on the
rising edge of SCLK into the address register
(see Table 2 and Table 3).
EOC
CS
This pin is an active push/pull output and indi-
cates the status of the ADC12130/2/8. When
low, it signals that the A/D is busy with a con-
version, auto-calibration, auto-zero or power
down cycle. The rising edge of EOC signals the
end of one of these cycles.
The voltage applied to these inputs should not
exceed VA+ or go below GND. Exceeding this
range on an unselected channel will corrupt the
reading of a selected channel.
This is the chip select pin. When a logic low is
applied to this pin, the rising edge of SCLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE.
With CS low, the falling edge of SCLK shifts the
data resulting from the previous ADC conver-
sion out on DO, with the exception of the first bit
of data. When CS is low continuously, the first
bit of the data is clocked out on the rising edge
of EOC (end of conversion). When CS is
toggled, the falling edge of CS always clocks
out the first bit of data. CS should be brought
low when SCLK is low. The falling edge of CS
resets a conversion in progress and starts the
sequence for a new conversion. When CS is
brought back low during a conversion, that con-
version is prematurely terminated. The data in
the output latches may be corrupted. Therefore,
when CS is brought back low during a conver-
sion in progress the data output at that time
should be ignored. CS may also be left continu-
ously low. In this case it is imperative that the
correct number of SCLK pulses be applied to
the ADC in order to remain synchronous. After
the ADC supply power is applied it expects to
see 13 clock pulses for each I/O sequence. The
number of clock pulses the ADC expects is the
same as the digital output word length. This
word length can be modified by the data shifted
in at the DO pin. Table 4 details the data
required.
COM
This pin is another analog input pin. It is used
as a pseudo ground when the analog multi-
plexer is single-ended.
MUXOUT1, MUXOUT2
These
pins.
are
the
multiplexer
output
A/DIN1,
A/DIN2
These are the converter input pins. MUXOUT1
is usually tied to A/DIN1. MUXOUT2 is usually
tied to A/DIN2. If external circuitry is placed
between MUXOUT1 and A/DIN1, or MUXOUT2
and A/DIN2 it may be necessary to protect
these pins. The voltage at these pins should not
+
exceed VA or go below AGND (see Figure 6).
VREF
+
−
This is the positive analog voltage reference
input. In order to maintain accuracy, the voltage
range of VREF (VREF = VREF+ − VREF−) is 1 VDC
to 5.0 VDC and the voltage at VREF+ cannot
exceed VA+. See Figure 5 for recommended
bypassing.
VREF
The negative voltage reference input. In order
to maintain accuracy, the voltage at this pin
must not go below GND or exceed VA+. (See
Figure 5).
VA+, VD+
These are the analog and digital power supply
+
+
pins. VA and VD are not connected together
on the chip. These pins should be tied to the
same power supply and bypassed separately
(see Figure 5). The operating voltage range of
DOR
This is the data output ready pin. This pin is an
active push/pull output. It is low when the con-
version result is being shifted out and goes high
to signal that all the data has been shifted out.
VA+ and VD+ is 3.0 VDC to 5.5 VDC
.
DGND
AGND
This is the digital ground pin (see Figure 5).
This is the analog ground pin (see Figure 5).
CONV
A logic low is required on this pin to program
any mode or change the ADC’s configuration
as listed in the Mode Programming Table
www.national.com
4
Absolute Maximum Ratings
(Notes 1, 2)
Operating Ratings (Notes 1, 2)
Operating Temperature Range
TMIN ≤ TA ≤ TMAX
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
−40˚C ≤ TA ≤ +85˚C
+3.0V to +5.5V
≤ 100 mV
Supply Voltage (V+ = VA+ = VD+)
|VA+ − VD+|
Positive Supply Voltage
VREF
+
−
0V to VA+
(V+ = VA+ = VD+)
6.5V
VREF
0V to (VREF+ −1V)
1V to VA+
Voltage at Inputs and Outputs
except CH0–CH7 and COM
Voltage at Analog Inputs
CH0–CH7 and COM
VREF (VREF+ − VREF−)
−0.3V to V+ +0.3V
VREF Common Mode Voltage Range
[(VREF+) − (VREF−)] / 2
A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 Voltage Range
A/D IN Common Mode
Voltage Range
0.1 VA+ to 0.6 VA+
0V to VA+
GND −5V to V+ +5V
300 mV
|VA+ − VD+|
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
TA = 25˚C (Note 4)
30 mA
120 mA
[(VIN+) − (VIN−)] / 2
0V to VA+
500 mW
1500V
260˚C
ESD Susceptibility (Note 5)
Human Body Model
Package Thermal Resistance
Thermal
Part Number
Soldering Information
Resistance (θJA
)
N Packages (10 seconds)
SO Package (Note 6):
Vapor Phase (60 seconds)
Infrared (15 seconds)
ADC12130CIN
53˚C/W
70˚C/W
134˚C/W
64˚C/W
40˚C/W
97˚C/W
50˚C/W
ADC12130CIWM
ADC12132CIMSA *
ADC12132CIWM *
ADC121038CIN
ADC121038CIMSA
ADC12138CIWM
215˚C
220˚C
Storage Temperature
−65˚C to +150˚C
* The ADC12132 is obsolete and is shown for reference only.
Converter Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V
common-mode voltage) or (V+ = VA+ = VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode
−
+
voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF and VREF ≤ 25Ω, fCK = fSK
5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25˚C. (Notes 7, 8, 9)
=
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
Symbol
Parameter
Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12 + sign Bits (min)
ILE
Integral Linearity Error
Differential Non-Linearity
Positive Full-Scale Error
Negative Full-Scale Error
After Auto-Cal (Notes 12, 18)
After Auto-Cal
1/2
2
LSB (max)
LSB (max)
LSB (max)
LSB (max)
DNL
1.5
3.0
3.0
After Auto-Cal (Notes 12, 18)
After Auto-Cal (Notes 12, 18)
After Auto-Cal (Notes 5, 18)
VIN(+) = VIN(−) = 2.048V
After Auto-Cal (Note 15)
After Auto-Cal (Notes 12, 13, 14)
1/2
1/2
Offset Error
1/2
2
LSB (max)
DC Common Mode Error
Total Unadjusted Error
2
1
LSB (max)
LSB
TUE
Multiplexer Chan-to-Chan Matching V+ = +5V 10%, VREF = +4.096V
0.05
LSB
Power Supply Sensitivity
Offset Error
0.5
0.5
0.5
0.5
LSB
LSB
LSB
LSB
+ Full-Scale Error
− Full-Scale Error
Integral Linearity Error
5
www.national.com
Converter Electrical Characteristics (Continued)
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V
common-mode voltage) or (V+ = VA+ = VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode
−
+
voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF and VREF ≤ 25Ω, fCK = fSK
5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25˚C. (Notes 7, 8, 9)
=
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
Symbol
Parameter
Conditions
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
+
fIN = 1 kHz, VIN = 5 VPP, VREF = 5.0V
69.4
68.3
65.7
31
dB
dB
+
S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN = 5 VPP, VREF = 5.0V
fIN = 40 kHz, VIN = 5 VPP, VREF+ = 5.0V
dB
−3 dB Full Power Bandwidth
VIN = 5 VPP, where S/(N+D) drops 3 dB
kHz
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
+
fIN = 1 kHz, VIN
=
5V, VREF = 5.0V
77.0
73.9
67.0
40
dB
dB
+
S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN
fIN = 40 kHz, VIN
=
=
5V, VREF = 5.0V
+
5V, VREF = 5.0V
dB
−3 dB Full Power Bandwidth
VIN
=
5V, where S/(N+D) drops 3 dB
kHz
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
CREF
CA/D
Reference Input Capacitance
A/DIN1 and A/DIN2 Analog Input
Capacitance
85
75
pF
pF
A/DIN1 and A/DIN2 Analog Input
Leakage Current
VIN = +5.0V or VIN = 0V
0.1
µA
GND − 0.05
(VA+) + 0.05
V (min)
V (max)
CH0–CH7 and COM Input Voltage
CH0–CH7 and COM Input
Capacitance
CCH
10
20
pF
pF
µA
CMUXOUT MUX Output Capacitance
On Channel = 5V and
Off Channel = 0V
−0.01
Off Channel Leakage (Note 16)
CH0–CH7 and COM Pins
On Channel = 0V and
Off Channel = 5V
0.01
0.01
−0.01
0.01
850
5
µA
µA
On Channel = 5V and
Off Channel = 0V
On Channel Leakage (Note 16)
CH0–CH7 and COM Pins
On Channel = 0V and
Off Channel = 5V
µA
MUXOUT1 and MUXOUT2 Leakage
Current
VMUXOUT = 5.0V or VMUXOUT = 0V
µA
VIN = 2.5V and
RON
MUX On Resistance
1900
Ω (max)
%
VMUXOUT = 2.4V
VIN = 2.5V and
RON Matching Channel to Channel
VMUXOUT = 2.4V
VIN = 5 VPP, fIN = 40 kHz
Channel-to-Channel Crosstalk
MUX Bandwidth
−72
90
dB
kHz
www.national.com
6
DC and Logic Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+ ≤ 25Ω, fCK
= fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all
other limits TA = TJ = 25˚C. (Notes 7, 8, 9)
V+ = VA+ = V+ = VA+ =
Typical VD+ = 3.3V
VD+ = 5V
Limits
Units
(Limits)
Symbol
Parameter
Conditions
(Note 10)
Limits
(Note 11)
(Note 11)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
VIN(1)
VIN(0)
IIN(1)
IIN(0)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical ′“0” Input Current
VA+ = VD+ = V+ +10%
VA+ = VD+ = V+ −10%
VIN = V+
2.0
0.8
2.0
0.8
V (min)
V (max)
µA (max)
µA (min)
0.005
1.0
1.0
VIN = 0V
−0.005
−1.0
−1.0
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
VA+ = VD+ = V+ − 10%,
2.4
2.9
0.4
2.4
4.25
0.4
V (min)
V (min)
V (max)
IOUT = −360 µA
VA+ = VD+ = V+ − 10%,
IOUT = −10 µA
VA+ = VD+ = V+ − 10%
IOUT = 1.6 mA
VOUT = 0V
VOUT(1) Logical “1” Output Voltage
VOUT(0) Logical “0” Output Voltage
−0.1
−0.1
−14
16
−3.0
3.0
−3.0
3.0
µA (max)
µA (max)
mA
IOUT
TRI-STATE Output Current
VOUT = V+
+ISC
−ISC
Output Short Circuit Source Current
Output Short Circuit Sink Current
VOUT = 0V
VOUT = VD+
mA
POWER SUPPLY CHARACTERISTICS
Awake (Active)
1.5
3.0
2.5
4.0
mA (max)
µA
CS = HIGH, Powered Down,
CCLK on
600
20
ID+
Digital Supply Current
CS = HIGH, Powered Down,
CCLK off
µA
mA (max)
µA
Awake (Active)
CS = HIGH, Powered Down,
CCLK on
10
IA+
Positive Analog Supply Current
Reference Input Current
CS = HIGH, Powered Down,
CCLK off
0.1
µA
µA
µA
CS = HIGH, Powered Down,
CCLK on
70
IREF
CS = HIGH, Powered Down,
CCLK off
0.1
7
www.national.com
AC Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+ ≤ 25Ω, fCK
= fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all
other limits TA = TJ = 25˚C. (Note 17)
Typical
(Note 10)
Symbol
fCK
Parameter
Conditions
Limits (Note 11)
Units (Limits)
10
1
5
MHz (max)
MHz (min)
MHz (max)
Hz (min)
% (min)
% (max)
% (min)
% (max)
(max)
Conversion Clock (CCLK) Frequency
Serial Data Clock SCLK Frequency
Conversion Clock Duty Cycle
Serial Data Clock Duty Cycle
Conversion Time
10
0
5
fSK
40
60
40
60
44(tCK
)
44(tCK
)
tC
12-Bit + Sign or 12-Bit
6 Cycles Programmed
8.8
µs (max)
(min)
6(tCK
10(tCK
18(tCK
34(tCK
)
6(tCK
7(tCK
1.2
)
)
(max)
µs (min)
µs (max)
(min)
1.4
)
)
)
10(tCK
11(tCK
2.0
)
)
(max)
10 Cycles Programmed
18 Cycles Programmed
34 Cycles Programmed
µs (min)
µs (max)
(min)
2.2
tA
Acquisition Time (Note 19)
18(tCK
19(tCK
3.6
)
)
(max)
µs (min)
µs (max)
(min)
3.8
34(tCK
35(tCK
6.8
)
)
(max)
µs (min)
µs (max)
(max)
7.0
4944(tCK
76(tCK
2(tCK
)
4944(tCK
)
tCAL
tAZ
Self-Calibration Time
Auto-Zero Time
988.8
µs (max)
(max)
)
76(tCK
)
15.2
µs (max)
(min)
)
2(tCK
3(tCK
0.40
)
)
(max)
Self-Calibration or Auto-Zero
tSYNC
Synchronization Time from DOR
µs (min)
µs (max)
0.60
DOR High Time when CS is Low
Continuously for Read Data and
Software Power Up/Down
9(tSK
)
)
9(tSK
)
(max)
tDOR
1.8
µs (max)
8(tSK
8(tSK
1.6
)
(max)
tCONV
CONV Valid Data Time
µs (max)
www.national.com
8
AC Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+ ≤ 25Ω, fCK
= fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all
other limits TA = TJ = 25˚C. (Note 17) (Continued)
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
Symbol
tHPU
Parameter
Conditions
Hardware Power-Up Time, Time from PD
Falling Edge to EOC Rising Edge
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to EOC
Rising Edge
500
500
25
700
700
µs (max)
µs (max)
tSPU
Access Time Delay from CS Falling Edge
to DO Data Valid
tACC
tSET-UP
tDELAY
t1H, t0H
tHDI
60
50
5
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
ns (min)
Set-Up Time of CS Falling Edge to Serial
Data Clock Rising Edge
Delay from SCLK Falling Edge to CS
Falling Edge
0
70
5
Delay from CS Rising Edge to DO
TRI-STATE
RL = 3k, CL = 100 pF
100
15
10
DI Hold Time from Serial Data Clock
Rising Edge
DI Set-Up Time from Serial Data Clock
Rising Edge
tSDI
5
DO Hold Time from Serial Data Clock
Falling Edge
35
65
5
ns (max)
ns (min)
tHDO
tDDO
tRDO
tFDO
tCD
RL = 3k, CL = 100 pF
Delay from Serial Data Clock Falling Edge
to DO Data Valid
50
90
ns (max)
DO Rise Time, TRI-STATE to High DO
Rise Time, Low to High
10
10
15
15
40
40
40
40
ns (max)
ns (max)
ns (max)
ns (max)
RL = 3k, CL = 100 pF
RL = 3k, CL = 100 pF
DO Fall Time, TRI-STATE to Low DO Fall
Time, High to Low
Delay from CS Falling Edge to DOR
Falling Edge
45
45
80
80
ns (max)
ns (max)
Delay from Serial Data Clock Falling Edge
to DOR Rising Edge
tSD
CIN
Capacitance of Logic Inputs
Capacitance of Logic Outputs
20
20
pF
pF
COUT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
<
>
V + or V +), the current at that pin should be limited to 30 mA.
Note 3: When the input voltage (V ) at any pin exceeds the power supplies (V
GND or V
IN
IN
IN
A
D
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T max, θ and the ambient temperature, T . The maximum
J
JA
A
allowable power dissipation at any temperature is P = (T max − T )/θ or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
D
J
A
JA
T max = 150˚C.
J
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V + or 5V below GND
A
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V + or below GND by more than 50 mV. As an example, if V + is 4.5 V , full-scale input voltage must be ≤4.55
A
A
DC
V
to ensure accurate conversions.
DC
9
www.national.com
AC Electrical Characteristics (Continued)
01207904
+
Note 8: To guarantee accuracy, it is required that the V + and V + be connected together to the same power supply with separate bypass capacitors at each V
A
D
pin.
Note 9: With the test condition for V
(V
+ − V
−) given as +4.096V, the 12-bit LSB is 1.0 mV. For V
= 2.5V, the 12-bit LSB is 610 µV.
REF
REF
REF
REF
Note 10: Typical figures are at T = T = 25˚C and represent most likely parametric norm.
J
A
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions
between −1 to 0 and 0 to +1 (see Figure 4).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V = 0.4V for a falling edge and V = 2.4V for a rising edge. TRI-STATE output voltage is forced
OL
OL
to 1.4V.
Note 18: The ADC12130 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will
result in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then t is 6, 10, 18 or 34 clock periods minimum and maximum.
A
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
01207905
FIGURE 1. Transfer Characteristic
www.national.com
10
AC Electrical Characteristics (Continued)
01207906
FIGURE 2. Simplified Error Curve vs. Output Code without Auto-Calibration or Auto-Zero Cycles
01207907
FIGURE 3. Simplified Error Curve vs. Output Code after Auto-Calibration Cycle
11
www.national.com
AC Electrical Characteristics (Continued)
01207908
FIGURE 4. Offset or Zero Error Voltage
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-
calibration unless otherwise specified.
Linearity Error Change
vs. Clock Frequency
Linearity Error Change
vs. Temperature
01207953
01207954
Linearity Error Change
vs. Reference Voltage
Linearity Error Change
vs. Supply Voltage
01207955
01207956
www.national.com
12
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. (Continued)
Full-Scale Error Change
vs. Clock Frequency
Full-Scale Error Change
vs. Temperature
01207957
01207958
01207960
01207962
Full-Scale Error Change
vs. Reference Voltage
Full-Scale Error Change
vs. Supply Voltage
01207959
Zero Error Change
vs. Clock Frequency
Zero Error Change
vs. Temperature
01207961
13
www.national.com
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. (Continued)
Zero Error Change
vs. Reference Voltage
Zero Error Change
vs. Supply Voltage
01207964
01207963
Analog Supply Current
vs. Temperature
Digital Supply Current
vs. Clock Frequency
01207965
01207966
Digital Supply Current
vs. Temperature
Linearity Error Change
vs. Temperature
01207968
01207967
www.national.com
14
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. (Continued)
Full-Scale Error Change
vs. Temperature
Full-Scale Error Change
vs. Supply Voltage
01207969
01207971
01207973
01207970
01207972
01207974
Zero Error Change
vs. Temperature
Zero Error Change
vs. Supply Voltage
Analog Supply Current
vs. Temperature
Digital Supply Current
vs. Temperature
15
www.national.com
Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified.
Bipolar Spectral Response
with 1 kHz Sine Wave Input
Bipolar Spectral Response
with 10 kHz Sine Wave Input
01207975
01207976
Bipolar Spectral Response
with 20 kHz Sine Wave Input
Bipolar Spectral Response
with 30 kHz Sine Wave Input
01207977
01207978
Bipolar Spectral Response
with 40 kHz Sine Wave Input
Bipolar Spectral Response
with 50 kHz Sine Wave Input
01207979
01207980
www.national.com
16
Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified. (Continued)
Bipolar Spurious Free
Dynamic Range
Unipolar Signal-to-Noise Ratio
vs. Input Frequency
01207981
01207982
Unipolar Signal-to-Noise
+ Distortion Ratio
Unipolar Signal-to-Noise
+ Distortion Ratio
vs. Input Frequency
vs. Input Signal Level
01207983
01207984
Unipolar Spectral Response
with 1 kHz Sine Wave Input
Unipolar Spectral Response
with 10 kHz Sine Wave Input
01207985
01207986
17
www.national.com
Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified. (Continued)
Unipolar Spectral Response
with 20 kHz Sine Wave Input
Unipolar Spectral Response
with 30 kHz Sine Wave Input
01207987
01207988
Unipolar Spectral Response
with 40 kHz Sine Wave Input
Unipolar Spectral Response
with 50 kHz Sine Wave Input
01207989
01207990
Test Circuits
DO “TRI-STATE” (t1H, t0H
)
DO except “TRI-STATE”
01207913
01207914
www.national.com
18
Test Circuits (Continued)
Leakage Current
01207915
Timing Diagrams
DO “TRI-STATE” Falling and Rising Edge
DO Falling and Rising Edge
01207917
01207916
DI Data Input Timing
01207918
DO Data Output Timing Using CS
01207919
19
www.national.com
Timing Diagrams (Continued)
DO Data Output Timing with CS Continuously Low
01207920
ADC12138 Auto Cal or Auto Zero
01207921
Note: DO output data is not valid during this cycle.
www.national.com
20
Timing Diagrams (Continued)
ADC12138 Read Data without Starting a Conversion Using CS
01207922
ADC12138 Read Data without Starting a Conversion with CS Continuously Low
01207923
21
www.national.com
Timing Diagrams (Continued)
ADC12138 Conversion Using CS with 16-Bit Digital Output Format
01207924
ADC12138 Conversion with CS Continuously Low and 16-Bit Digital Output Format
01207925
www.national.com
22
Timing Diagrams (Continued)
ADC12138 Software Power Up/Down Using CS with 16-Bit Digital Output Format
01207926
ADC12138 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format
01207927
23
www.national.com
Timing Diagrams (Continued)
ADC12138 Hardware Power Up/Down
01207928
Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will
be stored in the output shift register.
ADC12138 Configuration Modification—Example of a Status Read
01207929
www.national.com
24
01207931
*Tantalum
**Monolithic Ceramic or better
FIGURE 5. Recommended Power Supply Bypassing and Grounding
01207930
FIGURE 6. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins
25
www.national.com
Format and Set-Up Tables
TABLE 1. Data Out Formats
DO Formats
17
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16
X
X
X
X
9
3
Sign MSB 10
9
5
7
8
4
8
7
3
9
6
2
5
1
4
3
2
1
LSB
X
Bits
13
MSB
First
Sing MSB 10
8
4
4
7
5
5
6
6
LSB
Bits
17
with
Sign
LSB
1
2
10 MSB Sign
10 MSB Sign
X
2
0
X
1
0
X
LSB
0
Bits
13
LSB
First
LSB
0
1
0
2
0
9
3
0
8
6
9
5
7
8
4
8
7
3
9
6
2
Bits
16
MSB 10
5
1
4
3
MSB
First
12
MSB 10
7
4
4
6
5
5
LSB
Bits
16
without
Sign
LSB
LSB
1
1
2
2
3
3
6
6
7
7
8
8
9
9
10 MSB
10 MSB
0
Bits
12
LSB
First
Bits
X = High or Low state.
TABLE 2. ADC12138 Multiplexer Addressing
Analog Channel Addressed and Assignment
with A/DIN1 tied to MUXOUT1 and A/DIN2 tied
to MUXOUT2
A/D Input
Polarity
Assignment
Multiplexer Output
Channel
MUX Address
Mode
Assignment
DI0 DI1 DI2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
L
L
L
L
L
L
L
H
L
+
−
+
−
+
+
+
+
−
−
−
−
+
+
+
+
+
+
+
+
−
−
−
−
+
+
+
+
−
−
−
−
−
−
−
−
CH0
CH2
CH4
CH6
CH0
CH2
CH4
CH6
CH0
CH2
CH4
CH6
CH1
CH3
CH5
CH7
CH1
CH3
CH5
CH7
CH1
CH3
CH5
CH7
COM
COM
COM
COM
COM
COM
COM
COM
+
−
+
−
+
L
L
H
H
L
+
−
+
−
+
L
L
H
L
+
−
+
−
+
Differential
L
H
H
H
H
L
+
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
−
−
−
−
−
−
−
−
L
L
H
L
L
H
H
L
L
H
L
Single-Ended
H
H
H
H
+
L
H
L
+
H
H
+
H
+
www.national.com
26
Format and Set-Up Tables (Continued)
TABLE 3. ADC12130 and ADC12132* Multiplexer Addressing
Analog Channel Addressed and
Assignment with A/DIN1 tied to MUXOUT1
and A/DIN2 tied to MUXOUT2
MUX
Address
A/D Input Polarity
Assignment
Multiplexer Output
Channel Assignment
Mode
DI0
DI1
CH0
CH1
−
COM
A/DIN1
A/DIN2
MUXOUT1 MUXOUT2
L
L
+
−
+
+
−
+
+
−
+
−
−
CH0
CH0
CH0
CH1
CH1
CH1
Differential
L
H
H
H
L
+
−
−
COM
COM
Single-Ended
H
+
Note: ADC12130 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.
* ADC12132 is obsolete; shown for reference only.
TABLE 4. Mode Programming
ADC12138 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
DO Format
(next Conversion
Cycle)
Mode Selected
ADC12130
and
(Current)
DI0 DI1
DI2 DI3 DI4 DI5
ADC12132 *
See Table 2 or Table 3
See Table 2 or Table 3
See Table 2 or Table 3
See Table 2 or Table 3
L
L
L
L
L
L
L
H
L
12 Bit Conversion
12 Bit Conversion
12 or 13 Bit MSB First
16 or 17 Bit MSB First
12 or 13 Bit LSB First
16 or 17 Bit LSB First
No Change
L
H
H
L
L
12 Bit Conversion
L
L
H
L
12 Bit Conversion
L
L
L
L
L
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
Auto Cal
L
L
H
L
Auto Zero
No Change
L
H
H
L
Power Up
No Change
L
H
L
Power Down
No Change
H
H
H
H
H
H
H
H
Read Status Register
Data Out without Sign
Data Out with Sign
No Change
L
H
H
L
No Change
L
No Change
H
H
H
H
H
Acquisition Time—6 CCLK Cycles
Acquisition Time—10 CCLK Cycles
Acquisition Time—18 CCLK Cycles
Acquisition Time—34 CCLK Cycles
User Mode
No Change
L
No Change
L
No Change
L
No Change
H
No Change
Test Mode
H
X
X
X
H
H
H
H
No Change
(CH1–CH7 become Active Outputs)
Note: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB First, and user mode.
X = Don’t Care
* ADC12132 is obsolete; shown for reference only.
TABLE 5. Conversion/Read Data Only Mode Programming
CS
L
CONV
PD
L
Mode
L
H
X
X
See Table 4 for Mode
L
L
Read Only (Previous DO Format). No Conversion.
H
L
Idle
X
H
Power Down
X = Don’t Care
27
www.national.com
Format and Set-Up Tables (Continued)
TABLE 6. Status Register
Status Bit
Location
Status Bit
DB0
PU
DB1
DB2
Cal
DB3
DB4
12 or 13
“High”
DB5
DB6
Sign
DB7
DB8
PD
16 or 17
Justification Test Mode
Device Status
“High”
DO Output Format Status
“High” “High” When “High” When
“High”
“High”
Not used
Function
indicates a indicates a indicates
indicates a indicates a indicates
the
“High” the
device is
Power Up Power
Sequence Down
an
12 or 13
16 or 17
that the
sign bit is
included.
When
conversion
Auto-Cal
bit format bit format
result will be in test
is in
Sequence Sequence
output MSB
first. When
“Low” the
mode.
progress
is in
is in
When
progress
progress
“Low” the
sign bit is
not
“Low” the
result will be device is
output LSB
first.
in user
mode.
included.
www.national.com
28
the ADC to accomplish this configuration modification. The
next instruction, shown in Figure 8, issued to the A/D starts
conversion N+1 with 16-bit format and 12 bits of resolution
formatted MSB first. Again the data output during this I/O
cycle is the data from conversion N.
Application Information
1.0 DIGITAL INTERFACE
1.1 Interface Concepts
The number of SCLKs applied to the A/D during any conver-
sion I/O sequence should vary in accord with the data out
word format chosen during the previous conversion I/O se-
quence. The various formats and resolutions available are
shown in Table 1. In Figure 8, since 16-bit without sign MSB
first format was chosen during I/O sequence 4, the number
of SCLKs required during I/O sequence 5 is 16. In the
following I/O sequence the format changes to 12-bit without
sign MSB first; therefore the number of SCLKs required
during I/O sequence 6 changes accordingly to 12.
The example in Figure 7 shows a typical sequence of events
after the power is applied to the ADC12130/2/8:
01207932
FIGURE 7. Typical Power Supply Power Up Sequence
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects. Not
doing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below
details out the number of clock periods required for different
DO formats:
The first instruction input to the A/D via DI initiates Auto Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
A/D. Again the data output at that time has no significance
since the Auto Cal procedure modifies the data in the output
shift register. To retrieve the status information, an additional
read status instruction is issued to the A/D. At this time the
status data is available on DO. If the Cal signal in the status
word, is low Auto Cal has been completed. Therefore, the
next instruction issued can start a conversion. The data
output at this time is again status information. To keep noise
from corrupting the A/D conversion, status can not be read
during a conversion. If CS is strobed and is brought low
during a conversion, that conversion is prematurely ended.
EOC can be used to determine the end of a conversion or
the A/D controller can keep track in software of when it would
be appropriate to communicate to the A/D again. Once it has
been determined that the A/D has completed a conversion,
another instruction can be transmitted to the A/D. The data
from this conversion can be accessed when the next instruc-
tion is issued to the A/D.
Number of
DO Format
SCLKs
Expected
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
12
13
16
17
12-Bit MSB or LSB First
16-Bit MSB or LSB first
If erroneous SCLK pulses desynchronize the communica-
tions, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.
Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. Not doing so will desynchronize the serial com-
munication to the A/D. (See Section 1.3.)
The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continu-
ously vs. the case when CS is cycled. Take the I/O sequence
detailed in Figure 7 (Typical Power Supply Sequence) as an
example. The table below lists the number of SCLK pulses
required for each instruction:
1.2 Changing Configuration
The configuration of the ADC12130/2/8 on power up defaults
to 12-bit plus sign resolution, 12- or 13-bit MSB First, 10
CCLK acquisition time, user mode, no Auto Cal, no Auto
Zero, and power up mode. Changing the acquisition time
and turning the sign bit on and off requires an 8-bit instruc-
tion to be issued to the ADC. This instruction will not start a
conversion. The instructions that select a multiplexer ad-
dress and format the output data do start a conversion.
Figure 8 describes an example of changing the configuration
of the ADC12130/2/8.
CS Low
Instruction
Auto Cal
CS Strobed
Continuously
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
8 SCLKs
8 SCLKs
8 SCLKs
8 SCLKs
13 SCLKs
Read Status
Read Status
During I/O sequence 1, the instruction on DI configures the
ADC12130/2/8 to do a conversion with 12-bit +sign resolu-
tion. Notice that when the 6 CCLK Acquisition and Data Out
without Sign instructions are issued to the ADC, I/O se-
quences 2 and 3, a new conversion is not started. The data
output during these instructions is from conversion N which
was started during I/O sequence 1. The Configuration Modi-
fication timing diagram describes in detail the sequence of
events necessary for a Data Out without Sign, Data Out with
Sign, or 6/10/18/34 CCLK Acquisition time mode selection.
Table 4 describes the actual data necessary to be input to
12-Bit + Sign Conv 1
12-Bit + Sign Conv 2
1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
(see Table 2, Table 3 and Table 4). In Figure 8 the only times
when the channel configuration could be modified would be
during I/O sequences 1, 4, 5 and 6. Input channels are
reselected before the start of each new conversion. Shown
29
www.national.com
powered down in this way, the A/D conversion circuitry is
deactivated but the digital I/O circuitry is kept active. Hard-
ware power up/down is controlled by the state of the PD pin.
Software power-up/down is controlled by the instruction is-
sued to the ADC. If a software power up instruction is issued
to the ADC while a hardware power down is in effect (PD pin
high) the device will remain in the power-down state. If a
software power down instruction is issued to the ADC while
a hardware power up is in effect (PD pin low), the device will
power down. When the device is powered down by software,
it may be powered up by either issuing a software power up
instruction or by taking PD pin high and then low. If the power
down command is issued during an A/D conversion, that
conversion is interrupted, so the data output after power up
cannot be relied upon.
Application Information (Continued)
below is the data bit stream required on DI, during I/O
sequence number 4 in Figure 8, to set CH1 as the positive
input and CH0 as the negative input for the different versions
of ADCs:
Part
DI Data
Number
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
ADC12130
and
ADC12132 *
L
H
L
L
L
H
L
L
L
X
H
X
L
ADC12138
L
H
L
Where X can be a logic high (H) or low (L).
* ADC12132 is obsolete; shown for reference only.
1.5 Power Up/Down
The ADC may be powered down by taking the PD pin HIGH
or by the instruction input on DI (see Table 4 and Table 5,
and the Power Up/Down timing diagrams). When the ADC is
01207933
FIGURE 8. Changing the ADC’s Conversion Configuration
1.6 User Mode and Test Mode
Instruction
DI Data
An instruction may be issued to the ADC to put it into test
mode, which is used by the manufacturer to verify complete
functionality of the device. During test mode CH0–CH7 be-
come active outputs. If the device is inadvertently put into the
test mode with CS continuously low, the serial communica-
tions may be desynchronized. Synchronization may be re-
gained by cycling the power supply voltage to the device.
Cycling the power supply voltage will also set the device into
user mode. If CS is used in the serial interface, the ADC may
be queried to see what mode it is in. This is done by issuing
a “read STATUS register” instruction to the ADC. When bit 9
of the status register is high, the ADC is in test mode; when
bit 9 is low the ADC, is in user mode. As an alternative to
cycling the power supply, an instruction sequence may be
used to return the device to user mode. This instruction
sequence must be issued to the ADC using CS. The follow-
ing table lists the instructions required to return the device to
user mode. Note that this entire sequence, including both
Test Mode and User Mode values, should be sent to recover
from the test mode.
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
TEST MODE
Reset
H
L
L
L
L
L
X
L
L
L
L
L
X
L
L
L
L
L
X
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
Test Mode
Instructions
L
L
H
H
L
USER MODE
Power Up
Set DO with
or without
Sign
H
L
H
L
L
L
H
H
L
H
or L
Set
H
H
Acquisition
Time
L
L
H
L
H
H
H
H
L
or L or L
Start a
H
H
H
H
H
Conversion or L or L or L or L
or L or L or L
X = Don’t Care
The power up, data with or without sign, and acquisition time
instructions should be resent after returning to the user
mode. This is to ensure that the ADC is in the required state
before a conversion is started.
www.national.com
30
combination thereof (see Figure 9). The difference between
the voltages on the VREF and VREF pins determines the
Application Information (Continued)
+
−
1.7 Reading the Data Without Starting a Conversion
input voltage span (VREF). The analog input voltage range is
−
0 to VA+. Negative digital output codes result when VIN
>
The data from a particular conversion may be accessed
without starting a new conversion by ensuring that the
CONV line is taken high during the I/O sequence. See the
Read Data timing diagrams. Table 5 describes the operation
of the CONV pin.
−
+
VIN+. The actual voltage at VIN or VIN cannot go below
AGND.
2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER
For the ADC12138, the analog input multiplexer can be
configured with 4 differential channels or 8 single ended
channels with the COM input as the zero reference or any
8 Single-Ended Channels
with COM
4 Differential
Channels
as Zero Reference
01207934
01207935
FIGURE 9.
Differential
Configuration
Single-Ended
Configuration
01207936
01207937
A/DIN1 and A/DIN2 can be assigned as the + or − input
A/DIN1 is + input
A/DIN2 is − input
FIGURE 10.
CH0, CH2, CH4, and CH6 can be assigned to the MUX-
OUT1 pin in the differential configuration, while CH1, CH3,
CH5, and CH7 can be assigned to the MUXOUT2 pin. In the
differential configuration, the analog inputs are paired as
follows: CH0 with CH1, CH2 with CH3, CH4 with CH5 and
CH6 with CH7. The A/DIN1 and A/DIN2 pins can be as-
signed positive or negative polarity.
The Multiplexer assignment tables for the ADC12130/2/8
(Table 2 and Table 3) summarize the aforementioned func-
tions for the different versions of A/Ds.
2.1 Biasing for Various Multiplexer Configurations
Figure 11 is an example of biasing the device for single-
ended operation. The sign bit is always low. The digital
output range is 0 0000 0000 0000 to 0 1111 1111 1111. One
LSB is equal to 1 mV (4.1V/4096 LSBs).
With the single-ended multiplexer configuration CH0 through
CH7 can be assigned to the MUXOUT1 pin. The COM pin is
always assigned to the MUXOUT2 pin. A/DIN1 is assigned
as the positive input; A/DIN2 is assigned as the negative
input. (See Figure 10).
31
www.national.com
Application Information (Continued)
01207938
FIGURE 11. Single-Ended Biasing
For pseudo-differential signed operation, the biasing circuit
shown in Figure 12 shows a signal AC coupled to the ADC.
This gives a digital output range of −4096 to +4095. With a
2.5V reference, 1 LSB is equal to 610 µV. Although, the ADC
is not production tested with a 2.5V reference, when VA+ and
VD are +5.0V linearity error typically will not change more
than 0.1 LSB (see the curves in the Typical Electrical Char-
acteristics Section). With the ADC set to an acquisition time
of 10 clock periods, the input biasing resistor needs to be
600Ω or less. Notice though that the input coupling capacitor
needs to be made fairly large to bring down the high pass
corner. Increasing the acquisition time to 34 clock periods
(with a 5 MHz CCLK frequency) would allow the 600Ω to
increase to 6k, which with a 1 µF coupling capacitor would
set the high pass corner at 26 Hz. Increasing R, to 6k would
allow R2 to be 2k.
+
01207939
FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC
An alternative method for biasing pseudo-differential opera-
tion is to use the +2.5V from the LM4040 to bias any ampli-
www.national.com
32
LM4041 to set the full scale voltage at exactly 2.048V and a
lower grade LM4040D-2.5 to bias up everything to 2.5V as
shown in Figure 14 will allow the use of all the ADC’s digital
output range of −4096 to +4095 while leaving plenty of head
room for the amplifier.
Application Information (Continued)
fier circuits driving the ADC as shown in Figure 13. The value
of the resistor pull-up biasing the LM4040-2.5 will depend
upon the current required by the op amp biasing circuitry.
In the circuit of Figure 13 some voltage range is lost since
the amplifier will not be able to swing to +5V and GND with
a single +5V supply. Using an adjustable version of the
Fully differential operation is shown in Figure 15. One LSB
for this case is equal to (4.1V/4096) = 1 mV.
01207940
FIGURE 13. Alternative Pseudo-Differential Biasing
01207941
FIGURE 14. Pseudo-Differential Biasing without the Loss of Digital Output Range
33
www.national.com
Application Information (Continued)
01207942
FIGURE 15. Fully Differential Biasing
3.0 REFERENCE VOLTAGE
varies between very specific voltage limits, a time and tem-
perature stable voltage source can be connected to the
reference inputs. Typically, the reference voltage’s magni-
tude will require an initial adjustment to null reference volt-
age induced full-scale errors.
+
The difference in the voltages applied to the VREF and
VREF− defines the analog input span (the difference between
the voltage applied between two multiplexer inputs or the
voltage applied to one of the multiplexer inputs and analog
ground), over which 4095 positive and 4096 negative codes
exist. The voltage sources driving VREF+ or VREF− must have
very low output impedance and noise. The circuit in Figure
16 is an example of a very stable reference appropriate for
use with the device.
Below are recommended references along with some key
specifications.
Output
Temperature
Coefficient
Part Number
LM4041CI-Adj
Voltage
Tolerance
0.5%
100ppm/˚C
100ppm/˚C
50ppm/˚C
2ppm/˚C
LM4040AI-4.1
0.1%
LM4050AI-4.1
0.1%
Circuit of Figure 16
Adjustable
The reference voltage inputs are not fully differential. The
ADC12130/2/8 will not generate correct conversions or com-
parisons if VREF+ is taken below VREF−. Correct conversions
+
−
result when VREF and VREF differ by 1V and remain, at all
times, between ground and VA+. The VREF common mode
range, (VREF+ + VREF−)/2 is restricted to (0.1 x VA+) to (0.6 x
01207943
*Tantalum
+
VA+). Therefore, with VA = 5V the center of the reference
FIGURE 16. Low Drift Extremely
Stable Reference Circuit
ladder should not go below 0.5V or above 3.0V. Figure 17 is
+
a graphic representation of the voltage restrictions on VREF
−
and VREF
.
The ADC12130/2/8 can be used in either ratiometric or
absolute reference applications. In ratiometric systems, the
analog input voltage is proportional to the voltage used for
the ADC’s reference voltage. When this voltage is the sys-
+
+
tem power supply, the VREF pin is connected to VA and
−
VREF is connected to ground. This technique relaxes the
system reference stability requirements because the analog
input voltage and the ADC reference voltage move together.
This maintains the same output code for given input condi-
tions. For absolute accuracy, where the analog input voltage
www.national.com
34
6.0 INPUT SOURCE RESISTANCE
Application Information (Continued)
<
For low impedance voltage sources ( 600Ω), the input
charging current will decay, before the end of the S/H’s
acquisition time of 2 µs (10 CCLK periods with fCK = 5 MHz),
to a value that will not introduce any conversion errors. For
high source impedances, the S/H’s acquisition time can be
increased to 18 or 34 CCLK periods. For less ADC accuracy
and/or slower CCLK frequencies the S/H’s acquisition time
may be decreased to 6 CCLK periods. To determine the
number of clock periods (Nc) required for the acquisition time
with a specific source impedance for the various resolutions
the following equations can be used:
12 Bit + Sign NC = [RS + 2.3] x fCK x 0.824
Where fCK is the conversion clock (CCLK) frequency in MHz
and RS is the external source resistance in kΩ. As an ex-
ample, operating with a resolution of 12 Bits + sign, a 5 MHz
clock frequency and maximum acquisition time of 34 conver-
sion clock periods the ADC’s analog inputs can handle a
source impedance as high as 6 kΩ. The acquisition time may
also be extended to compensate for the settling or response
time of external circuitry connected between the MUXOUT
and A/DIN pins.
An acquisition is started by a falling edge of SCLK and ends
with a rising edge of CCLK (see timing diagrams). If SCLK
and CCLK are asynchronous one extra CCLK clock period
may be inserted into the programmed acquisition time for
synchronization. Therefore, with asynchronous SCLK and
CCLK, the acquisition time will change from conversion to
conversion.
01207944
FIGURE 17. VREF Operating Range
4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12130/2/8’s fully differential ADC generate a two’s
complement output that is found by using the equation
shown below:
7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected
between the analog input pins, CH0–CH7, and analog
ground to filter any noise caused by inductive pickup asso-
ciated with long input leads. These capacitors will not de-
grade the conversion accuracy.
for (12-bit) resolution the Output Code =
8.0 NOISE
Round off to the nearest integer value between −4096 to
4095 if the result of the above equation is not a whole
number.
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion
errors. Input filtering can be used to reduce the effects of the
noise sources.
Examples are shown in the table below:
Code Output
+
−
+
−
VREF
VREF
VIN
VIN
Digital
9.0 POWER SUPPLIES
+2.5V
+1V
0V
+1.5V
+3V
0V
0V
0,1111,1111,1111
0,1011,1011,1000
+
+
Noise spikes on the VA and VD supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 µF or greater
paralleled with 0.1 µF monolithic ceramic capacitors. More or
different bypassing may be necessary depending on the
overall system requirements. Separate bypass capacitors
+4.096V
+4.096V
+4.096V
0V
+2.499V +2.500V 1,1111,1111,1111
0V +4.096V 1,0000,0000,0000
0V
5.0 INPUT CURRENT
At the start of the acquisition window (tA) a charging current
flows into or out of the analog input pins (A/DIN1 and
A/DIN2) depending on the input voltage polarity. The analog
input pins are CH0–CH7 and COM when A/DIN1 is tied to
MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value
of this input current will depend on the actual input voltage
applied, the source impedance and the internal multiplexer
switch on resistance. With MUXOUT1 tied to A/DIN1 and
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux
on resistance is typically 750Ω.
+
+
should be used for the VA and VD supplies and placed as
close as possible to these pins.
10.0 GROUNDING
The ADC12130/2/8’s performance can be maximized
through proper grounding techniques. These include the use
of separate analog and digital areas of the board with analog
and digital components and traces located only in their re-
spective areas. Bypass capacitors of 0.01 µF and 0.1 µF
surface mount capacitors and a 10 µF are recommended at
35
www.national.com
ity to digitize AC signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise (S/N), signal-to-noise
+ distortion ratio (S/(N + D)), effective bits, full power band-
width, aperture time and aperture jitter are quantitative mea-
sures of the A/D converter’s capability.
Application Information (Continued)
each of the power supply pins for best performance. These
capacitors should be located as close to the bypassed pin as
practical, especially the smaller value capacitors.
11.0 CLOCK SIGNAL LINE ISOLATION
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave-
form is applied to the A/D converter’s input, and the trans-
form is then performed on the digitized waveform. S/(N + D)
and S/N are calculated from the resulting FFT data, and a
spectral plot may also be obtained. Typical values for S/N
are shown in the table of Electrical Characteristics, and
spectral plots of S/(N + D) are included in the typical perfor-
mance curves.
The ADC12130/2/8’s performance is optimized by routing
the analog input/output and reference signal conductors as
far as possible from the conductors that carry the clock
signals to the CCLK and SCLK pins. Maintaining a separa-
tion of at least 7 to 10 times the height of the clock trace
above its reference plane is recommended.
12.0 THE CALIBRATION CYCLE
A calibration cycle needs to be started after the power sup-
plies, reference, and clock have been given enough time to
stabilize after initial turn-on. During the calibration cycle,
correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits. Full-
scale error typically changes 0.4 LSB over temperature
and linearity error changes even less; therefore it should be
necessary to go through the calibration cycle only once after
power up if the Power Supply Voltage and the ambient
temperature do not change significantly (see the curves in
the Typical Performance Characteristics).
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can be
seen in the S/(N + D) versus frequency curves. These curves
will also give an indication of the full power bandwidth (the
frequency at which the S/(N + D) or S/N drops 3 dB).
Effective number of bits can also be useful in describing the
A/D’s noise and distortion performance. An ideal A/D con-
verter will have some amount of quantization noise, deter-
mined by its resolution, and no distortion, which will yield an
optimum S/(N + D) ratio given by the following equation:
S/(N + D) = (6.02 x n + 1.76) dB
where "n" is the A/D’s resolution in bits.
Since the ideal A/D converter has no distortion, the effective
bits of a real A/D converter, therefore, can be found by:
13.0 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the A/D,
the auto-zero cycle can be used. It may be desirable to do an
auto-zero cycle whenever the ambient temperature or the
power supply voltage change significantly. (See the curves
titled “Zero Error Change vs. Ambient Temperature” and
“Zero Error Change vs. Supply Voltage” in the Typical Per-
formance Characteristics.)
n(effective) = ENOB = (S/(N + D) - 1.76 / 6.02
As an example, this device with a differential signed 5V,
1 kHz sine wave input signal will typically have a S/N of
77 dB, which is equivalent to 12.5 effective bits.
15.0 AN RS232 SERIAL INTERFACE
Shown on the following page is a schematic for an RS232
interface to any IBM and compatible PCs. The DTR, RTS,
and CTS RS232 signal lines are buffered via level transla-
tors and connected to the ADC12138’s DI, SCLK, and DO
pins, respectively. The D flip-flop is used to generate the CS
signal.
14.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but the standard DC integral and differential nonlin-
earity specifications will not accurately predict the A/D con-
verter’s performance with AC input signals. The important
specifications for AC applications reflect the converter’s abil-
www.national.com
36
Application Information (Continued)
01207946
+
+
+
Note: V , V , and V on the ADC12138 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF
REF
A
D
caps.
The assignment of the RS232 port is shown below
B7
X
B6
X
B5
X
B4
CTS
0
B3
X
B2
X
B1
B0
Input Address
3FE
3FC
X
X
COM1
Output Address
X
X
X
X
X
RTS DTR
A sample program, written in Microsoft QuickBasic, is shown
on the next page. The program prompts for data mode select
instruction to be sent to the A/D. This can be found from the
Mode Programming table shown earlier. The data should be
entered in “1”s and “0”s as shown in the table with DI0 first.
Next, the program prompts for the number of SCLKs re-
quired for the programmed mode select instruction. For in-
stance, to send all “0”s to the A/D, selects CH0 as the +input,
CH1 as the −input, 12-bit conversion, and 13-bit MSB first
data output format (if the sign bit was not turned off by a
previous instruction). This would require 13 SCLK periods
since the output data format is 13 bits.
sign, power up, 12- or 13-bit MSB First, and user mode. Auto
Cal, Auto Zero, Power Up and Power Down instructions do
not change these default settings. The following power up
sequence should be followed:
1. Run the program
2. Prior to responding to the prompt apply the power to the
ADC12138
3. Respond to the program prompts
It is recommended that the first instruction issued to the
ADC12138 be Auto Cal (see Section 1.1).
The ADC powers up with No Auto Cal, No Auto Zero, 10
CCLK Acquisition Time, 12-bit conversion, data out with
37
www.national.com
Application Information (Continued)
Code Listing:
’variables DOL=Data Out word length, DI=Data string for A/D DI input,
’
DO=A/D result string
’SET CS# HIGH
OUT &H3FC, (&H2 OR INP (&H3FC)
OUT &H3FC, (&HFE AND INP(&H3FC)
OUT &H3FC, (&HFD AND INP (&H3FC)
OUT &H3FC, (&HEF AND INP(&H3FC))
10
’set RTS HIGH
’SET DTR LOW
’SET RTS LOW
’set B4 low
LINE INPUT <&ldquo>DI data for ADC12138 (see Mode Table on data sheet)”; DI$
INPUT <&ldquo>ADC12138 output word length (12,13,16 or 17)”; DOL
20
’SET CS# HIGH
OUT &H3FC, (&H2 OR INP (&H3FC)
OUT &H3FC, (&HFE AND INP(&H3FC)
OUT &H3FC, (&HFD AND INP (&H3FC)
’SET CS# LOW
’set RTS HIGH
’SET DTR LOW
’SET RTS LOW
OUT &H3FC, (&H2 OR INP (&H3FC)
OUT &H3FC, (&H1 OR INP(&H3FC)
OUT &H3FC, (&HFD AND INP (&H3FC)
DO$=<&ldquo> ”
’set RTS HIGH
’SET DTR HIGH
’SET RTS LOW
’reset DO variable
OUT &H3FC, (&H1 OR INP(&H3FC)
OUT &H3FC, (&HFD AND INP(&H3FC))
FOR N = 1 TO 8
’SET DTR HIGH
’SCLK low
Temp$ = MID$(DI$, N, 1)
IF Temp$=<&ldquo>0” THEN
OUT &H3FC, (&H1 OR INP(&H3FC))
ELSE OUT &H3FC, (&HFE AND INP(&H3FC))
END IF
’out DI
OUT &H3FC, (&H2 OR INP(&H3FC))
IF (INP(&H3FE) AND 16) = 16 THEN
DO$ = DO$ + <&ldquo>0”
ELSE
’SCLK high
DO$ = DO$ + <&ldquo>1”
END IF
’Input DO
OUT &H3FC, (&H1 OR INP(&H3FC)
OUT &H3FC, (&HFD AND INP(&H3FC))
NEXT N
’SET DTR HIGH
’SCLK low
IF DOL > 8 THEN
FOR N=9 TO DOL
OUT &H3FC, (&H1 OR INP(&H3FC)
OUT &H3FC, (&HFD AND INP(&H3FC))
OUT &H3FC, (&H2 OR INP(&H3FC))
IF (INP(&H3FE) AND &H1O) = &H1O THEN
DO$ = DO$ + <&ldquo>0”
ELSE
’SET DTR HIGH
’SCLK low
’SCLK high
DO$ = DO$ + <&ldquo>1”
END IF
NEXT N
END IF
OUT &H3FC, (&HFA AND INP(&H3FC))
FOR N = 1 TO 500
’SCLK low and DI high
NEXT N
PRINT DO$
INPUT <&ldquo>Enter <&ldquo>C” to convert else <&ldquo>RETURN” to alter DI data”; s$
IF s$ = <&ldquo>C” OR s$ = <&ldquo>c” THEN
GOTO 20
ELSE
GOTO 10
END IF
END
www.national.com
38
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC12130CIWM
NS Package Number M16B
Order Number ADC12138CIWM
NS Package Number M28B
39
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number ADC12132CIMSA (obsolete)
NS Package Number MSA20
Order Number ADC12138CIMSA
NS Package Number MSA28
www.national.com
40
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number ADC12130CIN
NS Package Number N16E
Order Number ADC12138CIN
NS Package Number N28B
41
www.national.com
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
ADC12130_06 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ADC12130_14 | TI | ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
| ADC12132 | NSC | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
| ADC12132 | TI | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
| ADC12132CIMSA | NSC | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
| ADC12132CIMSA/NOPB | TI | IC,DATA ACQ SYSTEM,2-CHANNEL,13-BIT,SSOP,20PIN,PLASTIC | 获取价格 |
|
| ADC12132CIMSAX | NSC | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
| ADC12138 | NSC | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
| ADC12138 | TI | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
| ADC12138CIMSA | NSC | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
| ADC12138CIMSA | TI | ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | 获取价格 |
|
ADC12130_06 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
