ADC12H034CIMSAX中文资料_数据手册_规格书

April 2007

ADC12H030/ADC12H032/ADC12H034/ADC12H038,

ADC12030/ADC12032/ADC12034/ADC12038

Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters

with MUX and Sample/Hold

General Description

Some device/package combinations are obsolete and

shown for reference only.

The ADC12030, and ADC12H030 families are 12-bit plus sign

successive approximation A/D converters with serial I/O and

configurable input multiplexers. The ADC12034/ADC12H034

and ADC12038/ADC12H038 have 4 and 8 channel multiplex-

ers, respectively. The differential multiplexer outputs and A/D

inputs are available on the MUXOUT1, MUXOUT2, A/DIN1

and A/DIN2 pins. The ADC12030/ADC12H030 has a two

channel multiplexer with the multiplexer outputs and A/D in-

puts internally connected. The ADC12030 family is tested

with a 5 MHz clock, while the ADC12H030 family is tested

with an 8 MHz clock. On request, these A/Ds go through a

self calibration process that adjusts linearity, zero and full-

scale errors to less than ±1 LSB each.

Features

Serial I/O (MICROWIRE Compatible)

■

2, 4, or 8 chan differential or single-ended multiplexer

Analog input sample/hold function

Power down mode

Variable resolution and conversion rate

Programmable acquisition time

Variable digital output word length and format

No zero or full scale adjustment required

Fully tested and guaranteed with a 4.096V reference

■

0V to 5V analog input range with single 5V power supply

No Missing Codes over temperature

Key Specifications

■ Resolution

■ 12-bit plus sign conversion time

– ADC12H30 family

The analog inputs can be configured to operate in various

combinations of single-ended, differential, or pseudo-differ-

ential modes. A fully differential unipolar analog input range

(0V to +5V) can be accommodated with a single +5V supply.

In the differential modes, valid outputs are obtained even

when the negative inputs are greater than the positive be-

cause of the 12-bit plus sign output data format.

12-bit plus sign

5.5 µs (max)

8.8 µs (max)

– ADC12030 family

■ 12-bit plus sign throughput time

– ADC12H30 family

The serial I/O is configured to comply with NSC MICROWIRE.

For voltage references see the LM4040, LM4050 or LM4041.

8.6 µs (max)

14 µs (max)

– ADC12030 family

±1 LSB (max)

■ Integral Linearity Error

■ Single Supply

■ Power consumption

– Power down

5V ±10%

33 mW (max)

100 µW (typ)

Applications

Medical instruments

■

Process control systems

Test equipment

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

11354

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ADC12038 Simplified Block Diagram

1135401

Connection Diagrams

16-Pin Wide Body

SO Packages

20-Pin Wide Body

SO Packages

1135406

Top View

1135407

Top View

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2

24-Pin Wide Body

SO, DIP, SSOP-EIAJ Packages

28-Pin Wide Body

SO Packages

1135408

Top View

1135409

Top View

Ordering Information

Industrial Temperature Range

−40°C ≤ T_A≤ +85°C

ADC12H030CIWM,

ADC12030CIWM

ADC12030CIWMX

ADC12032CIWM

ADC12034CIN

Package

M16B, Wide Body SO

M16B, Wide Body SO - Tape & Reel

M20B, Wide Body SO

N24C, Dual-In-Line

ADC12034CIWM

ADC12H034CIMSA

ADC12H034CIMSAX

M24B, Wide Body SO

MSA24, SSOP

MSA24, SSOP - Tape & Reel

ADC12H038CIWM,

ADC12038CIWM

M28B, Wide Body SO

ADC12H038CIWMX,

ADC12038CIWMX

M28B, Wide Body SO - Tape & Reel

* Some of these product/package combinations are on lifetime buy or are obsolete and shown here for reference only. Check our

web site for product/package availability.

3

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STATE. With CS low the falling edge

of SCLK shifts the data resulting

from the previous ADC conversion

out on DO, with the exception of the

first bit of data. When CS is low con-

tinuously, the first bit of the data is

clocked out on the rising edge of

EOC (end of conversion). When CS

is toggled the falling edge of CS al-

ways clocks out the first bit of data.

CS should be brought low when

SCLK is low. The falling edge of CS

resets a conversion in progress and

starts the sequence for a new con-

version. When CS is brought back

low during a conversion, that con-

version is prematurely terminated.

The data in the output latches may

be corrupted. Therefore, when CS is

brought back low during a conver-

sion in progress the data output at

that time should be ignored. CS may

also be left continuously low. In this

case it is imperative that the correct

number of SCLK pulses be applied

to the ADC in order to remain syn-

chronous. After the ADC supply

power is applied it expects to see 13

clock pulses for each I/O sequence.

The number of clock pulses the ADC

expects is the same as the digital

output word length. This word length

can be modified by the data shifted

in on the DO pin. Table 5 details the

data required.

Pin Descriptions

CCLK

The clock applied to this input con-

trols the successive approximation

conversion time interval and the ac-

quisition time. The rise and fall times

of the clock edges should not exceed

1 µs.

SCLK

This is the serial data clock input.

The clock applied to this input con-

trols the rate at which the serial data

exchange occurs. The rising edge

loads the information on the DI pin

into the multiplexer address and

mode select shift register. This ad-

dress controls which channel of the

analog input multiplexer (MUX) is

selected and the mode of operation

for the A/D. With CS low the falling

edge of SCLK shifts the data result-

ing from the previous ADC conver-

sion out on DO, with the exception of

the first bit of data. When CS is low

continuously, the first bit of the data

is clocked out on the rising edge of

EOC (end of conversion). When CS

is toggled the falling edge of CS al-

ways clocks out the first bit of data.

CS should be brought low when

SCLK is low. The rise and fall times

of the clock edges should not exceed

1 µs.

DI

This is the serial data input pin. The

data applied to this pin is shifted by

the rising edge of SCLK into the mul-

tiplexer address and mode select

register. Table 2 through Table 5

show the assignment of the multi-

plexer address and the mode select

data.

DOR

This is the data output ready pin.

This pin is an active push/pull output.

It is low when the conversion result

is being shifted out and goes high to

signal that all the data has been shift-

ed out.

DO

The data output pin. This pin is an

active push/pull output when CS is

low. When CS is high, this output is

TRI-STATE^®. The A/D conversion

result (D0–D12) and converter sta-

tus data are clocked out by the falling

edge of SCLK on this pin. The word

length and format of this result can

vary (see Table 1). The word length

and format are controlled by the data

shifted into the multiplexer address

and mode select register (see Table

5).

CONV

A logic low is required on this pin to

program any mode or change the

ADC's configuration as listed in the

Mode Programming Table 5 such as

12-bit conversion, 8-bit conversion,

Auto-Cal, Auto Zero etc. When this

pin is high the ADC is placed in the

read data only mode. While in the

read data only mode, bringing CS

low and pulsing SCLK will only clock

out on DO any data stored in the AD-

Cs output shift register. The data on

DI will be neglected. A new conver-

sion will not be started and the ADC

will remain in the mode and/or con-

figuration previously programmed.

Read data only cannot be performed

while a conversion, Auto-Cal or Au-

to-Zero are in progress.

EOC

This pin is an active push/pull output

and indicates the status of the

ADC12030/2/4/8. When low, it sig-

nals that the A/D is busy with a con-

version, auto-calibration, auto-zero

or power down cycle. The rising

edge of EOC signals the end of one

of these cycles.

PD

This is the power down pin. When

PD is high the A/D is powered down;

when PD is low the A/D is powered

up. The A/D takes a maximum of 250

µs to power up after the command is

given.

CS

This is the chip select pin. When a

logic low is applied to this pin, the

rising edge of SCLK shifts the data

on DI into the address register. This

low also brings DO out of TRI-

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4

+

CH0–CH7

These are the analog inputs of the

MUX. A channel input is selected by

the address information at the DI pin,

which is loaded on the rising edge of

SCLK into the address register (See

Tables 2, 3, 4).

ceed V_Aor go below AGND (see

Figure 6).

V_REF

+

This is the positive analog voltage

reference input. In order to maintain

accuracy, the voltage range of V_REF

(V_REF= V_REF+ − V_REF−) is 1 V_DCto

The voltage applied to these inputs

should not exceed V_A+ or go below

GND. Exceeding this range on an

unselected channel will corrupt the

reading of a selected channel.

5.0 V_DCand the voltage at V_REF+

cannot exceed V_A+. See Figure 5 for

recommended bypassing.

V_REF

−

The negative voltage reference in-

put. In order to maintain accuracy,

the voltage at this pin must not go

below GND or exceed V_A+. (See

Figure 5).

COM

This pin is another analog input pin.

It is used as a pseudo ground when

the analog multiplexer is single-end-

ed.

V_A+, V_D+

These are the analog and digital

power supply pins. V_A⁺and V_D⁺are

not connected together on the chip.

These pins should be tied to the

same power supply and bypassed

separately (see Figure 5). The oper-

ating voltage range of V_A+ and V_D+

MUXOUT1,MUXOUT2

A/DIN1, /DIN2

These are the multiplexer output

pins.

These are the converter input pins.

MUXOUT1 is usually tied to A/DIN1.

MUXOUT2 is usually tied to A/DIN2.

If external circuitry is placed be-

tween MUXOUT1 and A/DIN1, or

MUXOUT2 and A/DIN2 it may be

necessary to protect these pins. The

voltage at these pins should not ex-

is 4.5 V_DCto 5.5 V_DC

.

DGND

AGND

This is the digital ground pin (see

Figure 5).

This is the analog ground pin (see

Figure 5).

5

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Absolute Maximum Ratings

(Notes 1, 2)

Operating Ratings (Notes 1, 2)

Operating Temperature Range

T_MIN≤ T_A≤ T_MAX

−40°C ≤ T_A≤ +85°C

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V⁺= V_A+ = V_D+)

|V_A+ − V_D+|

+4.5V to +5.5V

≤ 100 mV

0V to V_A+

Positive Supply Voltage

V_REF

+

−

(V⁺= V_A+ = V_D+)

6.5V

−0.3V to (V⁺+0.3V)

GND −5V to (V⁺+5V)

V_REF

0V to (V_REF+ −1V)

1V to V_A+

Voltage at Inputs and Outputs

except CH0–CH7 and COM

Voltage at Analog Inputs

CH0–CH7 and COM

V_REF(V_REF+ − V_REF−)

V_REFCommon Mode Voltage Range

[(V_REF+) − (V_REF−)] / 2

0.1 V_A+ to 0.6 V_A+

0V to V_A+

A/DIN1, A/DIN2, MUXOUT1 and

MUXOUT2 Voltage Range A/D

IN Common Mode Voltage Range

[(V_IN+) − (V_IN−)] / 2

|V_A+ − V_D+|

300 mV

±30 mA

±120 mA

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Package Dissipation at

T_A= 25°C (Note 4)

0V to V_A+

Package Thermal Resistance

500 mW

1500V

260°C

ESD Susceptibility (Note 5)

Human Body Model

Soldering Information

N Packages (10 seconds)

SO Package (Note 6):

Vapor Phase (60 seconds)

Infrared (15 seconds)

Thermal Resistance

Part Number

(θ_JA

)

ADC12(H)030CIWM

70°C/W

64°C/W

42°C/W

57°C/W

97°C/W

50°C/W

ADC12032CIWM

ADC12034CIN

215°C

220°C

ADC12034CIWM

ADC12H034CIMSA

ADC12(H)038CIWM

Storage Temperature

−65°C to +150°C

Some product/package combinations are obsolete or on life-

time buy. These are shown for reference only. Please check

our web site for availability.

Converter Electrical Characteristics

The following specifications apply for V⁺= V_A+ = V_D+ = +5.0 V_DC, V_REF+ = +4.096 V_DC, V_REF− = 0 V_DC, 12-bit + sign conversion

mode, f_CK= f_SK= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f_CK= f_SK= 5 MHz for the ADC12030,

ADC12032, ADC12034 and ADC12038, R_S= 25Ω, source impedance for V_REF+ and V_REF− ≤ 25Ω, fully-differential input with fixed

2.048V common-mode voltage, and 10(t_CK) acquisition time unless otherwise specified. Boldface limits apply for T_A= T_J=

T_MINto T_MAX; all other limits T_A= T_J= 25°C. (Notes 7, 8, 9)

Typical

(Note 10)

Limits

(Note 11)

Units

(Limits)

Symbol

Parameter

Conditions

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

12 + sign

±1

Bits (min)

LSB (max)

ILE

Integral Linearity Error

Differential Non-Linearity

Positive Full-Scale Error

Negative Full-Scale Error

After Auto-Cal (Notes 12, 18)

After Auto-Cal

±1/2

DNL

±1

After Auto-Cal (Notes 12, 18)

±1/2

±3.0

After Auto-Cal (Notes 5, 18)

V_IN(+) = V_IN(−) = 2.048V

Offset Error

±1/2

±2

LSB (max)

DC Common Mode Error

Total Unadjusted Error

After Auto-Cal (Note 15)

±2

±1

±3.5

LSB (max)

LSB

TUE

After Auto-Cal (Notes 12, 13, 14)

Resolution with No Missing Codes 8-bit + sign mode

8 + sign

±1/2

Bits (min)

LSB (max)

INL

Integral Linearity Error

Differential Non-Linearity

Positive Full-Scale Error

Negative Full-Scale Error

8-bit + sign mode (Note 12)

DNL

8-bit + sign mode

±3/4

8-bit + sign mode (Note 12)

±1/2

8-bit + sign mode, after Auto-Zero

V_IN(+) = V_IN(−) = + 2.048V (Note 13)

Offset Error

±1/2

LSB (max)

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6

Typical

(Note 10)

Limits

(Note 11)

Units

(Limits)

Symbol

Parameter

Conditions

8-bit + sign mode after Auto-Zero

(Notes 12, 13, 14)

TUE

Total Unadjusted Error

±3/4

LSB (max)

LSB

Multiplexer Chan-to-Chan

Matching

±0.05

V⁺= +5V ±10%, V_REF= +4.096V

Power Supply Sensitivity

Offset Error

+ Full-Scale Error

− Full-Scale Error

±0.5

±1

LSB (max)

LSB

±1.5

Integral Linearity Error

Output Data from “12-Bit

Conversion of Offset”

+10

−10

LSB (max)

LSB (min)

(see Table 5) (Note 20)

Output Data from “12-Bit

Conversion of Full-Scale”

4095

4093

LSB (max)

LSB (min)

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS

f_IN= 1 kHz, V_IN= 5 V_P-P, V_REF⁺= 5.0V

69.4

68.3

65.7

31

dB

Signal-to-Noise Plus Distortion

Ratio

f_IN= 20 kHz, V_IN= 5 V_P-P, V_REF⁺= 5.0V

f_IN= 40 kHz, V_IN= 5 V_P-P, V_REF+ = 5.0V

V_IN= 5 V_P-P, where S/(N+D) drops 3 dB

S/(N+D)

dB

−3 dB Full Power Bandwidth

kHz

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS

f_IN= 1 kHz, V_IN= ±5V, V_REF⁺= 5.0V

77.0

73.9

67.0

40

dB

Signal-to-Noise Plus Distortion

Ratio

f_IN= 20 kHz, V_IN= ±5V, V_REF⁺= 5.0V

f_IN= 40 kHz, V_IN= ±5V, V_REF⁺= 5.0V

V_IN= ±5V, where S/(N+D) drops 3 dB

S/(N+D)

dB

−3 dB Full Power Bandwidth

kHz

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS

C_REF

Reference Input Capacitance

85

75

pF

A/DIN1, A/DIN2 Analog Input

Capacitance

C_A/D

A/DIN1, A/DIN2 Analog Input

Leakage Current

V_IN= +5.0V or V_IN= 0V

±0.1

±1.0

µA (max)

GND − 0.05

(V_A+) + 0.05

V (min)

V (max)

CH0–CH7 and COM Input Voltage

CH0–CH7 and COM Input

Capacitance

C_CH

10

pF

C_MUXOUT

MUX Output Capacitance

20

pF

On Channel = 5V and Off Channel = 0V

On Channel = 0V and Off Channel = 5V

On Channel = 5V and Off Channel = 0V

On Channel = 0V and Off Channel = 5V

−0.01

0.01

−0.3

0.3

µA (min)

µA (max)

µA (min)

Off Channel Leakage CH0–CH7

and COM Pins (Note 16)

0.01

0.3

On Channel Leakage CH0–CH7

and COM Pins (Note 16)

−0.01

−0.3

MUXOUT1 and MUXOUT2

Leakage Current

V_MUXOUT= 5.0V or V_MUXOUT= 0V

0.01

0.3

µA (max)

R_ON

MUX On Resistance

R_ONMatching Chan-to-Chan

Chan-to-Chan Crosstalk

MUX Bandwidth

V_IN= 2.5V and V_MUXOUT= 2.4V

V_IN= 5 V_P-P, f_IN= 40 kHz

850

5

1150

Ω (max)

%

dB

−72

90

kHz

7

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DC and Logic Electrical Characteristics

The following specifications apply for V⁺= V_A+ = V_D+ = +5.0 V_DC, V_REF+ = +4.096 V_DC, V_REF− = 0 V_DC, 12-bit + sign conversion

mode, f_CK= f_SK= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f_CK= f_SK= 5 MHz for the ADC12030,

ADC12032, ADC12034 and ADC12038, R_S= 25Ω, source impedance for V_REF+ and V_REF− ≤ 25Ω, fully-differential input with fixed

2.048V common-mode voltage, and 10(t_CK) acquisition time unless otherwise specified. Boldface limits apply for T_A= T_J=

T_MINto T_MAX; all other limits T_A= T_J= 25°C. (Notes 7, 8, 9)

Symbo

l

Typical

(Note 10)

Limits

(Note 11)

Units

(Limits)

Parameter

Conditions

CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS

V_IN(1)

V_IN(0)

I_IN(1)

V⁺= 5.5V

V⁺= 4.5V

V_IN= 5.0V

V_IN= 0V

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

2.0

0.8

V (min)

V (max)

µA (max)

µA (min)

0.005

1.0

I_IN(0)

−0.005

−1.0

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS

V⁺= 4.5V, I_OUT= −360 µA

2.4

4.25

0.4

V (min)

V_OUT(1)

V_OUT(0)

I_OUT

Logical “1” Output Voltage

Logical “0” Output Voltage

TRI-STATE Output Current

V⁺= 4.5V, I_OUT= − 10 µA

V⁺= 4.5V, I_OUT= 1.6 mA

V_OUT= 0V

V (max)

µA (max)

mA (min)

−0.1

0.1

14

−3.0

3.0

V_OUT= 5V

+I_SC

−I_SC

V_OUT= 0V

Output Short Circuit Source Current

Output Short Circuit Sink Current

6.5

V_OUT= V_D+

16

8.0

POWER SUPPLY CHARACTERISTICS

Digital Supply Current

ADC12030, ADC12032, ADC12034 and CS = HIGH, Powered Down, CCLK on

ADC12038

Awake

1.6

600

20

2.5

3.2

4.0

mA (max)

µA

CS = HIGH, Powered Down, CCLK off

Awake

µA

I_D+

Digital Supply Current

ADC12H030, ADC12H032, ADC12H034 CS = HIGH, Powered Down, CCLK on

and ADC12H038

2.3

0.9

20

mA

µA

CS = HIGH, Powered Down, CCLK off

Awake

2.7

10

0.1

mA (max)

µA

I_A+

Positive Analog Supply Current

CS = HIGH, Powered Down, CCLK on

CS = HIGH, Powered Down, CCLK off

µA

Awake

70

0.1

µA

I_REF

Reference Input Current

CS = HIGH, Powered Down

AC Electrical Characteristics

The following specifications apply for V⁺= V_A+ = V_D+ = +5.0 V_DC, V_REF+ = +4.096 V_DC, V_REF− = 0 V_DC, 12-bit + sign conversion

mode, t_r= t_f= 3 ns, f_CK= f_SK= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f_CK= f_SK= 5 MHz for the

ADC12030, ADC12032, ADC12034 and ADC12038, R_S= 25Ω, source impedance for V_REF+ and V_REF− ≤ 25Ω, fully-differential

input with fixed 2.048V common-mode voltage, and 10(t_CK) acquisition time unless otherwise specified. Boldface limits apply for

T_A= T_J= T_MINto T_MAX; all other limits T_A= T_J= 25°C. (Note 17)

ADC12H030/2/4/8 ADC12030/2/4/8

Units

(Limits)

Symb

ol

Typical

(Note 10)

Parameter

Conditions

Limits

(Note 11)

f_CK

Conversion Clock (CCLK)

Frequency

10

1

8

5

MHz (max)

MHz (min)

Serial Data Clock SCLK

Frequency

10

0

MHz (max)

Hz (min)

f_SK

40

60

40

60

% (min)

% (max)

Conversion Clock Duty Cycle

Serial Data Clock Duty Cycle

40

60

40

60

% (min)

% (max)

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8

ADC12H030/2/4/8 ADC12030/2/4/8

Units

(Limits)

Symb

ol

Typical

(Note 10)

Parameter

Conditions

Limits

(Note 11)

44(t_CK

21(t_CK

)

44(t_CK

5.5

)

44(t_CK

8.8

)

(max)

µs (max)

12-Bit + Sign or 12-Bit

8-Bit + Sign or 8-Bit

t_C

Conversion Time

21(t_CK

2.625

21(t_CK

4.2

(max)

µs (max)

6(t_CK

7(t_CK

0.75

)

6(t_CK

7(t_CK

)

(min)

6(t_CK

10(t_CK

18(t_CK

34(t_CK

)

(max)

6 Cycles Programmed

10 Cycles Programmed

18 Cycles Programmed

34 Cycles Programmed

1.2

1.4

µs (min)

µs (max)

(min)

0.875

10(t_CK

11(t_CK

)

10(t_CK

11(t_CK

)

(max)

1.25

1.375

18(t_CK

19(t_CK

2.0

2.2

µs (min)

µs (max)

(min)

t_A

Acquisition Time (Note 19)

)

18(t_CK

19(t_CK

)

(max)

2.25

2.375

34(t_CK

35(t_CK

3.6

3.8

µs (min)

µs (max)

(min)

)

34(t_CK

35(t_CK

)

(max)

4.25

6.8

7.0

µs (min)

µs (max)

(max)

4.375

4944(t_CK

76(t_CK

)

4944(t_CK

618.0

)

4944(t_CK

988.8

)

t_CKAL

t_AZ

Self-Calibration Time

Auto-Zero Time

µs (max)

(max)

)

76(t_CK

9.5

)

76(t_CK

15.2

)

µs (max)

(min)

2(t_CK

)

2(t_CK

3(t_CK

)

2(t_CK

3(t_CK

)

Self-Calibration or Auto-Zero

Synchronization Time from

DOR

)

(max)

t_SYNC

0.250

0.375

0.40

0.60

µs (min)

µs (max)

DOR High Time when CS is

Low Continuously for Read

Data and Software Power Up/

Down

ꢀ

9(t_SK

ꢀ

9(t_SK

ꢀ

9(t_SK

ꢀ

(max)

µs (max)

)

t_DOR

1.125

1.8

8(t_SK

1.0

)

8(t_SK

1.6

(max)

t_CONV

CONV Valid Data Time

µs (max)

Timing Characteristics

The following specifications apply for V⁺= V_A+ = V_D+ = +5.0 V_DC, V_REF+ = +4.096 V_DC, V_REF− = 0 V_DC, 12-bit + sign conversion

mode, t_r= t_f= 3 ns, f_CK= f_SK= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H03, f_CK= f_SK= 5 MHz for the

ADC12030, ADC12032, ADC12034 and ADC12038, R_S= 25Ω, source impedance for V_REF+ and V_REF− ≤ 25Ω, fully-differential

input with fixed 2.048V common-mode voltage, and 10(t_CK) acquisition time unless otherwise specified. Boldface limits apply for

T_A= T_J= T_MINto T_MAX; all other limits T_A= T_J= 25°C. (Note 17)

Typical

(Note 10) (Note 11)

Limits

Units

(Limits)

Symbol

Parameter

Conditions

Hardware Power-Up Time, Time from PD Falling Edge to

EOC Rising Edge

t_HPU

140

250

µs (max)

Software Power-Up Time, Time from Serial Data Clock

Falling Edge to EOC Rising Edge

t_SPU

140

20

250

50

µs (max)

ns (max)

ns (min)

t_ACC

Access Time Delay from CS Falling Edge to DO Data Valid

Set-Up Time of CS Falling Edge to Serial Data Clock Rising

Edge

t_SET-UP

30

9

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Typical

(Note 10) (Note 11)

Limits

Units

(Limits)

Symbol

Parameter

Conditions

t_DELAY

t_1H, t_0H

t_HDI

Delay from SCLK Falling Edge to CS Falling Edge

Delay from CS Rising Edge to DO TRI-STATE

DI Hold Time from Serial Data Clock Rising Edge

DI Set-Up Time from Serial Data Clock Rising Edge

0

40

5

ns (min)

ns (max)

ns (min)

R_L= 3k, C_L= 100 pF

100

15

t_SDI

5

10

50

5

ns (max)

ns (min)

t_HDO

t_DDO

t_RDO

R_L= 3k, C_L= 100 pF

DO Hold Time from Serial Data Clock Falling Edge

25

Delay from Serial Data Clock Falling Edge to DO Data Valid

DO Rise Time, TRI-STATE to High

DO Rise Time, Low to High

35

10

12

25

50

30

45

ns (max)

R_L= 3k, C_L= 100 pF

DO Fall Time, TRI-STATE to Low

t_FDO

t_CD

t_SD

DO Fall Time, High to Low

Delay from CS Falling Edge to DOR Falling Edge

Delay from Serial Data Clock Falling Edge to DOR Rising

Edge

25

45

ns (max)

C_IN

Capacitance of Logic Inputs

Capacitance of Logic Outputs

10

20

pF

C_OUT

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: When the input voltage (V_IN) at any pin exceeds the power supplies (V_IN< GND or V_IN> V_A+ or V_D+), the current at that pin should be limited to 30 mA.

The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T_Jmax, θ_JAand the ambient temperature, T_A. The maximum

allowable power dissipation at any temperature is P_D= (T_Jmax − T_A)/θ_JAor the number given in the Absolute Maximum Ratings, whichever is lower.

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book for other methods of soldering surface mount devices.

Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V_A+ or 5V below

GND will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage

magnitude of selected or unselected analog input go above V_A+ or below GND by more than 50 mV. As an example, if V_A+ is 4.5 V_DC, full-scale input voltage

must be ≤4.55 V_DCto ensure accurate conversions.

1135402

Note 8: To guarantee accuracy, it is required that the V_A+ and V_D+ be connected together to the same power supply with separate bypass capacitors at each V

⁺pin.

Note 9: With the test condition for V_REF(V_REF+ − V_REF−) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.

Note 10: Typical figures are at T_J= T_A= 25°C and represent most likely parametric norm.

Note 11: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-

scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figures 2, 3).

Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions

between 1 to 0 and 0 to +1 (see Figure 4).

Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.

Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.

Note 16: Channel leakage current is measured after the channel selection.

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10

Note 17: Timing specifications are tested at the TTL logic levels, V_IL= 0.4V for a falling edge and V_IH= 2.4V for a rising edge. TRI-STATE output voltage is forced

to 1.4V.

Note 18: The ADC12030 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will

result in a maximum repeatability uncertainty of 0.2 LSB.

Note 19: If SCLK and CCLK are driven from the same clock source, then t_Ais 6, 10, 18 or 34 clock periods minimum and maximum.

Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output

data from these modes are not an indication of the accuracy of a conversion result.

1135410

FIGURE 1. Transfer Characteristic

1135411

FIGURE 2. Simplified Error Curve vs. Output Code without Auto-Calibration or Auto-Zero Cycles

11

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1135412

FIGURE 3. Simplified Error Curve vs. Output Code after Auto-Calibration Cycle

1135413

FIGURE 4. Offset or Zero Error Voltage

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12

Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-

calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9)

Linearity Error Change

vs. Clock Frequency

Linearity Error Change

vs. Temperature

1135453

1135455

1135457

1135454

1135456

1135458

Linearity Error Change

vs. Reference Voltage

Linearity Error Change

vs. Supply Voltage

Full-Scale Error Change

vs. Clock Frequency

Full-Scale Error Change

vs. Temperature

13

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Full-Scale Error Change

vs. Reference Voltage

Full-Scale Error Change

vs. Supply Voltage

1135460

1135459

Zero Error Change

vs. Clock Frequency

Zero Error Change

vs. Temperature

1135461

1135462

Zero Error Change

vs. Reference Voltage

Zero Error Change

vs. Supply Voltage

1135464

1135463

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14

Analog Supply Current

vs. Temperature

Digital Supply Current

vs. Clock Frequency

1135465

1135466

Digital Supply Current

vs. Temperature

1135467

15

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Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign mode

after auto-calibration unless otherwise specified.

Bipolar Spectral Response

with 1 kHz Sine Wave Input

Bipolar Spectral Response

with 10 kHz Sine Wave Input

1135468

1135470

1135472

1135469

1135471

1135473

Bipolar Spectral Response

with 20 kHz Sine Wave Input

Bipolar Spectral Response

with 30 kHz Sine Wave Input

Bipolar Spectral Response

with 40 kHz Sine Wave Input

Bipolar Spectral Response

with 50 kHz Sine Wave Input

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16

Bipolar Spurious Free

Dynamic Range

Unipolar Signal-to-Noise Ratio

vs. Input Frequency

1135474

1135475

Unipolar Signal-to-Noise

+ Distortion Ratio

vs. Input Frequency

Unipolar Signal-to-Noise

+ Distortion Ratio

vs. Input Signal Level

1135476

1135477

Unipolar Spectral Response

with 1 kHz Sine Wave Input

Unipolar Spectral Response

with 10 kHz Sine Wave Input

1135478

1135479

17

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Unipolar Spectral Response

with 20 kHz Sine Wave Input

Unipolar Spectral Response

with 30 kHz Sine Wave Input

1135480

1135481

Unipolar Spectral Response

with 40 kHz Sine Wave Input

Unipolar Spectral Response

with 50 kHz Sine Wave Input

1135482

1135483

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18

Test Circuits

DO “TRI-STATE” (t_1H, t_OH

)

DO except “TRI-STATE”

1135403

1135404

Leakage Current

1135405

Timing Diagrams

DO Falling and Rising Edge

DO “TRI-STATE” Falling and Rising Edge

1135418

1135419

DI Data Input Timing

1135420

19

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DO Data Output Timing Using CS

1135421

DO Data Output Timing with CS Continuously Low

1135422

ADC12038 Auto Cal or Auto Zero

1135423

Note: DO output data is not valid during this cycle.

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20

ADC12038 Read Data without Starting a Conversion Using CS

1135424

ADC12038 Read Data without Starting a Conversion with CS Continuously Low

1135425

21

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ADC12038 Conversion Using CS with 8-Bit Digital Output Format

1135426

ADC12038 Conversion Using CS with 16-Bit Digital Output Format

1135451

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22

ADC12038 Conversion with CS Continuously Low and 8-Bit Digital Output Format

1135428

ADC12038 Conversion with CS Continuously Low and 16-Bit Digital Output Format

1135429

23

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ADC12038 Software Power Up/Down Using CS with 16-Bit Digital Output Format

1135452

ADC12038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format

1135431

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24

ADC12038 Hardware Power Up/Down

1135432

Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will

be stored in the output shift register.

ADC12038 Configuration Modification—Example of a Status Read

1135433

Note: In order for all 9 bits of Status Information to be accessible, the last conversion programmed before Cycle N needs to have a resolution of 8 bits plus sign,

12 bits, 12 bits plus sign, or greater.

25

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1135435

*Tantalum

**Monolithic Ceramic or better

FIGURE 5. Recommended Power Supply Bypassing and Grounding

1135434

FIGURE 6. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins

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26

Format and Set-Up Tables

TABLE 1. Data Out Formats

DO Formats

DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB1 DB1 DB1 DB1 DB1 DB1 DB16

0

1

2

3

4

5

17

Bits

X

9

5

3

0

8

4

3

Sign MSB 10

9

5

1

7

8

4

7

3

6

5

4

3

2

1

LSB

MSB 13

First Bits

Sign MSB 10

Sign MSB

8

4

7

3

5

6

2

6

9

5

1

6

2

1

LSB

9

Bits

6

2

0

9

5

2

LSB

8

with

Sign

17

Bits

LSB

0

1

0

9

10 MSB Sign

X

2

0

X

1

0

X

LSB 13

First Bits

8

9

Bits

MSB Sign

16

Bits

MSB 10

8

4

7

3

6

2

5

1

4

3

0

LSB

MSB 12

First Bits

MSB 10

7

3

4

6

2

5

LSB

8

Bits

MSB

LSB

6

1

LSB

7

without

sign

16

Bits

8

9

10 MSB

LSB 12

First Bits

7

8

Bits

MSB

X = High or Low state.

27

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TABLE 2. ADC12038 Multiplexer Addressing

Analog Channel Addressed

A/D Input

Polarity

Assignment

Multiplexer Output

Channel

and Assignment

with A/DIN1 tied to MUXOUT1

and A/DIN2 tied to MUXOUT2

MUX Address

Assignment

Mode

DI0 DI1 DI2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CO A/DIN1 A/DIN2 MUXOUT MUXOUT

M

1

2

L

H

L

+

−

+

−

+

CH0

CH2

CH4

CH6

CH0

CH2

CH4

CH6

CH0

CH2

CH4

CH6

CH1

CH3

CH5

CH7

CH1

CH3

CH5

CH7

CH1

CH3

CH5

CH7

COM

−

+

−

+

−

L

H

L

+

−

+

−

L

H

L

+

−

+

−

Differential

L

H

L

+

L

H

L

+

L

H

L

+

L

H

L

+

H

−

L

H

L

H

L

H

L

Single-Ended

H

+

L

H

L

+

H

+

H

+

TABLE 3. ADC12034 Multiplexer Addressing

Analog Channel Addressed

and Assignment

with A/DIN1 tied to MUXOUT1

and A/DIN2 tied to MUXOUT2

A/D Input Polarity

Assignment

Multiplexer Output

Channel Assignment

MUX Address

Mode

DI0

DI1

L

DI2

CH0

CH1

CH2

CH3 COM

A/DIN1

A/DIN2

MUXOUT1

CH0

MUXOUT2

CH1

L

H

L

+

−

+

−

+

L

+

−

+

CH2

CH3

−

Differential

L

H

L

+

CH0

CH1

−

L

H

L

+

CH2

CH3

H

+

CH0

COM

−

L

H

L

CH2

Single-Ended

H

CH1

H

+

CH3

−

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28

TABLE 4. ADC12032 and ADC12030 Multiplexer Addressing

Analog Channel Addressed

and Assignment

with A/DIN1 tied to MUXOUT1

and A/DIN2 tied to MUXOUT2

A/D Input Polarity

Assignment

Multiplexer Output

Channel Assignment

MUX Address

Mode

DI0

L

DI1

L

CH0

CH1

COM

A/DIN1

A/DIN2

MUXOUT1 MUXOUT2

+

−

+

−

+

CH0

CH1

−

+

−

+

Differential

L

H

L

COM

−

Single-Ended

H

+

Note:

ADC12030 and ADC12H030 do not have A/DIN1, A/DIN2, MUX-

OUT1 and MUXOUT2 pins.

TABLE 5. Mode Programming

DI3 DI4 DI5 DI6 DI7

ADC12038

ADC12034

DI0

DI1

DI2

DI3 DI4 DI5 DI6

DO Format

(next Conversion

Cycle)

Mode Selected

(Current)

ADC12030

and

DI0

DI1

DI2 DI3 DI4 DI5

ADC12032

See Tables 2, 3 or Table 4

L

H

L

12 Bit Conversion

12 or 13 Bit MSB First

16 or 17 Bit MSB First

8 or 9 Bit MSB First

12 or 13 Bit MSB First

12 or 13 Bit LSB First

16 or 17 Bit LSB First

8 or 9 Bit LSB First

12 or 13 Bit LSB First

No Change

L

H

L

8 Bit Conversion

L

H

L

12 Bit Conversion of Full-Scale

12 Bit Conversion

See Tables 2, 3 or Table 4

L

H

L

H

L

12 Bit Conversion

L

H

L

8 Bit Conversion

L

H

L

H

L

H

L

H

L

H

L

12 Bit Conversion of Offset

Auto Cal

H

L

H

L

Auto Zero

No Change

L

H

L

Power Up

No Change

L

H

L

Power Down

No Change

H

Read Status Register

Data Out without Sign

Data Out with Sign

No Change

L

H

L

No Change

L

No Change

H

Acquisition Time—6 CCLK Cycles

Acquisition Time—10 CCLK Cycles

Acquisition Time—18 CCLK Cycles

Acquisition Time—34 CCLK Cycles

User Mode

No Change

L

No Change

L

No Change

L

No Change

H

No Change

Test Mode

(CH1–CH7 become Active Outputs)

H

X

H

No Change

Note: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first, and user mode.

X = Don't Care

TABLE 6. Conversion/Read Data Only Mode Programming

CS

L

CONV

PD

L

Mode

L

H

X

See Table 5 for Mode

L

Read Only (Previous DO Format). No Conversion.

H

X

L

Idle

H

Power Down

X = Don't Care

29

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TABLE 7. Status Register

Status Bit

Location

DB0

PU

DB1

DB2

Cal

DB3

DB4

DB5

DB6

Sign

DB7

DB8

Status Bit

PD

8 or 9

12 or 13

16 or 17

Justification Test Mode

Device Status

DO Output Format Status

When “High” When “High”

“High”

indicates

an 8 or 9 bit 12 or 13 bit 16 or 17 bit that the

“High”

the

conversion

the device is

in test mode.

indicates a indicates a indicates

Power Up Power

Sequence Down

an Auto-

Cal

result will be When “Low”

output MSB the device is

format

sign bit is

included.

When

“Low” the

sign bit is

not

is in

progress

Sequence Sequence

Function

first. When

“Low” the

result will be

output LSB

first.

in user mode.

is in

progress

included.

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30

events necessary for a Data Out without Sign, Data Out with

Sign, or 6/10/18/34 CCLK Acquisition time mode selection.

Table 5 describes the actual data necessary to be input to the

ADC to accomplish this configuration modification. The next

instruction, shown in Figure 8, issued to the A/D starts con-

version N+1 with 8 bits of resolution formatted MSB first.

Again the data output during this I/O cycle is the data from

conversion N.

Applications Information

Some of the device/package combinations are obsolete

and are described here for reference only. Please see our

web site for availability.

1.0 DIGITAL INTERFACE

1.1 Interface Concepts

The number of SCLKs applied to the A/D during any conver-

sion I/O sequence should vary in accord with the data out

word format chosen during the previous conversion I/O se-

quence. The various formats and resolutions available are

shown in Table 1. In Figure 8, since 8-bit, without sign, MSB

first format was chosen during I/O sequence 4, the number of

SCLKs required during I/O sequence 5 is 8. In the following

I/O sequence the format changes to 12-bit without sign MSB

first; therefore the number of SCLKs required during I/O se-

quence 6 changes accordingly to 12.

The example in Figure 7 shows a typical sequence of events

after the power is applied to the ADC12030/2/4/8:

1135436

FIGURE 7. Typical Power Supply Power Up Sequence

1.3 CS Low Continuously Considerations

When CS is continuously low, it is important to transmit the

exact number of SCLK pulses that the ADC expects. Not do-

ing so will desynchronize the serial communications to the

ADC. When the supply power is first applied to the ADC, it will

expect to see 13 SCLK pulses for each I/O transmission. The

number of SCLK pulses that the ADC expects to see is the

same as the digital output word length. The digital output word

length is controlled by the Data Out (DO) format. The DO for-

mat maybe changed any time a conversion is started or when

the sign bit is turned on or off. The table below details out the

number of clock periods required for different DO formats:

The first instruction input to the A/D via DI initiates Auto-Cal.

The data output on DO at that time is meaningless and is

completely random. To determine whether the Auto Cal has

been completed, a read status instruction is issued to the A/

D. Again the data output at that time has no significance since

the Auto Cal procedure modifies the data in the output shift

register. To retrieve the status information, an additional read

status instruction is issued to the A/D. At this time the status

data is available on DO. If the Cal signal in the status word,

is low Auto Cal has been completed. Therefore, the next in-

struction issued can start a conversion. The data output at this

time is again status information. To keep noise from corrupt-

ing the A/D conversion, status can not be read during a

conversion. If CS is strobed and is brought low during a con-

version, that conversion is prematurely ended. EOC can be

used to determine the end of a conversion or the A/D con-

troller can keep track in software of when it would be appro-

priate to communicate to the A/D again. Once it has been

determined that the A/D has completed a conversion, another

instruction can be transmitted to the A/D. The data from this

conversion can be accessed when the next instruction is is-

sued to the A/D.

Number of

DO Format

SCLKs

Expected

SIGN OFF

SIGN ON

SIGN OFF

SIGN ON

SIGN OFF

SIGN ON

8

ꢁ8-Bit MSB or LSB First

9

12

13

16

17

12-Bit MSB or LSB First

16-Bit MSB or LSB first

Note, when CS is low continuously it is important to transmit

the exact number of SCLK cycles, as shown in the timing di-

agrams. Not doing so will desynchronize the serial commu-

nication to the A/D. (See Section 1.3.)

If erroneous SCLK pulses desynchronize communications,

the simplest way to recover is by cycling the power supply to

the device. Not being able to easily resynchronize the device

is a shortcoming of leaving CS low continuously.

1.2 Changing Configuration

The number of clock pulses required for an I/O exchange may

be different for the case when CS is left low continuously vs.

the case when CS is cycled. Take the I/O sequence detailed

in Figure 7 (Typical Power Supply Sequence) as an example.

The table below lists the number of SCLK pulses required for

each instruction:

The configuration of the ADC12030/2/4/8 on power up de-

faults to 12-bit plus sign resolution, 12- or 13-bit MSB First,

10 CCLK acquisition time, user mode, no Auto Cal, no Auto

Zero, and power up mode. Changing the acquisition time and

turning the sign bit on and off requires an 8-bit instruction to

be issued to the ADC. This instruction will not start a conver-

sion. The instructions that select a multiplexer address and

format the output data do start a conversion. Figure 8 de-

scribes an example of changing the configuration of the

ADC12030/2/4/8.

CS Low

Instruction

Auto Cal

CS Strobed

Continuously

13 SCLKs

8 SCLKs

13 SCLKs

Read Status

During I/O sequence 1, the instruction on DI configures the

ADC12030/2/4/8 to do a conversion with 12-bit +sign resolu-

tion. Notice that when the 6 CCLK Acquisition and Data Out

without Sign instructions are issued to the ADC, I/O se-

quences 2 and 3, a new conversion is not started. The data

output during these instructions is from conversion N which

was started during I/O sequence 1. The Configuration Modi-

fication timing diagram describes in detail the sequence of

Read Status

12-Bit + Sign Conv 1

12-Bit + Sign Conv 2

1.4 Analog Input Channel Selection

The data input on DI also selects the channel configuration

(see Tables 2, 3, 4, 5). In Figure 8 the only times when the

31

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channel configuration could be modified is during I/O se-

quences 1, 4, 5 and 6. Input channels are reselected before

the start of each new conversion. Shown below is the data bit

stream required on DI, during I/O sequence number 4 in Fig-

ure 8, to set CH1 as the positive input and CH0 as the

negative input for the different versions of ADCs:

1.5 Power Up/Down

The ADC may be powered down by taking the PD pin HIGH

or by the instruction input on DI (see Table 5 and Table 6, and

the Power Up/Down timing diagrams). When the ADC is pow-

ered down in this way, the A/D conversion circuitry is deacti-

vated but the digital I/O circuitry is kept active. Hardware

power up/down is controlled by the state of the PD pin. Soft-

ware power-up/down is controlled by the instruction issued to

the ADC. If a software power up instruction is issued to the

ADC while a hardware power down is in effect (PD pin high)

the device will remain in the power-down state. If a software

power down instruction is issued to the ADC while a hardware

power up is in effect (PD pin low), the device will power down.

When the device is powered down by software, it may be

powered up by either issuing a software power up instruction

or by taking PD pin high and then low. If the power down

command is issued during an A/D conversion, that conversion

is interrupted, so the data output after power up cannot be

relied upon.

DI Data

Part

Number

DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

ADC12H030

ADC12030

L

H

L

H

L

X

L

X

L

ADC12H032

ADC12032

ADC12H034

ADC12034

H

L

ADC12H038

ADC12038

L

H

Where X can be a logic high (H) or low (L).

1135437

FIGURE 8. Changing the ADC's Conversion Configuration

Instruction

1.6 User Mode and Test Mode

DI Data

An instruction may be issued to the ADC to put it into test

mode, which is used by the manufacturer to verify complete

functionality of the device. During test mode CH0–CH7 be-

come active outputs. If the device is inadvertently put into the

test mode with CS continuously low, the serial communica-

tions may be desynchronized. Synchronization may be re-

gained by cycling the power supply voltage to the device.

Cycling the power supply voltage will also set the device into

user mode. If CS is used in the serial interface, the ADC may

be queried to see what mode it is in. This is done by issuing

a “read STATUS register” instruction to the ADC. When bit 9

of the status register is high, the ADC is in test mode; when

bit 9 is low the ADC, is in user mode. As an alternative to

cycling the power supply, an instruction sequence may be

used to return the device to user mode. This instruction se-

quence must be issued to the ADC using CS. The following

table lists the instructions required to return the device to user

mode. Note that this entire sequence, including both Test

Mode and User Mode values, should be sent to recover from

the test mode.

DI0 DI1 DI2 DI3 DI4 DI5 DI6 D17

TEST MODE

H

L

H

X

L

X

L

X

L

H

L

H

L

Reset

Test Mode

Instructions

L

H

L

USER MODE

Power Up

H

L

Set DO with or

without Sign or L

L

H

L

H

L

H

Set

H

H or

L

Acquisition

or L

L

H

L

Time

Start a

Conversion or L

H

H or

L

H

or L

H or

L

H

or L

H or H or

L

X = Don't Care

The power up, data with or without sign, and acquisition time

instructions should be resent after returning to the user mode.

This is to ensure that the ADC is in the required state before

a conversion is started.

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32

1.7 Reading the Data Without Starting a Conversion

with the COM input as the zero reference or any combination

thereof (see Figure 9). The difference between the voltages

The data from a particular conversion may be accessed with-

out starting a new conversion by ensuring that the CONV line

is taken high during the I/O sequence. See the Read Data

timing diagrams. Table 6 describes the operation of the

CONV pin.

+

−

on the V_REFand V_REFpins determines the input voltage

span (V_REF). The analog input voltage range is 0 to V_A⁺. Neg-

ative digital output codes result when V_IN⁻> V_IN⁺. The actual

voltage at V_IN⁻or V_IN⁺cannot go below AGND.

2.0 THE ANALOG MULTIPLEXER

For the ADC12038, the analog input multiplexer can be con-

figured with 4 differential channels or 8 single ended channels

4 Differential

Channels

8 Single-Ended Channels

with COM

as Zero Reference

1135438

1135439

FIGURE 9.

Differential

Configuration

Single-Ended

Configuration

1135440

1135441

A/DIN1 and A/DIN2 can be assigned as the + or − input

A/DIN1 is + input

A/DIN2 is − input

FIGURE 10.

CH0, CH2, CH4, and CH6 can be assigned to the MUXOUT1

pin in the differential configuration, while CH1, CH3, CH5, and

CH7 can be assigned to the MUXOUT2 pin. In the differential

configuration, the analog inputs are paired as follows: CH0

with CH1, CH2 with CH3, CH4 with CH5 and CH6 with CH7.

The A/DIN1 and A/DIN2 pins can be assigned positive or

negative polarity.

The Multiplexer assignment tables for the ADC12030,2,4,8

(Tables 2, 3, 4) summarize the aforementioned functions for

the different versions of A/Ds.

2.1 Biasing for Various Multiplexer Configurations

Figure 11 is an example of biasing the device for single-ended

operation. The sign bit is always low. The digital output range

is 0 0000 0000 0000 to 0 1111 1111 1111. One LSB is equal

to 1 mV (4.1V/4096 LSBs).

With the single-ended multiplexer configuration CH0 through

CH7 can be assigned to the MUXOUT1 pin. The COM pin is

always assigned to the MUXOUT2 pin. A/DIN1 is assigned as

the positive input; A/DIN2 is assigned as the negative input.

(See Figure 10).

33

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1135446

FIGURE 11. Single-Ended Biasing

For pseudo-differential signed operation, the biasing circuit

shown in Figure 12 shows a signal AC coupled to the ADC.

This gives a digital output range of −4096 to +4095. With a

2.5V reference, 1 LSB is equal to 610 µV. Although, the ADC

is not production tested with a 2.5V reference, when V_A⁺and

V_Dare +5.0V linearity error typically will not change more

than 0.1 LSB (see the curves in the Typical Electrical Char-

acteristics Section). With the ADC set to an acquisition time

of 10 clock periods, the input biasing resistor needs to be

600Ω or less. Notice though that the input coupling capacitor

needs to be made fairly large to bring down the high pass

corner. Increasing the acquisition time to 34 clock periods

(with a 5 MHz CCLK frequency) would allow the 600Ω to in-

crease to 6k, which with a 1 µF coupling capacitor would set

the high pass corner at 26 Hz. Increasing R, to 6k would allow

R₂to be 2k.

+

1135447

FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC

An alternative method for biasing pseudo-differential opera-

tion is to use the +2.5V from the LM4040 to bias any amplifier

circuits driving the ADC as shown in Figure 13. The value of

the resistor pull-up biasing the LM4040-2.5 will depend upon

the current required by the op amp biasing circuitry.

to set the full scale voltage at exactly 2.048V and a lower

grade LM4040D-2.5 to bias up everything to 2.5V as shown

in Figure 14 will allow the use of all the ADC's digital output

range of −4096 to +4095 while leaving plenty of head room

for the amplifier.

In the circuit of Figure 13 some voltage range is lost since the

amplifier will not be able to swing to +5V and GND with a

single +5V supply. Using an adjustable version of the LM4041

Fully differential operation is shown in Figure 15. One LSB for

this case is equal to (4.1V/4096) = 1 mV.

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34

1135448

FIGURE 13. Alternative Pseudo-Differential Biasing

1135449

FIGURE 14. Pseudo-Differential Biasing without the Loss of Digital Output Range

35

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1135450

FIGURE 15. Fully Differential Biasing

3.0 REFERENCE VOLTAGE

an initial adjustment to null reference voltage induced full-

scale errors.

The difference in the voltages applied to the V_REF⁺and V_REF

⁻defines the analog input span (the difference between the

voltage applied between two multiplexer inputs or the voltage

applied to one of the multiplexer inputs and analog ground),

over which 4095 positive and 4096 negative codes exist. The

Below are recommended references along with some key

specifications.

Output

Voltage

Tolerance

Temperature

Coefficient

Part Number

LM4041CI-Adj

+

−

voltage sources driving V_REFor V_REFmust have very low

output impedance and noise. The circuit in Figure 16 is an

example of a very stable reference appropriate for use with

the device.

±0.5%

±0.1%

±100ppm/°C

±50ppm/°C

±10ppm/°C

±3.0ppm/°C

±2ppm/°C

LM4040AI-4.1

LM4120AI-4.1

LM4121AI-4.1

LM4050AI-4.1

LM4030AI-4.1

LM4140AC-4.1

Circuit of Figure 16

±0.2%

±0.1%

±0.05%

±0.1%

Adjustable

The reference voltage inputs are not fully differential. The

ADC12030/2/4/8 will not generate correct conversions or

1135442

comparisons if V_REFis taken below V_REF⁻. Correct conver-

+

*Tantalum

sions result when V_REF⁺and V_REF⁻differ by 1V and remain,

at all times, between ground and V_A⁺. The V_REFcommon

mode range, (V_REF⁺+ V_REF⁻)/2 is restricted to (0.1 × V_A⁺) to

(0.6 × V_A⁺). Therefore, with V_A⁺= 5V the center of the refer-

ence ladder should not go below 0.5V or above 3.0V. Figure

FIGURE 16. Low Drift Extremely

Stable Reference Circuit

The ADC12030/2/4/8 can be used in either ratiometric or ab-

solute reference applications. In ratiometric systems, the ana-

log input voltage is proportional to the voltage used for the

ADC's reference voltage. When this voltage is the system

power supply, the V_REF⁺pin is connected to V_A⁺and V_REF⁻is

connected to ground. This technique relaxes the system ref-

erence stability requirements because the analog input volt-

age and the ADC reference voltage move together. This

maintains the same output code for given input conditions.

For absolute accuracy, where the analog input voltage varies

between very specific voltage limits, a time and temperature

stable voltage source can be connected to the reference in-

puts. Typically, the reference voltage's magnitude will require

17 is a graphic representation of the voltage restrictions on

−

V_REF⁺and V_REF

.

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36

6.0 INPUT SOURCE RESISTANCE

For low impedance voltage sources (<600Ω), the input charg-

ing current will decay, before the end of the S/H's acquisition

time of 2 µs (10 CCLK periods with f_C= 5 MHz), to a value

that will not introduce any conversion errors. For high source

impedances, the S/H's acquisition time can be increased to

18 or 34 CCLK periods. For less ADC resolution and/or slower

CCLK frequencies the S/H's acquisition time may be de-

creased to 6 CCLK periods. To determine the number of clock

periods (N_c) required for the acquisition time with a specific

source impedance for the various resolutions the following

equations can be used:

12 Bit + Sign N_C= [R_S+ 2.3] × f_C× 0.824

ꢀꢁ8 Bit + Sign N_C= [R_S+ 2.3] × f_C× 0.57

Where f_Cis the conversion clock (CCLK) frequency in MHz

and R_Sis the external source resistance in kΩ. As an exam-

ple, operating with a resolution of 12 Bits+sign, a 5 MHz clock

frequency and maximum acquisition time of 34 conversion

clock periods the ADC's analog inputs can handle a source

impedance as high as 6 kΩ. The acquisition time may also be

extended to compensate for the settling or response time of

external circuitry connected between the MUXOUT and A/

DIN pins.

1135445

FIGURE 17. V_REFOperating Range

An acquisition is started by a falling edge of SCLK and ended

by a rising edge of CCLK (see timing diagrams). If SCLK and

CCLK are asynchronous one extra CCLK clock period may

be inserted into the programmed acquisition time for synchro-

nization. Therefore with asynchronous SCLK and CCLKs the

acquisition time will change from conversion to conversion.

4.0 ANALOG INPUT VOLTAGE RANGE

The ADC12030/2/4/8's fully differential ADC generate a two's

complement output that is found by using the equations

shown below:

for (12-bit) resolution the Output Code =

7.0 INPUT BYPASS CAPACITANCE

External capacitors (0.01 µF–0.1 µF) can be connected be-

tween the analog input pins, CH0–CH7, and analog ground

to filter any noise caused by inductive pickup associated with

long input leads. These capacitors will not degrade the con-

version accuracy.

for (8-bit) resolution the Output Code =

8.0 NOISE

The leads to each of the analog multiplexer input pins should

be kept as short as possible. This will minimize input noise

and clock frequency coupling that can cause conversion er-

rors. Input filtering can be used to reduce the effects of the

noise sources.

Round off to the nearest integer value between −4096 to 4095

for 12-bit resolution and between −256 to 255 for 8-bit reso-

lution if the result of the above equation is not a whole number.

Examples are shown in the table below:

9.0 POWER SUPPLIES

Digital Output

Noise spikes on the V_A⁺and V_D⁺supply lines can cause con-

version errors; the comparator will respond to the noise. The

ADC is especially sensitive to any power supply spikes that

occur during the auto-zero or linearity correction. The mini-

mum power supply bypassing capacitors recommended are

low inductance tantalum capacitors of 10 µF or greater par-

alleled with 0.1 µF monolithic ceramic capacitors. More or

different bypassing may be necessary depending on the over-

all system requirements. Separate bypass capacitors should

be used for the V_A⁺and V_D⁺supplies and placed as close as

possible to these pins.

+

−

+

−

V_REF

V_IN

Code

+2.5V

+1V

0V

+1.5V

+3V

0V

0,1111,1111,1111

0,1011,1011,1000

+4.096V

0V

+2.499V +2.500V 1,1111,1111,1111

0V +4.096V 1,0000,0000,0000

0V

5.0 INPUT CURRENT

At the start of the acquisition window (t_A) a charging current

flows into or out of the analog input pins (A/DIN1 and A/DIN2)

depending on the input voltage polarity. The analog input pins

are CH0–CH7 and COM when A/DIN1 is tied to MUXOUT1

and A/DIN2 is tied to MUXOUT2. The peak value of this input

current will depend on the actual input voltage applied, the

source impedance and the internal multiplexer switch on re-

sistance. With MUXOUT1 tied to A/DIN1 and MUXOUT2 tied

to A/DIN2 the internal multiplexer switch on resistance is typ-

ically 1.6 kΩ. The A/DIN1 and A/DIN2 mux on resistance is

typically 750Ω.

10.0 GROUNDING

The ADC12030/2/4/8's performance can be maximized

through proper grounding techniques. These include the use

of separate analog and digital areas of the board with analog

and digital components and traces located only in their re-

spective areas. Bypass capacitors of 0.01 µF and 0.1 µF

surface mount capacitors and a 10 µF are recommended at

each of the power supply pins for best performance. These

37

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capacitors should be located as close to the bypassed pin as

practical, especially the smaller value capacitors.

to digitize AC signals without significant spectral errors and

without adding noise to the digitized signal. Dynamic charac-

teristics such as signal-to-noise (S/N), signal-to-noise + dis-

tortion ratio (S/(N + D)), effective bits, full power bandwidth,

aperture time and aperture jitter are quantitative measures of

the A/D converter's capability.

11.0 CLOCK SIGNAL LINE ISOLATION

The ADC12030/2/4/8's performance is optimized by routing

the analog input/output and reference signal conductors as

far as possible from the conductors that carry the clock signals

to the CCLK and SCLK pins. Maintaining a separation of at

least 7 to 10 times the height of the clock trace above its ref-

erence plane is recommended.

An A/D converter's AC performance can be measured using

Fast Fourier Transform (FFT) methods. A sinusoidal wave-

form is applied to the A/D converter's input, and the transform

is then performed on the digitized waveform. S/(N + D) and

S/N are calculated from the resulting FFT data, and a spectral

plot may also be obtained. Typical values for S/N are shown

in the table of Electrical Characteristics, and spectral plots of

S/(N + D) are included in the typical performance curves.

12.0 THE CALIBRATION CYCLE

A calibration cycle needs to be started after the power sup-

plies, reference, and clock have been given enough time to

stabilize after initial turn-on. During the calibration cycle, cor-

rection values are determined for the offset voltage of the

sampled data comparator and any linearity and gain errors.

These values are stored in internal RAM and used during an

analog-to-digital conversion to bring the overall full-scale, off-

set, and linearity errors down to the specified limits. Full-scale

error typically changes ±0.4 LSB over temperature and lin-

earity error changes even less; therefore it should be neces-

sary to go through the calibration cycle only once after power

up if the Power Supply Voltage and the ambient temperature

do not change significantly (see the curves in the Typical Per-

formance Characteristics).

The A/D converter's noise and distortion levels will change

with the frequency of the input signal, with more distortion and

noise occurring at higher signal frequencies. This can be seen

in the S/(N + D) versus frequency curves.

Effective number of bits can also be useful in describing the

A/D's noise and distortion performance. An ideal A/D con-

verter will have some amount of quantization noise, deter-

mined by its resolution, and no distortion, which will yield an

optimum S/(N + D) ratio given by the following equation:

S/(N + D) = (6.02 × n + 1.76) dB

where "n" is the A/D's resolution in bits.

13.0 THE AUTO-ZERO CYCLE

Since the ideal A/D converter has no distortion, the effective

bits of a real A/D converter, therefore, can be found by:

To correct for any change in the zero (offset) error of the A/D,

the auto-zero cycle can be used. It may be necessary to do

an auto-zero cycle whenever the ambient temperature or the

power supply voltage change significantly. (See the curves

titled “Zero Error Change vs. Ambient Temperature” and “Ze-

ro Error Change vs. Supply Voltage” in the Typical Perfor-

mance Characteristics.)

n(effective) = ENOB = (S/(N + D) - 1.76 / 6.02

As an example, this device with a differential signed 5V, 1 kHz

sine wave input signal will typically have a S/(N + D) of 77 dB,

which is equivalent to 12.5 effective bits.

15.0 AN RS232 SERIAL INTERFACE

Shown on the following page is a schematic for an RS232

interface to any IBM and compatible PCs. The DTR, RTS, and

CTS RS232 signal lines are buffered via level translators and

connected to the ADC12038's DI, SCLK, and DO pins, re-

spectively. The D flip flop drives the CS control line.

14.0 DYNAMIC PERFORMANCE

Many applications require the A/D converter to digitize AC

signals, but the standard DC integral and differential nonlin-

earity specifications will not accurately predict the A/D

converter's performance with AC input signals. The important

specifications for AC applications reflect the converter's ability

1135444

Note: V_A⁺, V_D⁺, and V_REF⁺on the ADC12038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF caps.

The assignment of the RS232 port is shown below

B7

X

B6

X

B5

X

B4

CTS

0

B3

X

B2

X

B1

B0

Input Address

3FE

3FC

X

COM1

Output Address

X

RTS DTR

www.national.com

38

A sample program, written in Microsoft QuickBasic, is shown

on the next page. The program prompts for data mode select

instruction to be sent to the A/D. This can be found from the

Mode Programming table shown earlier. The data should be

entered in “1”s and “0”s as shown in the table with DI0 first.

Next the program prompts for the number of SCLKs required

for the programmed mode select instruction. For instance, to

send all “0”s to the A/D, selects CH0 as the +input, CH1 as

the −input, 12-bit conversion, and 13-bit MSB first data output

format (if the sign bit was not turned off by a previous instruc-

tion). This would require 13 SCLK periods since the output

data format is 13 bits.

power up, 12- or 13-bit MSB first, and user mode. Auto Cal,

Auto Zero, Power Up and Power Down instructions do not

change these default settings. The following power up se-

quence should be followed:

1. Run the program

2. Prior to responding to the prompt apply the power to the

ADC12038

3. Respond to the program prompts

It is recommended that the first instruction issued to the

ADC12038 be Auto Cal (see Section 1.1).

The ADC powers up with No Auto Cal, No Auto Zero, 10

CCLK Acquisition Time, 12-bit conversion, data out with sign,

39

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Code Listing:

'variables DOL=Data Out word length, DI=Data string for A/D DI input,

'

DO=A/D result string

'SET CS# HIGH

OUT

10

&H3FC, (&H2 OR INP (&H3FC))

'set RTS HIGH

'set DTR LOW

'set RTS LOW

'set B4 low

&H3FC, (&HFE AND INP(&H3FC))

&H3FC, (&HFD AND INP(&H3FC))

&H3FC, (&HEF AND INP(&H3FC))

LINE INPUT “DI data for ADC12038 (see Mode Table on data sheet)”; DI$

INPUT “ADC12038 output word length (8,9,12,13,16 or 17)”; DOL

20

'SET CS# HIGH

OUT

&H3FC, (&H2 OR INP (&H3FC))

&H3FC, (&HFE AND INP(&H3FC))

&H3FC, (&HFD AND INP(&H3FC))

'set RTS HIGH

'set DTR LOW

'set RTS LOW

'SET CS# LOW

OUT

DO$=

&H3FC, (&H2 OR INP (&H3FC))

'set RTS HIGH

'set DTR HIGH

'set RTS LOW

'reset DO variable

'SET DTR HIGH

'SCLK low

&H3FC, (&H1 OR INP(&H3FC))

&H3FC, (&HFD AND INP(&H3FC))

“ ”

OUT &H3FC, (&H1 OR INP(&H3FC))

OUT &H3FC, (&HFD AND INP(&H3FC))

FOR N=1 TO 8

Temp$=MID$(DI$,N,1)

IF Temp$=“0” THEN

OUT &H3FC,(&H1 OR INP(&H3FC))

ELSE OUT &H3FC, (&HFE AND INP(&H3FC))

END IF

'out DI

OUT &H3FC, (&H2 OR INP(&H3FC))

IF (INP(&H3FE) AND 16)=16 THEN

DO$=DO$+“0”

'SCLK high

ELSE

DO$=DO$+“1”

END IF

'input DO

OUT &H3FC, (&H1 OR INP(&H3FC))

OUT &H3FC, (&HFD AND INP(&H3FC))

NEXT N

'SET DTR HIGH

'SCLK low

IF DOL>8 THEN

FOR N=9 TO DOL

OUT &H3FC, (&H1 OR INP(&H3FC))

OUT &H3FC, (&HFD AND INP(&H3FC))

OUT &H3FC, (&H2 OR INP(&H3FC))

IF (INP(&H3FE) AND &H10)=&H10 THEN

DO$=DO$+“0”

'SET DTR HIGH

'SCLK low

'SCLK high

ELSE

DO$=DO$+“1”

END IF

NEXT N

END IF

OUT

&H3FC, (&HFA AND INP(&H3FC))

'SCLK low and DI high

FOR N=1 TO 500

NEXT N

PRINT DO$

INPUT “Enter “C” to convert else “RETURN” to alter DI data”; s$

IF s$=“C” OR s$=“c” THEN

GOTO 20

ELSE

GOTO 10

END IF

END

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40

Physical Dimensions inches (millimeters) unless otherwise noted

Order Number ADC12030CIWM or ADC12H030CIWM

NS Package Number M16B

Order Number ADC12032CIWM

NS Package Number M20B

41

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Order Number ADC12034CIWM

NS Package Number M24B

Order Number ADC12H034CIMSA

NS Package Number MSA24

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42

Order Number ADC12038CIWM or ADC12H038CIWM

NS Package Number M28B

Order Number ADC12034CIN

NS Package Number N24C

43

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Notes

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是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	EIAJ, SSOP-24	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.44	Is Samacsys：	N
最大模拟输入电压：	5.55 V	最小模拟输入电压：	-0.05 V
最长转换时间：	5.5 µs	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e0
长度：	8.2 mm	最大线性误差 (EL)：	0.0244%
湿度敏感等级：	1	模拟输入通道数量：	4
位数：	12	功能数量：	1
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出位码：	2'S COMPLEMENT BINARY
输出格式：	SERIAL	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	235
认证状态：	Not Qualified	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	2 mm	标称供电电压：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	5.3 mm
Base Number Matches：	1

型号	制造商	描述	替代类型	文档
ADC12H034CIMSA	NSC	Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold	功能相似

型号	制造商	描述	价格	文档
ADC12H034CIN	NSC	Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold	获取价格
ADC12H034CIWM	NSC	Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold	获取价格
ADC12H034CIWM/NOPB	TI	IC,DATA ACQ SYSTEM,4-CHANNEL,13-BIT,SOP,24PIN,PLASTIC	获取价格
ADC12H034CIWMX	ETC	Single-Ended Data Acquisition System	获取价格
ADC12H038	NSC	Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold	获取价格
ADC12H038CIN	NSC	IC 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP28, 0.600 INCH, PLASTIC, DIP-28, Analog to Digital Converter	获取价格
ADC12H038CIWM	NSC	Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold	获取价格
ADC12H038CIWM/NOPB	TI	8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28, SOP-28	获取价格
ADC12H038CIWMX	NSC	Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold	获取价格
ADC12J1600	TI	12 位、1.6GSPS、射频采样模数转换器 (ADC)	获取价格

ADC12H034CIMSAX

ADC12H034CIMSAX 概述

ADC12H034CIMSAX 规格参数

ADC12H034CIMSAX 数据手册

ADC12H034CIMSAX 替代型号

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