CD4023 [NSC]
Buffered Triple 3-Input NAND,NOR Gate; 缓冲的三重3输入NAND，NOR门
| 型号： | CD4023 |
| 厂家： | 
National Semiconductor |
| 描述： | Buffered Triple 3-Input NAND,NOR Gate |
| 文件： | 总6页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
CD4023BM/CD4023BC
Buffered Triple 3-Input NAND Gate
CD4025BM/CD4025BC
Buffered Triple 3-Input NOR Gate
General Description
Features
Wide supply voltage range
High noise immunity
Low power TTL
Y
Y
Y
3.0V to 15V
0.45 V (typ.)
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-chan-
nel enhancement mode transistors. They have equal source
and sink current capabilities and conform to standard B se-
ries output drive. The devices also have buffered outputs
which improve transfer characteristics by providing very
high gain. All inputs are protected against static discharge
DD
fan out of 2 driving 74L
or 1 driving 74LS
compatibility
Y
Y
Y
5V–10V–15V parametric ratings
Symmetrical output characteristics
Maximum input leakage 1 mA at 15V over full
temperature range
with diodes to V
and V
.
SS
DD
Connection Diagrams
CD4023BM/CD4023BC
Dual-In-Line Package
CD4025BM/CD4025BC
Dual-In-Line Package
TL/F/5956–1
TL/F/5956–2
Top View
Top View
Order Number CD4023B or CD4025B
C
1995 National Semiconductor Corporation
TL/F/5956
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
DC Supply Voltage (V
)
DD
5 V to 15 V
DC DC
Input Voltage (V
)
IN
0 V to V
V
DC DD DC
b
a
DC Supply Voltage (V
)
DD
0.5 V to 18 V
DC
DC
Operating Temperature Range (T )
A
b
a
0.5 V
Input Voltage (V
IN
)
0.5 V to V
DC DD
DC
b
b
a
55 C to 125 C
CD4023BM, CD4025BM
CD4023BC, CD4025BC
§
40 C to 85 C
§
§
b
a
65 C to 150 C
Storage Temp. Range (T )
S
§
§
a
§
Power Dissipation (P )
D
Dual-In-Line
Small Outline
700 mW
500 mW
Lead Temperature (T )
L
(Soldering, 10 seconds)
260 C
§
DC Electrical Characteristics CD4023BM, CD4025BM (Note 2)
b
a
a
55 C
§
Typ
25 C
125 C
§
Typ
§
Min Max
Symbol
Parameter
Conditions
Units
Min
Min
Max
e
e
e
I
Quiescent Device Current
V
DD
V
DD
V
DD
5V
10V
15V
0.25
0.5
1.0
0.004 0.25
7.5
15
30
mA
mA
mA
DD
0.005
0.006
0.5
1.0
e
e
e
V
V
V
V
Low Level Output Voltage
V
V
V
5V
10V
15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
OL
OH
IL
DD
DD
DD
e
e
e
High Level Output Voltage V
5V
10V
15V
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
4.95
9.95
14.95
V
V
V
DD
DD
DD
V
V
e
e
e
e
4.5V
Low Level Input Voltage
High Level Input Voltage
V
DD
V
DD
V
DD
5V, V
10V, V
15V, V
1.5
3.0
4.0
2
4
6
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
O
k
k
e
9.0V
13.5V
I
I
1mA
O
O
l
l
O
O
l
l
e
(
e
e
e
e
0.5V
V
DD
V
DD
V
DD
5V, V
O
10V, V
15V, V
3.5
1mA 7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
IH
e
e
1.0V
1.5V
O
O
(
e
e
0.4V
I
I
I
Low Level Output Current
(Note 3)
V
DD
V
DD
V
DD
5V, V
O
e
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.2
8
0.36
0.90
2.4
mA
mA
mA
OL
e
e
10V, V
15V, V
0.5V
1.5V
O
O
e
e
e
e
e
5V, V
O
10V, V
15V, V
b
b
b
b
b
High Level Output Current V
(Note 3)
4.6V
0.64
0.51
0.88
2.2
0.36
0.90
mA
mA
mA
OH
IN
DD
DD
DD
e
e
b
b
b
V
V
9.5V
13.5V
1.6
4.2
1.3
3.4
O
O
b
b
b
b
8
2.4
b
5
e
e
e
e
b
0.10
0.10
b
b
0.10
0.10
b
Input Current
V
DD
V
DD
15V, V
15V, V
0V
15V
10
10b
5
1.0 mA
1.0 mA
IN
IN
Schematic Diagram
CD4023BC/CD4023BM
(/3 Device Shown
*All Inputs Protected
by Standard CMOS Input
Protection Circuit.
TL/F/5956–3
2
DC Electrical Characteristics CD4023BC, CD4025BC (Note 2)
b
a
a
85 C
40 C
§
25 C
§
§
Symbol
Parameter
Conditions
Units
Min Typ Min
Typ
Max Min Max
e
e
e
I
Quiescent Device Current
V
DD
V
DD
V
DD
5V
1.0
2.0
4.0
0.004
0.005
0.006
1.0
2.0
4.0
7.5
15
30
mA
mA
mA
DD
10V
15V
e
e
e
V
V
V
V
Low Level Output Voltage
V
V
V
5V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
OL
OH
IL
DD
DD
DD
10V
15V
e
e
e
High Level Output Voltage V
5V
4.95
9.95
4.95
9.95
5
4.95
9.95
V
V
V
DD
DD
DD
V
V
10V
15V
10
15
14.95
14.95
14.95
e
e
e
e
4.5V
Low Level Input Voltage
High Level Input Voltage
V
DD
V
DD
V
DD
5V, V
1.5
3.0
4.0
2
4
6
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
O
k
k
e
e
10V, V
15V, V
9.0V
I
I
1mA
O
O
l
l
O
O
l
l
13.5V
(
e
e
e
e
0.5V
V
DD
V
DD
V
DD
5V, V
O
3.5
3.5
7.0
3
6
9
3.5
7.0
V
V
V
IH
e
e
10V, V
15V, V
1.0V
1.5V
1mA 7.0
O
O
(
11.0
11.0
11.0
e
e
0.4V
I
I
I
Low Level Output Current
(Note 3)
V
DD
V
DD
V
DD
5V, V
O
0.52
1.3
0.44
1.1
0.88
2.2
8
0.36
0.90
2.4
mA
mA
mA
OL
e
e
e
e
10V, V
15V, V
0.5V
1.5V
O
O
3.6
3.0
e
e
e
e
5V, V
O
b
b
b
b
b
High Level Output Current
(Note 3)
V
DD
V
DD
V
DD
4.6V
0.52
0.44
0.88
0.36
0.90
mA
mA
mA
OH
IN
e
e
b
b
b
b
b
2.2
10V, V
15V, V
9.5V
1.3
3.6
1.1
3.0
O
O
b
b
2.4
13.5V
8
b
5
e
e
e
e
b
b
b
b
1.0 mA
Input Current
V
V
15V, V
15V, V
0V
0.3
10
10b
0.3
DD
IN
5
15V
0.3
0.3
1.0
mA
DD
IN
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
e
Note 2: V
0V unless otherwise specified.
and I are tested one output at a time.
SS
Note 3: I
OH
OL
Schematic Diagram
CD4025BM/CD4025BC
(/3 Device Shown
*All Inputs Protected
by Standard CMOS Input
Protection Circuit.
TL/F/5956–4
3
e
e
e
50 pF, R 200k, unless otherwise specified
L
AC Electrical Characteristics* T
25 C, C
§
A
L
CD4023BC
CD4023BM
CD4025BC
CD4025BM
Symbol
Parameter
Conditions
Units
Min
Typ
Max
Min
Typ
Max
e
e
e
t
t
Propagation Delay, High-to-Low Level
V
V
V
5V
130
60
250
100
70
130
60
250
100
70
ns
ns
ns
PHL
DD
DD
DD
10V
15V
40
40
e
e
e
Propagation Delay, Low-to-High Level
Transition Time
V
DD
V
DD
V
DD
5V
110
50
250
100
70
120
60
250
100
70
ns
ns
ns
PLH
10V
15V
35
40
e
e
e
t
t
,
V
DD
V
DD
V
DD
5V
90
50
40
200
100
80
90
50
40
200
100
80
ns
ns
ns
THL
10V
15V
TLH
C
C
Average Input Capacitance
Any Input
Any Gate
5
7.5
5
7.5
pF
pF
IN
Power Dissipation Capacity (Note 4)
17
17
PD
*AC Parameters are guaranteed by DC correlated testing.
Note 4: C determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics Application
PD
Note AN-90.
4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4023BMJ, CD4023BCJ, CD4025BMJ or CD4025BCJ
NS Package Number J14A
5
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number CD4023BMN, CD4023BCN, CD4025BMN or CD4025BCN
NS Package Number N14A
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