CD4723BMN [NSC]
Dual 4-Bit, 8-Bit Addressable Latch; 双4位， 8位可寻址锁存器
| 型号： | CD4723BMN |
| 厂家： | 
National Semiconductor |
| 描述： | Dual 4-Bit, 8-Bit Addressable Latch |
| 文件： | 总8页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
CD4723BM/CD4723BC Dual 4-Bit Addressable Latch
CD4724BM/CD4724BC 8-Bit Addressable Latch
General Description
e
e
low), changing more than one
The CD4723B is a dual 4-bit addressable latch with com-
mon control inputs, including two address inputs (A0, A1),
an active low enable input (E), and an active high clear input
(CL). Each latch has a data input (D) and four outputs (Q0–
Q3). The CD4724B is an 8-bit addressable latch with three
address inputs (A0–A2), an active low enable input (E), ac-
tive high clear input (CL), a data input (D) and eight outputs
(Q0–Q7).
able latch mode (E
CL
bit of the address could impose a transient wrong address.
Therefore, this should only be done while in the memory
e
e
low).
mode (E
high, CL
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V (typ.)
Y
Y
High noise immunity
DD
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is low.
Data entry is inhibited when enable (E) is high.
Low power TTL
compatibility
fan out of 2 driving 74L
or 1 driving 74LS
Y
Y
Y
Y
Y
Serial to parallel capability
Storage register capability
Random (addressable) data entry
When clear (CL) and enable (E) are high, all outputs are low.
When clear (CL) is high and enable (E) is low, the channel
demultiplexing occurs. The bit that is addressed has an ac-
tive output which follows the data input while all unad-
dressed bits are held low. When operating in the address-
Active high demultiplexing capability
Common active high clear
Connection Diagrams
CD4723B
Dual-In-Line Package
CD4724B
Dual-In-Line Package
Order Number CD4723B or
CD4724B
TL/F/6003–1
TL/F/6003–2
Top View
Top View
Truth Table
Mode Selection
Addressed
Latch
Unaddressed
E
CL
Mode
Latch
L
H
L
L
L
Follows Data
Hold Previous Data
Follows Data
Reset to ‘0’’
Holds Previous Data
Holds Previous Data
Reset to ‘‘0’’
Addressable Latch
Memory
H
H
Demultiplexer
Clear
H
Reset to ‘‘0’’
C
1995 National Semiconductor Corporation
TL/F/6003
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (V
)
DD
3.0V to 15 V
DC
Input Voltage (V
)
IN
0V to V V
DD DC
b
a
0.5V to 18 V
DC Supply Voltage (V
)
DD
DC
Operating Temperature Range (T )
A
b
a
0.5 V
Input Voltage (V
IN
)
0.5V to V
DD
DC
b
b
a
55 C to 125 C
CD4723BM/CD4724BM
CD4723BC/CD4724BC
§
40 C to 85 C
§
§
b
a
65 C to 150 C
Storage Temperature (T )
S
§
§
a
§
Power Dissipation (P )
D
Dual-In-Line
Small Outline
700 mW
500 mW
Lead Temperature (T )
L
(Soldering, 10 seconds)
260 C
§
DC Electrical Characteristics CD4723BM/CD4724BM (Note 2)
b
a
a
55 C
§
25 C
§
125 C
§
Symbol
Parameter
Conditions
Units
Min
Max
Min
Typ
Max
Min
Max
e
e
e
I
Quiescent Device
Current
V
DD
V
DD
V
DD
5V
5.0
10
20
0.02
0.02
0.02
5.0
10
20
150
300
600
mA
mA
mA
DD
10V
15V
s
1 mA
V
OL
Low Level
I
l
O
l
e
Output Voltage
V
5V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD
DD
DD
e
e
V
V
10V
15V
s
1 mA
V
OH
High Level
I
l
O
l
e
Output Voltage
V
5V
4.95
9.95
4.95
9.95
5.0
10
15
4.95
9.95
V
V
V
DD
DD
DD
e
e
V
V
10V
15V
14.95
14.95
14.95
e
e
e
e
0.5V or 4.5V
V
V
Low Level
V
V
V
5V, V
O
1.5
3.0
4.0
2.25
4.5
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
IL
DD
DD
DD
e
Input Voltage
10V, V
15V, V
1V or 9V
O
e
1.5V or 13.5V
6.75
O
e
e
e
e
0.5V or 4.5V
High Level
V
DD
V
DD
V
DD
5V, V
O
3.5
7.0
3.5
7.0
2.75
5.5
3.5
7.0
V
V
V
IH
e
e
Input Voltage
10V, V
15V, V
1V or 9V
O
O
1.5V or 13.5V
11.0
11.0
8.25
11.0
e
e
e
e
0.4V
I
I
I
Low Level Output
Current
V
V
V
5V, V
O
0.64
1.6
0.51
1.3
0.88
2.25
8.8
0.36
0.9
mA
mA
mA
OL
DD
DD
DD
e
e
10V, V
15V, V
0.5V
1.5V
O
O
(Note 3)
4.2
3.4
2.4
e
e
e
e
5V, V
O
b
b
b
b
b
0.36
High Level Output
Current
V
DD
V
DD
V
DD
4.6V
0.64
0.51
0.88
2.25
mA
mA
mA
OH
IN
e
e
b
b
b
b
b
b
10V, V
15V, V
9.5V
1.6
4.2
1.3
3.4
0.9
2.4
O
O
b
(Note 3)
13.5V
8.8
b
5
e
e
e
e
b
b
b
b
Input Current
V
V
15V, V
15V, V
0V
0.1
10
0.1
1.0
mA
mA
DD
IN
15V
0.1
10b
5
0.1
1.0
DD
IN
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation.
e
Note 2: V
0V unless otherwise specified.
SS
Note 3: I and I are tested one output at a time.
OL OH
2
DC Electrical Characteristics CD4723BC/CD4724BC (Note 2)
b
a
a
40 C
§
25 C
§
85 C
§
Symbol
Parameter
Conditions
Units
Min
Max
Min
Typ
Max
Min
Max
e
e
e
I
Quiescent Device
Current
V
DD
V
DD
V
DD
5V
20
40
80
0.02
0.02
0.02
20
40
80
150
300
600
mA
mA
mA
DD
10V
15V
s
1 mA
V
OL
Low Level
I
l
O
l
e
Output Voltage
V
5V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD
DD
DD
e
e
V
V
10V
15V
s
1 mA
V
OH
High Level
I
l
O
l
e
Output Voltage
V
5V
4.95
9.95
4.95
9.95
5.0
10
15
4.95
9.95
V
V
V
DD
DD
DD
e
e
V
V
10V
15V
14.95
14.95
14.95
e
e
e
e
0.5V or 4.5V
V
V
Low Level
V
V
V
5V, V
O
1.5
3.0
4.0
2.25
4.5
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
IL
DD
DD
DD
e
Input Voltage
10V, V
15V, V
1V or 9V
O
e
1.5V or 13.5V
6.75
O
e
e
e
e
0.5V or 4.5V
High Level
V
DD
V
DD
V
DD
5V, V
O
3.5
7.0
3.5
7.0
2.75
5.5
3.5
7.0
V
V
V
IH
e
1V or 9V
Input Voltage
10V, V
15V, V
O
O
e
1.5V or 13.5V 11.0
11.0
8.25
11.0
e
e
e
e
0.4V
I
I
I
Low Level Output
Current
V
V
V
5V, V
O
0.52
1.3
0.44
1.1
0.88
2.25
8.8
0.36
0.9
mA
mA
mA
OL
DD
DD
DD
e
e
10V, V
15V, V
0.5V
1.5V
O
O
(Note 3)
3.6
3.0
2.4
e
e
e
e
5V, V
O
b
b
b
b
b
0.36
High Level Output
Current
V
DD
V
DD
V
DD
4.6V
0.52
0.44
0.88
2.25
mA
mA
mA
OH
IN
e
e
b
b
b
b
b
b
10V, V
15V, V
9.5V
1.3
3.6
1.1
3.0
0.9
2.4
O
O
b
(Note 3)
13.5V
8.8
b
5
e
e
e
e
b
b
b
b
Input Current
V
V
15V, V
15V, V
0V
0.30
10
0.30
1.0
mA
mA
DD
IN
15V
0.30
10b
5
0.30
1.0
DD
IN
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation.
e
Note 2: V
0V unless otherwise specified.
SS
Note 3: I and I are tested one output at a time.
OL OH
3
AC Electrical Characteristics*
e
e
e
e
e
T
A
25 C, C
§
50 pF, R
200k, Input t
t
f
20 ns, unless otherwise noted
L
L
r
Symbol
Parameter
Conditions Min
Typ
Max
Units
e
e
e
t
Propagation Delay
Data to Output
V
DD
V
DD
V
DD
5V
200
75
400
150
100
ns
ns
ns
PHL, tPLH
10V
15V
50
e
e
e
t
t
t
t
, t
PLH PHL
Propagation Delay
Enable to Output
V
V
V
5V
200
80
400
160
120
ns
ns
ns
DD
DD
DD
10V
15V
60
e
e
e
Propagation Delay
Clear to Output
V
DD
V
DD
V
DD
5V
175
80
350
160
130
ns
ns
ns
PHL
10V
15V
65
e
e
e
, t
PLH PHL
Propagation Delay
Address to Output
V
DD
V
DD
V
DD
5V
225
100
75
450
200
150
ns
ns
ns
10V
15V
e
e
e
, t
THL TLH
Transition Time
(Any Output)
V
DD
V
DD
V
DD
5V
100
50
200
100
80
ns
ns
ns
10V
15V
40
e
e
e
T , T
WH WL
Minimum Data
Pulse Width
V
DD
V
DD
V
DD
5V
100
50
200
100
80
ns
ns
ns
10V
15V
40
e
e
e
t
t
t
t
t
t
, t
WH WL
Minimum Address
Pulse Width
V
V
V
5V
200
100
65
400
200
125
ns
ns
ns
DD
DD
DD
10V
15V
e
e
e
Minimum Clear
Pulse Width
V
DD
V
DD
V
DD
5V
75
40
25
150
75
ns
ns
ns
WH
SU
H
10V
15V
50
e
e
e
Minimum Setup Time
Data to E
V
DD
V
DD
V
DD
5V
40
20
15
80
40
30
ns
ns
ns
10V
15V
e
e
e
Minimum Hold Time
Data to E
V
DD
V
DD
V
DD
5V
60
30
25
120
60
ns
ns
ns
10V
15V
50
e
e
e
b
15
Minimum Setup Time
Address to E
V
DD
V
DD
V
DD
5V
50
30
20
ns
ns
ns
SU
H
10V
15V
0
0
e
e
e
b
b
b
Minimum Hold Time
Address to E
V
DD
V
DD
V
DD
5V
50
20
15
15
10
5
ns
ns
ns
10V
15V
C
C
Power Dissipation
Capacitance
Per Package
(Note 4)
PD
100
5.0
pF
pF
Input Capacitance
Any Input
7.5
IN
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation.
e
Note 2: V
0V unless otherwise specified.
SS
Note 3: I and I are tested one output at a time.
OL OH
2
e
see Application Note AN-90, ‘‘54C/74C Family Characteristics’’.
a
a
e
; where C
L
e
load capacitance; f frequency of operation; for further details,
Note 4: Dynamic power dissipation (P ) is given by: P
D
(C
C ) V
L CC
f
P
D
PD
Q
4
Logic Diagrams
CD4723B
TL/F/6003–3
5
Logic Diagrams (Continued)
CD4724B
TL/F/6003–4
6
Switching Time Waveforms
7
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4723BMJ, CD4723BCJ, CD4724BMJ or CD4724BCJ
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number CD4723BMN, CD4723BCN, CD4724BMN or CD4724BCN
NS Package Number N16E
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to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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