CGS702V
更新时间：2024-09-18 02:06:23
品牌：NSC
描述：Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI
概述
规格参数
数据手册CGS702V 概述
Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI 商业低偏移PLL 1至9的CMOS时钟驱动器与改善EMI 时钟驱动器
CGS702V 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 包装说明： | QCCJ, LDCC28,.5SQ | Reach Compliance Code： | unknown |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.92 |
| Is Samacsys： | N | 系列： | 702 |
| 输入调节： | STANDARD | JESD-30 代码： | S-PQCC-J28 |
| JESD-609代码： | e0 | 长度： | 11.43 mm |
| 逻辑集成电路类型： | PLL BASED CLOCK DRIVER | 功能数量： | 1 |
| 反相输出次数： | 端子数量： | 28 | |
| 实输出次数： | 9 | 最高工作温度： | 70 °C |
| 最低工作温度： | 输出特性： | 3-STATE | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | QCCJ |
| 封装等效代码： | LDCC28,.5SQ | 封装形状： | SQUARE |
| 封装形式： | CHIP CARRIER | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 5 V | 认证状态： | Not Qualified |
| Same Edge Skew-Max（tskwd）： | 1.5 ns | 座面最大高度： | 4.57 mm |
| 子类别： | Clock Drivers | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | COMMERCIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | J BEND | 端子节距： | 1.27 mm |
| 端子位置： | QUAD | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 11.43 mm | 最小 fmax： | 15 MHz |
| Base Number Matches： | 1 |
CGS702V 数据手册
通过下载CGS702V数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载September 1995
CGS702V
Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
with Improved EMI
Y
Guaranteed and tested: 500 ps pin-to-pin skew (T
) on 1x outputs
OSLH
OSHL
General Description
and T
The CGS702 is an off-the-shelf clock driver specifically de-
signed for today’s high speed processors. It provides low
skew outputs which are produced at different frequencies
from three fixed input references. The CGS702 is a reduced
EMI version of the CGS700. The XTALIN input pin is de-
signed to be driven from three distinct crystal oscillators run-
ning at 25 MHz, 33 MHz or 40 MHz.
Y
Y
Y
Y
PentiumTM and PowerPCTM compatible
Output buffer of nine drivers for large fanout
25 MHz–160 MHz output frequency range
Outputs operating at 4x, 2x, 1x of the reference
frequency for multi-frequency bus applications
Selectable output frequency
Y
Y
Y
Y
Y
Y
Internal loop filter to reduce noise and jitter
The PLL, using a charge pump and an internal loop filter,
multiplies this input frequency to create a maximum output
frequency of four times the input.
Separate Analog and digital V
and Ground pins
CC
Low frequency test mode by disabling the PLL
Implemented on National’s Core CMOS process
Symmetric output current drive:
The device includes a TRI-STATE control pin to disable
É
the outputs while the PLL is still in lock. This function allows
testing the board without having to wait to acquire the lock
a
b
30 mA/ 30 mA I /I
OL OH
Y
Y
once the testing is complete.
(Continued)
28-pin PCC for optimum skew performance
Guaranteed 2 kV ESD protection
Features
Y
Reduced EMI compared to CGS700 (refer to EMI
characteristics)
Pin Description
PLCC Package
Connection Diagram
Pin
1
Name
Description
V
Digital V
CC
CC
2
SKWSEL
CLK4
Skew Test Selector Pin
4x Clock Output
3
Pin Assignment for PLCC
4
V
Digital V
CC
CC
5
XTALIN
GND
Crystal Oscillator Input
Digital Ground
6
7
CLK1
0
1
2
1x Clock Output
Ð
Ð
Ð
8
V
Digital V
CC
CC
9
CLK1
GND
CLK1
1x Clock Output
Digital Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1x Clock Output
Output TRI-STATE Control
Skew Testing Pin
1x Clock Output
Digital Ground
TRI-STATE
SKWTST
CLK1
GND
CLK1
3
Ð
4
1x Clock Output
Ð
V
Digital V
CC
CC
EXTCLK
GNDA
External Test Clock
Analog Ground
V
Analog V
CC
CCA
TL/F/12386–1
EXTSEL
GND
External Clock MUX Selector
Digital Ground
CLK1
5
1x Clock Output
Ð
V
Digital V
CC
CC
CLK1
6
1x Clock Output
Ð
CLK1SEL
GND
CLK1 Multiplier Selector
Digital Ground
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
PentiumTM is a trademark of Intel Corporation.
PowerPCTM is a trademark of International Business Machines Corporation.
CLK2
2x Clock Output
C
1995 National Semiconductor Corporation
TL/F/12386
RRD-B30M105/Printed in U. S. A.
General Description (Continued)
Also included, are two EXTSEL and EXTCLK pins to allow
testing the chip via an external source. The EXTSEL pin,
once set to high, causes the External-Clock Mux to
Ð
change its input from the output of the VCO and Counter to
Once CLK1SEL pin is set to a low logic level, the CLK1
outputs will be at twice the input frequency, the same as the
CLK2 output, with CLK4 output still being at four times the
input frequency.
the external clock signal provided via EXTCLK input pin.
In addition two other pins are added for increasing the test
capability. SKWSEL and SKWTST pins allow testing of the
counter’s output and skew of the output drivers by bypass-
ing the VCO. In this test mode CLK4 frequency is the same
as SKWTST input frequency, while CLK2 is (/2 and CLK1
frequencies are (/4 respectively (refer to the truth table). In
addition CLK1SEL functionality is also true under this test
condition.
CLK1SEL pin changes the output frequency of the CLK1
Ð
0,6 outputs. During normal operation, when CLK1SEL pin is
high, these outputs are at the same frequency as the input
crystal oscillator, while CLK2 and CLK4 outputs are at twice
and four times the input frequency respectively.
Block Diagram
TL/F/12386–2
2
Truth Table
Input
Output
CLK2
CLK1 EXT EXT SKW SKW
TRI-
CLK4
CLK1
SEL
SEL CLK
SEL
TST
STATE
H*
L*
X
L
L
H
L
L
X
X
X
L
L
X
X
H
H
H
H
H
L
4x f
IN
2x f
IN
f
IN
4x f
IN
2x f
IN
2x f
IN
É
X
X
H
H
X
X
É
É
É
H
É
É
X
1x f
1x f
(/2x f
(/2x f
(/4x f
TST
TST
TST
TST
TST
TST
L
X
(/2x f
X
X
Z
Z
Z
*Steady state phase, frequency lock.
Typical Application
TL/F/12386–3
3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note 2: Power dissipation is calculated using 49 /W as the thermal coeffi-
§
cient for the PCC package at 225 LFM airflow. The input frequency
is assumed at 33 MHz with CLK4 at 132 MHz and CLK2 and
CLK1’s being at 66 MHz. In addition the ambient temperature is
b
assumed 70 with power supply at 5.0V.
§
Supply Voltage (V
)
CC
0.5V to 7.0V
DC Input Voltage Diode Current (I
)
IK
Recommended Operating
Conditions
e b
b
a
V
V
0.5V
a
20 mA
20 mA
e
V
CC
0.5V
b
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
0.5V to V
CC
Supply Voltage (V
)
CC
4.5V to 5.5V
DC Output Diode Current (I
)
O
Input Voltage (V )
I
0V to V
0V to V
CC
e b
b
a
V
V
0.5V
a
20 mA
20 mA
Output Voltage (V
)
O
CC
e
V
CC
0.5V
Input Crystal Frequency
25 MHz–40 MHz
a
DC Output Voltage (V
DC Output Source
)
O
0.5V
60 mA
60 mA
CC
a
0 C to 70 C
Operating Temperature (T )
A
§
§
1 MHz–10 MHz
External Clock Frequency (EXTCLK Pin)
XTALIN Duty Cycle Range
g
g
or Sink Current (I
)
O
25/75 (75/25)%
DC V
or Ground Current
CC
per Output Pin (I or I
CO
)
Input Rise and Fall Times (0.8V to 2.0V)
Crystal Input
All Other Inputs
GND
)
5 ns max.
10 ns max.
b
a
65 C to 150 C
Storage Temperature (T
§
§
STG
Junction Temperature
§
Power Dissipation (Static and Dynamic) (Note 2) 1400 mW
150 C
Typical i
LFM
0
C/W
54
§
JA
Note 1: The Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. The device should not
be operated at these limits. The parametric values defined in the
DC and AC Electrical Characteristics tables are not guaranteed at
the Absolute Maximum Ratings. The Recommended Operating
Conditions will define the conditions for actual device operation.
225
500
900
45
38
34
DC Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
e
e
25 C
5V, T
§
CC
A
e
V
CC
4.5V to 5.5V
e
T
0 C to 70 C
§ §
Symbol
Parameter
Conditions
V
CC
Units
Min
Typ
Max
V
V
V
Minimum Input
4.5
5.5
2.0
2.0
IH
V
V
High Level Voltage
Maximum Input
4.5
5.5
0.8
0.8
IL
Low LeveI Voltage
e b
Minimum Output
I
I
I
I
50 mA
4.5
5.5
4.4
5.4
4.4
5.4
OH
OH
OH
OL
OL
High Level Voltage
V
V
e b
b
30 mA
4.5
5.5
V
V
0.6
0.6
CC
b
CC
e
e
V
OL
Maximum Output
Low Level Voltage
50 mA
4.5
5.5
0.1
0.1
30 mA
4.5
5.5
0.6
0.6
e
b
1.0V
I
I
I
High Level Output Current
Low Level Output Current
Leakage Current
V
V
V
V
4.5
4.5
50
50
110
110
170
170
mA
mA
OH
OH
CC
e
1.0V
OL
IN
OL
IN
e
0.4V or 4.6V
GND
4.5
5.5
b
50
50.0
mA
mA
pF
e
I
Output Leakage Current
Input Capacitance
V
V
OZL/H
IN
b
a
5.0
5.5
5.0
e
V
or GND
OUT
CC
C
4.5
5.0
IN
10.0
a
Quiescent Analog Digital Current (No Load)
e
I
I
V
V
V
V
or GND
5.5
5.5
3
5.0
2.5
CC
IN
CC
mA
CCT
e
b
2.1 or GND
I
per TTL Input
CC
IN
CC
4
CGS702 AC Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
e
e
25 C
5V, T
§
CC
A
e
25 MHz to 40 MHz
V
4.5V to 5.5V
CC
e
f
IN
e
T
0 C to 70 C
§
§
Symbol
Parameter
Units
Notes
e
C
Circuit 1 and 2
Circuit 1 and 2
L
L
e
R
Min
Typ
Max
t
t
t
Output Rise
Output Fall
CLK4
0.8V to 2.6V
RISE
b
b
ns
ns
(Note 1)
CLK2
CLK1
1.0V to V
1.0V to V
1.0V
1.0V
2.0
2.0
CC
CC
CLK4
CLK2
CLK1
2.6V to 0.8V
FALL
SKEW
b
b
(Note 1)
(Note 2)
V
V
1.0V to 1.0V
1.0V to 1.0V
CC
CC
a
a
a
a
a
a
Maximum
to
to
to
Edges
Edges
Edges
CLK1 CLK1
Ð
CLK1 CLK4
500
1000
1500
Edge-to-Edge
Output Skew
ps
ms
%
Ð
CLK2 CLK4
Ð
t
t
Time to Lock the Output to the XTALIN Input
100
LOCK
Output Duty Cycle
CLK1 Outputs
CLK2 Output
CLK4 Output
49
49
35
51
51
65
CYCLE
(Note 3)
J
J
Output Jitter (Long Term)
300
ps
ps
(Notes 4, 5)
LT
b
a
75
Output Jitter
CLK1
CLK2
CLK4
75
(Notes 4, 5, 6)
(Notes 4, 5, 7)
(Notes 4, 5, 7)
CC
(Cycle to Cycle)
g
250
250
ps
g
ps
F
F
Minimum XTALIN Frequency
Maximum XTALIN Frequency
15
43
MHz
MHz
MIN
MAX
Note 1: t
and t
parameters are measured at the pin of the device
FALL
RISE
Note 2: Skew is measured at 50% of V
for CLK1 and CLK2. While it is measured at 1.4V for CLK4.
CC
Note 3: Output duty cycle is measured at V /2 for CLK1 and CLK2. While it is measured at 1.4V for CLK4.
DD
Note 4: Jitter parameter is characterized and is guaranteed by design only. It measures the uncertainty of either the positive or the negative edge over 1000 cycles.
It is also measured at output levels of V /2 . Refer to Figure 2 for further explanation.
CC
Note 5: The GNDA pins of the 702 must be as free of noise as possible for minimum jitter. Separate analog ground plane is recommended for the PCB.
Also the V
CCA
pin requires extra filtering to further reduce noise. Ferrite beads for filtering and bypass capacitors are suggested for V
pin.
CCA
Note 6: Cycle to Cycle Jitter is measured at V
CC/2
.
@
Note 7: Cycle to Cycle Jitter for CLK2 and CLK4 is only for 25 C, 5V measured
§
V
CC/2
.
TL/F/12386–5
TL/F/12386–4
Circuit 2. Test Circuit for CLK4
Circuit 1. Test Circuit for CLK1 and CLK2
5
CGS702 AC Electrical Characteristics (Continued)
TL/F/12386–6
FIGURE 1. Waveforms
TL/F/12386–7
e
b
a
Period(n 1) for either the rising or falling edge, where n is 1 to 1000 cycles.
Jitter
Period(1)
l
l
FIGURE 2. Jitter
Application References and Bibiliography
Information relating to EMI as well as general application hints are in the following application notes:
AN-988 (EMI App Note)
AN-640
AN-991
6
EMI Characteristics and Measurements for CGS702
MEASURING THE SPECTRAL CONTENT OF A LOGIC IC
The FCC certification test method is an open field measure-
ment procedure. Therefore, the spectral content of the de-
vice-under-test (in this case, an IC) cannot be detected be-
low the ambient level of radiation. The test-site is perma-
nent and the average ambient noise level remains relatively
constant.
In order to analyze the frequency, or spectral content of
logic ICs, two measurement techniques have been devel-
oped. One method, The Radiated Measurement Method, is
based on the system-level FCC certification test methodolo-
gy, FCC Open Site Test (OST) 55. The radiated method
utilizes a multilayer PCB with the IC-under-test is mounted
on a grounded, adjustable table placed 3 meters from an
antenna mast (see Figure 3 ). The IC’s input is stimulated by
a known periodic waveform and its output drives a typical
PCB microstrip. The 75X microstrip is properly terminated
to prevent reflections from affecting the IC’s spectral con-
tent results.
The CGS700 and CGS702 were tested for EMI using the
above method. A comparison of the EMI results in the form
of spectral content is shown in Figures 4 and 5.
For more details on EMI, see Application Note AN-831.
Screen Room with 120 dB Shielding
TL/F/12386–9
FIGURE 3. Radiated EMI Measurement Method
7
EMI Characteristics and Measurements (Continued)
TL/F/12386–8
e
e
e
e
25 C ANTENNA HORIZONTAL
§
XTALIN
40 MHz
V
5V
T
CC
FIGURE 4. CGS700
TL/F/12386–12
e
e
e
e
25 C ANTENNA HORIZONTAL
§
XTALIN
40 MHz
V
5V
T
CC
FIGURE 5. CGS702
8
Ordering Information
(Contact NSC Marketing for Specific Date of Availability)
TL/F/12386–11
9
Physical Dimensions inches (millimeters)
28-Lead Molded Plated Leaded Chip Carrier
Order Number CGS702V
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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