CLC411A8B [NSC]
High-Speed Video Op Amp with Disable; 高速视频运算放大器具有禁用
| 型号： | CLC411A8B |
| 厂家： | 
National Semiconductor |
| 描述： | High-Speed Video Op Amp with Disable |
| 文件： | 总8页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
N
CLC411
High-Speed Video Op Amp with Disable
General Description
Features
The CLC411 combines a state-of-the-art complementary bipolar
process with National’s patented current-feedback architecture to
provide a very high-speed op amp operating from ±15V supplies.
Drawing only 11mA quiescent current, the CLC411 provides a
200MHz small signal bandwidth and a 2300V/µs slew rate while
deliveringacontinuous70mAcurrentoutputwith±4.5Voutputswing.
TheCLC411’shigh-speedperformanceincludesa15nssettlingtime
to 0.1% (2V step) and a 2.3ns rise and fall time (6V step).
■ 200MHz small signal bandwidth (1Vpp)
■ ±0.05dB gain flatness to 30MHz
■ 0.02%, 0.03° differential gain, phase
■ 2300V/µs slew rate
■ 10ns disable to high-impedance output
■ 70mA continuous output current
■ ±4.5V output swing into 100Ω load
■ ±4.0V input voltage range
The CLC411 is designed to meet the requirements of professional
broadcastvideosystemsincludingcompositevideoandhighdefinition
television.TheCLC411exceedstheHDTVstandardforgainflatness
to 30MHz with it's ±0.05dB flat frequency response and exceeds
composite video standards with its very low differential gain and
phase errors of 0.02%, 0.03°. The CLC411 is the op amp of choice
for all video systems requiring upward compatibility from NTSC and
PAL to HDTV.
Applications
■ HDTVamplifier
■ Video line driver
■ High-speed analog bus driver
■ Video signal multiplexer
■ DAC output buffer
Gain Flatness (Av=+2)
TheCLC411featuresaveryfastdisable/enable(10ns/55ns)allowing
themultiplexingofhigh-speedsignalsontoananalogbusthroughthe
common output connections of multiple CLC411’s. Using the same
signal source to drive disable/enable pins is easy since “break-
before-make”isguaranteed.
The CLC411 is available in several versions:
CLC411AJP
CLC411AJE
CLC411A8B
-40°Cto+85°C
-40°Cto+85°C
-55°Cto+125°C
8-pin plastic DIP
8-pin plastic SOIC
8-pinhermeticCERDIP,
MIL-STD-883
0
Frequency (5MHz/div)
50
CLC411AMC
-55°Cto+125°C
dice, MIL-STD-883, Level B
DESCSMDnumber:5962-94566
+Vcc
6.8µF
DIS
Pinout
0.1µF
DIP & SOIC
Recommended
Inverting Gain
Configuration
7
+Vr
1
0.01µF
8
+
3
2
+Vr
1
2
3
4
8
7
6
5
DIS
6
25Ω
Vout
CLC411
-
Vinv
Vnon-inv
-Vcc
+Vcc
Vout
-Vr
_
0.01µF
5
4
-Vr
+
Vin
Rg
Rf
0.1µF
6.8µF
Select RT to yield
Rin = RT||Rg
RT
-Vcc
1999NationalSemiconductorCorporation
PrintedintheU.S.A.
http://www.national.com
CLC411 Electrical Characteristics
(
AV
=
+
2;
VCC
=
±
1
5
V
;
RL
=
1
0
0
Ω
;
Rf
=
3
0
1Ω
,
u
n
l
e
s
s
n
o
t
e
d
)
PARAMETERS
CONDITIONS
TYP
MIN/MAX RATINGS
UNITS
SYMBOL
AmbientTemperature
CLC411AJ
+25°C
-40°C
+25°C
+85°C
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vout < 1Vpp
Vout < 6Vpp
200
75
150
50
150
50
110
40
MHz
MHz
SSBW
LSBW
gain flatness
peaking
rolloff
peaking
rolloff
linear phase deviation
differential gain
differential phase
Vout < 1Vpp
DC to 30MHz
DC to 30MHz
DC to 200MHz
DC to 60MHz
DC to 60MHz
4.43MHz, RL=150W
4.43MHz, RL=150W
0.05
0.05
0.1
0.2
0.3
0.02
0.03
0.2
0.2
0.6
0.7
1.0
0.2
0.2
0.5
0.4
1.0
0.3
0.4
0.6
0.7
1.0
dB
dB
dB
dB
°
%
°
GFPL
GFRL
GFPH
GFRH
LPD
DG
DP
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.1%
overshoot
6V step
2V step
2V step
6V step
2.3
15
5
ns
ns
%
V/µs
TR
TS
OS
SR
23
15
18
10
23
15
slew rate
2300
DISTORTION AND NOISE RESPONSE (note 1)
2ND harmonic distortion
3RD harmonic distortion
equivalent noise input
voltage
2Vpp, 20MHz
2Vpp, 20MHz
-48
-52
-35
-42
-35
-42
-35
-35
dBc
dBc
HD2
HD3
>1MHz
>1MHz
>1MHz
>1MHz
2.5
12.9
6.3
-157
45
nV/√Hz VN
pA/√Hz ICI
pA/√Hz ICN
dBm1Hz SNF
inverting current
non-inverting current
noise floor
integrated noise
1MHz to 200MHz
µV
INV
STATIC DC PERFORMANCE
*input offset voltage
±2
+30
12
±200
±12
±50
56
52
11
±13
±50
65
±400
±40
±200
48
44
14
4.5
±9.0
±14
±50
±20
±250
±30
±150
48
44
12
4.5
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
mA
VIO
DVIO
IBN
DIBN
IBI
____
average temperature coefficient
*input bias current non-inverting
average temperature coefficient
*input bias current inverting
average temperature coefficient
power supply rejection ratio
common mode rejection ratio
*supply current
supply current
30
____
±30
____
DIBI
50
46
12
3.5
PSRR
CMRR
ICC
no load
disabled
2.5
ICCD
DISABLE/ENABLE PERFORMANCE (note 2)
disable time
enable time
DIS voltage
to >50dB attenuation @10MHz
10
55
30
30
60
ns
ns
TOFF
TON
pin 8
to disable
to enable
off isolation
4.5
5.5
59
<3.0
>7.0
55
<3.0
>6.5
55
<3.0
>6.5
55
V
V
dB
VDIS
VEN
OSD
at 10MHz
MISCELLANEOUS PERFORMANCE
non-inverting input resistance
1000
2.0
±6.0
±4.5
±4.0
70
250
3.0
750
3.0
±4.5
±4.0
±3.5
50
1000
3.0
kΩ
pF
V
V
V
RIN
CIN
VO
VOL
CMIR
IO
non-inverting input capacitance
output voltage range
output voltage range
common mode input range
output current
no load
RL=100Ω
30
40
mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels
are determined from tested parameters.
Absolute Maximum Ratings
Miscellaneous Ratings
Vcc
Iout
±18V
125mA
Recommended gain range ±1 to ±10V/V
Notes: * AJ :100% tested at +25°C.
common-mode input voltage
differential input voltage
±Vcc
note 1
note 2
:Specifications guaranteed using 0.01mF bypass capacitors
on pins 1 & 5.
:Break before make is guaranteed.
±15V
maximum junction temperature
operating temperature range: AJ
storage temperature range
lead temperature (soldering 10 sec)
ESD (human body model)
+150°C
-40°C to +85°C
-65°C to +150°C
+300°C
Package Thermal Resistance
1000V
Package
θJC
θJA
AJP
AJE
A8B
65°C/W
55°C/W
25°C/W
120°C/W
135°C/W
115°C/W
Reliability Information
Transistor count
70
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2
o
Non-Inverting Frequency Response
Inverting Frequency Response
Av = 2
Rf = 301Ω
Av = -2
Rf = 301Ω
Av = 1
Rf = 402Ω
Av = -1
Rf = 301Ω
Vout = 1Vpp
Vout = 1Vpp
0
-180
-270
-360
-450
-540
-630
-90
-180
-270
-360
-450
Av = 10
Rf = 200Ω
Av = -10
Rf = 200Ω
Av = 5
Rf = 200Ω
Av = -5
Rf = 249Ω
1
100
1
100
Frequency (MHz)
Frequency (MHz)
3
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+Vcc
+Vcc
6.8µF
0.1µF
6.8µF
0.1µF
Figure 3: Recommended
Inverting Gain Circuit
DIS
DIS
7
+Vr
7
+Vr
0.01µF
0.01µF
8
8
Vin
+
+
1
1
3
2
3
2
6
6
Vout
25Ω
Vout
CLC411
CLC411
Rin
_
0.01µF
_
0.01µF
5
5
4
4
-Vr
-Vr
Vin
Rg
Rf
Rf
Rg
0.1µF
6.8µF
0.1µF
6.8µF
Select RT to yield
Rin = RT||Rg
RT
Figure 1: Recommended
Non-inverting Gain Circuit
-Vcc
-Vcc
low-inductancegroundplane. BypassingtheVr pinswill
reduce high frequency noise (>10MHz) in the amplifier.
If this noise is not a concern these capacitors may be
eliminated.
Description
TheCLC411isahigh-speedcurrent-feedbackoperational
amplifier which operates from ±15V power supplies.
The external supplies (±VCC) are regulated to lower
voltages internally. The amplifier itself sees
approximately ±6.5V rails. Thus the device yields
performance comparable to Comlinear’s ±5V devices,
butwithhighersupplyvoltages. Thereisnodegradation
in rated specifications when the CLC411 is operated
from ±12V. A slight reduction in bandwidth will be
observed with ±10V supplies. Operation at less than
±10V is not recommended.
Differential Gain and Phase
The differential gain and phase errors of the CLC411
drivingonedoubly-terminatedvideoload(RL=150Ω)are
specified and guaranteed in the “Electrical
Characteristics” table. The “Typical Performance” plot,
“Differential Gain and Phase (4.43MHz)” shows the
differential gain and phase performance of the CLC411
when driving from one to four video loads. Application
noteOA-08, “DifferentialGainandPhaseforComposite
Video Systems,” describes in detail the techniques
used to measure differential gain and phase.
A block diagram of the amplifier and regulator topology
is shown in Figure 2, “CLC411 Equivalent Circuit.” The
regulatorsderivetheirreferencevoltagefromaninternal
floating zener voltage source. External control of the
zener reference pins can be used to level-shift amplifier
operation which is discussed in detail in the section
entitled “Extending Input/Output Range with Vr.”
FeedbackResistor
The loop gain and frequency response for a current-
feedback operational amplifier is determined largely by
the feedback resistor, Rf. The electrical characteristics
and typical performance plots contained within the
datasheet, unless otherwise stated, specify an Rf of
301Ω, a gain of +2V/V and operation with ±15V power
supplies. The frequency response at different gain
settings and supply voltages can be optimized by
selecting a different value of Rf. Generally, lowering Rf
will peak the frequency response and extend the
bandwidth while increasing its value will roll off the
response. For unity-gain voltage follower circuits, a
+Vcc
+Vr
7
17kΩ
1
+
reg
3
2
+
+
-
6
Vz
-
-Vr
5
_
reg
17kΩ
-Vcc
4
500
Figure 2: CLC411 Equivalent Circuit
400
Inverting
Power Supply Decoupling
300
There are four pins associated with the power supplies.
The VCC pins (4,7) are the external supply voltages. The
Vr pins (5,1) are connected to internal reference nodes.
Figures 1 and 3 , “Recommended Non-inverting Gain
Circuit” and "Recommended Inverting Gain Circuit"
show the recommended supply decoupling scheme
with four ceramic and two electrolytic capacitors. The
ceramiccapacitorsmustbeplacedimmediatelyadjacent
to the device pins and connected directly to a good
Non-Inverting
200
100
0
0
1
2
3
4
5
6
7
8
9
10
Gain (V/V)
Figure 4: Recommended Rf vs. Gain
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4
non-zero Rf must be used with current-feedback
operationalamplifierssuchastheCLC411. Application
note OA-13, “Current-Feedback Loop-Gain Analysis
and Performance Enhancements,” explains the
ramifications of Rf and how to use it to tailor the desired
frequencyresponsewithrespecttogain. Theequations
found in the application note should be considered as a
starting point for the selection of Rf. The equations do
not factor in the effects of parasitic capacitance found
ontheinvertinginput,theoutputnoracrossthefeedback
resistor. Equations in OA-13 require values for Rf
(301Ω), Av(+2)andRi (invertinginputresistance, 50Ω).
CombiningthesevaluesyieldsaZt*(optimumfeedback
transimpedance) of 400Ω. Figure 4 entitled
"Recommended Rf vs. Gain" will enable the selection of
the feedback resistor that provides a maximally flat
frequency response for the CLC411 over its gain range.
The linear portion of the two curves (i.e. AV>4) results
from the limitation on Rg (i.e. Rg ≥50Ω).
Enable/Disable Operation
ThedisablefeatureallowstheoutputsofseveralCLC411
devices to be connected onto a common analog bus
formingahigh-speedanalogmultiplexer.Whendisabled,
the output and inverting inputs of the CLC411 become
high impedances. The disable pin has an internal pull-
up resistor which is pulled-up to an internal voltage, not
totheexternalsupply. TheCLC411isenabledwhenpin
+
8 is left open or pulled-up to ≥ 7V and disabled when
+
grounded or pulled below 3V. CMOS logic devices are
necessary to drive the disable pin. For example, CMOS
+
logicwithVDD ≥ 7Vwillguaranteeproperoperationover
temperature. TTL voltage levels are inadequate for
controlling the disable feature.
For faster enable/disable operation than 15V CMOS
logic devices will allow, the circuit of Figure 5 is
recommended. Afastfour-transistorcomparator,Figure
5A, interfaces between the CLC411 DISABLE pin and
several standard logic families. This circuit has a
differential input between the bases of Q1 and Q2. As
such it may be driven directly from differential ECL
logic, as in shown in Figure 5B. Single-ended logic
familiesmayalsobeusedbyestablishinganappropriate
threshold voltage on the Vth input, the base of Q2.
+15V
0.1µF
Q3
Q4
CLC411 pin 8, DISABLE
Disable
Q1
Q2
Vth
Q1,Q2 MPSH10
Q3,Q4 MPSH81
3.57kΩ
0.1µF
-15V
Buffers
Figure 5A: Disable Interface
A
B
C
0
1
2
3
4
5
6
7
Q1
Q2
DIS (pin 8)
330Ω
330Ω
+
-5.2V
-5.2V
ECL
Gate
A
-
CLC411
Figure 5B: Differential ECL Interface
DIS (pin 8)
931Ω
+
50Ω
Q1
Q2
B
-
0.1µF
10kΩ
-15V
330Ω
ECL
Gate
CLC411
-5.2V
Figure 5C: ECL Interface
Figure 6: General Multiplexing Circuit
Figures 5C and 5D illustrate a single-ended ECL and
TTL interface respectively. The Disable input, the base
of Q1, is driven above and below the threshold, Vth.
50Ω
0.1µF
50Ω
Q2
Q1
332Ω
TTL
Gate
1N914
Fastest switching speeds result when the differential
voltage between the bases of Q1 and Q2 is kept to less
Figure 5D: TTL Interface
5
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than one volt. Single-ended ECL, Figure 5C, maintains
this desired maximum differential input voltage. TTL
and CMOS have higher Vhigh to Vlow excursions. The
circuit of figure 5D will ensure the voltage applied
between the bases of Q1 and Q2 does not cause
excessive switching delays in the CLC411. Under the
aboveproscribedfour-transistorinterface, allvariations
were evaluated with approximately 1ns rise and fall
times which produced switching speeds equivalent to
the rated disable/enable switching times found in the
"CLC411 Electrical Characteristics" table.
implicitly have 0V as their midpoint, i.e. the VO range
is ±6V, centered at 0V.
+
An external voltage source can be applied to Vr to shift
the range of the input/output voltages. For example, if
+
it were desired to move the positive VO range from 6V
+
to a 9V maximum in unipolar operation, Figure 7, “DC
+
Parameters as a Function of Vr”, is used to determine
+
the required supply and Vr voltages. Referring to
+
Figure 7, locate the point on the VOMAX line where the
+
ordinate is 9V. Draw a vertical line from this point
intersecting the other lines in the graph. The circuit
voltages are the ordinates of these intersections. For
this example these points are shown in the graph as
A general multiplexer configuration using several
CLC411s is illustrated in figure 6, where a typical 8-to-
1 digital mux is used to control the switching operation
of the paralleled CLC411s. Since "break-before-make"
is a guaranteed specification of the CLC411 this
configuration works nicely. Notice the buffers used in
driving the disable pins of the CLC411s. These buffers
may be 15V CMOS logic devices mentioned previously
or any variation of the four-transistor comparator
illustrated above.
+
+
solid dots. The required voltage sources are Vr= 12V,
+
+
VCC= 12V, -VCC=-12V. When these supply and
reference voltages are applied, the range for VO is -3V
+
+
to 9V,andCMIRrangesfrom-1Vto 7V.Thedifference
between the minimum and maximum voltages is
constant, i.e. 12V for VO, only the midpoint has been
+
shifted, i.e. from 0V to 3V for VO.
Note that in this example the -Vr pin has been left open
(or bypassed to reduce high-frequency noise). The
Extending Input/Output Range with Vr
+
AscanbeseeninFigure3, themagnitudeoftheinternal
regulated supply voltages is fixed by Vz. In normal
difference between Vr and -Vr is fixed by Vz. A level-
shifting voltage can be applied to only one of the
reference pins, not both. If extended operation were
needed in the negative direction, Figure 4 may be used
by changing the signs, and applying the resultant
negative voltage to the -Vr pin. It is recommended that
+
operation, with ±15V external supplies, Vr is nominally
+
9V when left floating. CMIR (common mode input
range) and VO (output voltage range, no load) are
specified under these conditions. These parameters
+
Vr be used for positive shifts, and -Vr for negative
shifts of input/output voltage range.
Printed Circuit Layout & Evaluation Board
Refer to application note OA-15, “Frequent Faux Pas in
Applying Wideband Current Feedback Amplifiers,” for
boardlayoutguidelinesandconstructiontechniques.Two
veryimportantpointstoconsiderbeforecreatingalayout
which are found in the above application note are worth
reiteration. Firsttheinputandoutputpinsaresensitiveto
parasitic capacitances. These parasitic capacitances
can cause frequency-response peaking or sustained
oscillation. To minimize the adverse effect of parasitic
capacitances, thegroundplaneshouldberemovedfrom
those pins to a distance of at least 0.25" Second, leads
shouldbekeptasshortaspossibleinthefinishedlayout.
Inparticular,thefeedbackresistorshouldhaveitsshortest
leadontheinvertinginputsideoftheCLC411.Theoutput
is less sensitive to parasitic capacitance and therefore
can drive the longer of the two feedback resistor
connections.TheevaluationboardavailablefortheCLC411
(part#730013forthrough-holepackages,730027forSO-
8) may be used as a reference for proper board layout.
Applicationschematicsforthisevaluationboardareinthe
product accessories section of the Comlinear databook.
20
15
10
5
+VCC
max
+Vr
+VOmax
-VOmin
-10
-5
5
10
15
+
_
-5
Vcm
Vcm
ange
r
cc
V
-10
-15
Recommended
+
-VCC
max
ange
r
cc
V
Recommended
-
Figure 7: DC Parameters as a Function of +Vr
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