CLC418 [NSC]
Dual High-Speed, Low-Power Line Driver; 双高速，低功耗线路驱动器
| 型号： | CLC418 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual High-Speed, Low-Power Line Driver |
| 文件： | 总12页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1996
N
Comlinear CLC418
Dual High-Speed, Low-Power Line Driver
General Description
Features
The Comlinear CLC418 dual high-speed current-feedback
operational amplifier is designed to drive low-impedance and
high capacitance loads while maintaining high signal fidelity.
Operating on ±5V power supplies, each of the CLC418’s
amplifiers produces a continuous 96mA output current. Into a
back-terminated 50Ω load, the devices produce -85/-64dBc
■
■
■
■
■
■
■
130MHz bandwidth (A = +2)
v
96mA output current
1.5mA supply current
-85/-75dBc HD2/HD3
15ns settling to 0.2%
-74dBc input-referred crosstalk (5MHz)
Single version available (CLC408)
second/third harmonic distortion (A = +2, V = 2V , f = 1MHz).
v
o
pp
The CLC418’s current-feedback architecture maintains consistent
performance over a wide range of gain and signal levels. DC gain
and bandwidth can be set independently. With proper resistor
selection, either maximally flat gain response or linear phase
response can be selected.
Applications
■
ADSL/HDSL driver
■
Coaxial cable driver
■
UTP differential line driver
■
Transformer/coil driver
■
High capacitive-load driver
Video line driver
Portable/battery-powered line driver
Differential A/D driver
Requiring a mere 15mW quiescent power per amplifier, the
CLC418 offers superior performance-vs-power with a 130MHz
small-signal bandwidth, 350V/ms slew rate and quick 4.6ns
rise/fall times (2Vstep). The combination of low quiescent power,
high output current drive and high performance make the
CLC418 a great choice for many battery-powered personal
communication/computing systems.
■
■
■
Non-Inverting Frequency Response
(Av = +2V/V, RL = 100Ω)
Combining the CLC418’s two amplifiers (shown below) results in
a powerful differential line driver for driving video signals over
unshielded twisted-pair (UTP). The CLC418 can also be used for
driving differential-input step-up transformers for applications
such as Asynchronous Digital Subscriber Lines (ADSL) or High-
Bit-Rate Digital Subscriber Lines (HDSL).
The CLC418’s amplifiers make excellent low-power high-
resolution A-to-D converter drivers with their very fast 15ns set-
tling time (to 0.2%) and ultra-low -85/-75dBc harmonic distortion
1M
10M
100M
(A = +2, V = 2V , f = 1MHz, R = 1kΩ).
v
o
pp
L
Frequency (Hz)
Typical Application Diagram
Pinout
Differential Line Driver
DIP & SOIC
with Load Impedance Conversion
Rg2
Rf2
Vo1
Vinv1
VCC
Vd/2
Vin
Rt1
Vo2
+
1/2
CLC418
Rm/2
Io
-
I:n
-Vd/2
+
Vo
-
1/2
CLC418
Zo
Vnon-inv1
VEE
Vinv2
Vnon-inv2
-
Req
RL
Rf1
+
UTP
Rt2
Rm/2
Rg1
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
(A = +2, R = 1kΩ, V = + 5V, RL = 100Ω, T = 25°C; unless specified)
CLC418 Electrical Characteristics
V
f
cc
PARAMETERS
CONDITIONS
TYP
MIN/MAX RATINGS
UNITS
NOTES
Ambient Temperature
CLC418AJ
+25˚C
+25˚C
0 to 70˚C -40 to 85˚C
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo < 1.0Vpp
Vo < 4.0Vpp
Vo < 1.0Vpp
Vo < 1.0Vpp
DC to 200MHz
<30MHz
130
45
30
80
33
25
80
29
20
75
28
20
MHz
MHz
MHz
B
-
0.1dB bandwidth
gain flatness
peaking
0
0.5
0.45
0.4
–
0.9
0.6
0.5
–
1.0
0.6
0.5
–
dB
dB
deg
%
B
B
rolloff
0.2
0.2
0.1
0.4
linear phase deviation
differential gain
differential phase
<30MHz
NTSC, RL=150Ω
NTSC, RL=150Ω
–
–
–
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.2%
overshoot
2V step
2V step
2V step
2V step
4.6
15
5
7.0
30
12
7.5
38
12
8.0
40
12
ns
ns
%
slew rate
AV = +2
350
260
225
215
V/µs
DISTORTION AND NOISE RESPONSE
2
nd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
-85
-85
-65
-64
-75
-50
-74
–
–
-60
–
–
-45
-68
–
–
-58
–
–
-44
-68
–
–
-58
–
–
-44
-68
dBc
dBc
dBc
dBc
dBc
dBc
dBc
B
B
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
2Vpp, 5MHz
crosstalk (input-referred)
equivalent input noise
voltage (eni)
>1MHz
>1MHz
>1MHz
5
1.4
13
6.3
1.8
16
6.6
1.9
17
6.7
2.3
18
nV/√Hz
pA/√Hz
pA/√Hz
non-inverting current (ibn)
inverting current (ibi)
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
input bias current (inverting)
average drift
power supply rejection ratio
common-mode rejection ratio
supply current
2
25
2
60
2
20
55
52
3.0
8
–
8
–
10
–
50
48
3.4
11
35
11
80
18
90
48
46
3.6
11
40
15
110
20
110
48
mV
µV/˚C
µA
nA/˚C
µA
nA/˚C
dB
dB
A
A
A
B
A
DC
DC
46
3.6
RL= ∞, 2 channels
mA
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
common mode input range
output voltage range
5
1
2.7
3.3
4.0
3
2
2.3
2.9
3.8
2.5
2
1
2
2.0
2.6
3.5
MΩ
pF
V
V
V
±
±
±
±
±
±
±2.2
±2.8
±3.7
±
±
±
RL = 100Ω
RL = ∞
output voltage range
output current
output resistance, closed loop
96
0.03
96
0.15
96
0.2
60
0.3
mA
Ω
C
DC
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
supply voltage
Notes
A) J-level: spec is 100% tested at +25°C, sample tested at +85°C.
L-level: spec is 100% wafer probed at +25°C.
B) J-level: spec is sample tested at +25°C.
C)The output current sourced or sunk by the CLC418 can
exceed the maximum safe output current limit.
±
7V
96mA
VCC
output current (see note C)
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
ESD rating (human body model)
±
+175°C
-65°C to +150°C
+300°C
4000V
http://www.national.com
2
(A = +2, R = 1kΩ, R = 100Ω, VCC = + 5V, T = 25°C; CLC418AJ; unless specified)
Typical Performance Characteristics
v
f
L
Non-Inverting Frequency Response
Inverting Frequency Response
Frequency Response vs. RL
RL=1k
Vo = 1Vpp
Vo = 1Vpp
Vo = 1Vpp
Rf=1.21k
RL=25
Av+2
Av+5
Rf=0.95k
RL=100
Rf=1k
Av-1
Av-5
Gain
Gain
Gain
Av-10
Av+1
Av+10
Av-2
RL=100
Phase
Phase
Phase
0
0
0
Av+10
RL=1k
Av-5
Rf=301
-90
-180
-270
-90
-90
-180
-270
Rf=200
Av+5
RL=25
-180
-270
-360
-450
Rf=402
Av-10
Rf=200
Av+2
Rf=953
Av-2
Rf=681
-360
-450
Av+1
Rf=3k
-360
-450
Av-1
Rf=806
1M
10M
100M
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Small Signal Channel Matching
Frequency Response vs. Vout
Frequency Response vs. Capacitive Load
Vo = 1Vpp
Vo = 1Vpp
CL=0pF
Rs =0
Channel A
CL=100pF
Rs =24.9
Channel B
Channel A
0.10Vpp
CL=1000pF
0
1.0Vpp
2.0Vpp
Rs =5.7
-45
-90
-135
-180
-225
+
-
Rs
CL
4.0Vpp
Channel B
1k
1k
CL=10pF
Rs =100
1k
1M
10M
100M
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Open Loop Transimpedance Gain, Z(s)
PSRR and CMRR
Equivalent Input Noise
1M
100k
10k
1k
180
140
100
60
100
10
1
100
10
1
60
50
40
30
20
10
0
Gain
Phase
ibi
CMRR
eni
PSRR
-
Vo
CLC418
Ii
+
100Ω
ibn
100
20
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Input-Referred Crosstalk
2nd & 3rd Harmonic Distortion
2nd Harmonic Distortion, RL = 25Ω
-40
-50
-60
-70
-80
-90
-20
-30
-40
-50
-60
-70
-80
-90
-45
-50
-55
-60
-65
-70
-75
Vo = 1Vpp
Vo = 2Vpp
10MHz
5MHz
2nd
RL = 100
3rd
RL = 100
2MHz
1MHz
3rd
RL = 1k
2nd
RL = 1k
1M
10M
100M
1M
10M
0
1
2
3
4
5
Frequency (Hz)
Frequency (Hz)
Output Amplitude (Vpp
)
2nd Harmonic Distortion, RL = 100Ω
3rd Harmonic Distortion, RL = 100Ω
3rd Harmonic Distortion, RL = 25Ω
-50
-55
-60
-65
-70
-75
-80
-85
-90
-30
-40
-50
-60
-70
-80
-20
-30
-40
-50
-60
-70
-80
10MHz
10MHz
10MHz
5MHz
2MHz
5MHz
5MHz
2MHz
2MHz
1MHz
1MHz
1MHz
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
Output Amplitude (Vpp
)
Output Amplitude (Vpp)
Output Amplitude (Vpp
)
3
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(A = +2, R = 1kΩ, R = 100Ω, VCC = + 5V, T = 25°C; CLC418AJ; unless specified)
Typical Performance Characteristics
v
f
L
3rd Harmonic Distortion, RL = 1kΩ
2nd Harmonic Distortion, RL = 1kΩ
Closed Loop Output Resistance
-55
-60
-65
-70
-75
-80
-85
-90
-95
-60
-65
-70
-75
-80
-85
-90
-95
100
10
1
10MHz
10MHz
5MHz
5MHz
2MHz
1MHz
2MHz
1MHz
0.1
0
1
2
3
4
5
0
1
2
3
4
5
10M
100M
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
Frequency (Hz)
Large Signal Pulse Response
Gain Flatness & Linear Phase Deviation
Small Signal Pulse Response
4.0
2.0
0
0.20
0.10
0
Av+2
Av+2
Phase
Gain
Av-2
-2.0
-4.0
-0.10
-0.20
Av-2
Time (10ns/div)
1M
10M
Time (10ns/div)
Frequency (Hz)
Pulse Crosstalk
Short Term Settling Time
Long Term Settling Time
0.2
0.1
0
0.4
0.2
0
Vout = 2Vstep
Active Output Channel
-0.2
-0.4
-0.1
-0.2
Time (10ns/div)
0
20n
40n
60n
80n
100n
1µ
10µ
100µ
1m
10m
100m
1
Time (s)
Time (s)
Settling Time vs. Capacitive Load
IBI, IBN, VOS vs. Temperature
70
60
50
40
30
20
10
60
7.0
6.0
5.0
4.0
3.0
2.0
1.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VOS
50
40
30
20
10
0
Rs
IBI
0.05%
0.1%
IBN
20p
100p
1000p
-50
0
50
100
CL (F)
Temperature (°C)
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4
CLC418 OPERATION
The CLC418 has a current-feedback (CFB) architecture
where:
built in an advanced complementary bipolar process.
The key features of current-feedback are:
■
■
■
A is the DC voltage gain
v
R is the feedback resistor
f
Z(jω) is the CLC418’s open-loop
transimpedance gain
■
AC bandwidth is independent of voltage gain
■
Inherently unity-gain stability
■
Frequency response may be adjusted with
Z jω
(
)
is the loop gain
■
feedback resistor (R in Figures 1-3)
f
R
f
■
■
High slew rate
The denominator of the equation above is approximately
at low frequencies. Near the -3dB corner
frequency, the interaction between R and Z(jω)
Low variation in performance for a wide range
of gains, signal levels and loads
Fast settling
1
f
■
dominates the circuit performance. Increasing R does
f
Current-feedback operation can be explained with a
simple model. The voltage gain for the circuits in Figures 1
and 2 is approximately:
the following:
■
Decreases loop gain
■
Decreases bandwidth
V
A
■
Reduces gain peaking
o
v
R
=
■
V
Lowers pulse response overshoot
f
in
1+
■
Affects frequency response phase linearity
Z jω
(
)
CLC418 DESIGN INFORMATION
Standard op amp circuits work with CFB op amps. There
are 3 unique design considerations for CFB:
The normalized gain plots in the Typical Performance
Characteristics section show different feedback
resistors (R ) for different gains. These values of R are
recommended for obtaining the highest bandwidth with
f
f
■
The feedback resistor (R in Figures 1-3) sets
AC performance
f
minimal peaking. The resistor R provides DC bias for
t
■
■
R cannot be replaced with a short or a capacitor
f
the non-inverting input.
The output offset voltage is not reduced by
balancing input resistances
For A < 6, use linear interpolation on the nearest A
v
v
v
values to calculate the recommended value of R . For A
f
The following sub-sections cover:
≥ 6, the minimum recommended R is 200Ω.
f
■
Design parameters, formulas and techniques
Interfaces
Application circuits
Layout techniques
SPICE model information
R
f
■
■
■
■
Select R to set the DC gain:
R =
g
g
A −1
v
DC gain accuracy is usually limited by the tolerance of R
f
and R .
g
DC Gain (non-inverting)
The non-inverting DC voltage gain for the configuration
DC Gain (unity gain buffer)
The recommended R for unity gain buffers is 3kΩ. R is
f
g
R
left open. Parasitic capacitance at the inverting node
f
shown in Figure 1 is:
A = 1+
v
may require a slight increase of R to maintain a flat
R
f
g
frequency response.
VCC
6.8µF
DC Gain (inverting)
+
The inverting DC voltage gain for the configuration
R
f
shown in Figure 2 is:
A = −
0.1µF
v
8
Vin
3(5)
2(6)
R
+
g
1(7)
Vo
1/2
CLC418
The normalized gain plots in the Typical Performance
Characteristics section show different feedback
resistors (R ) for different gains. These values of R are
Rt
-
4
Rf
f
f
0.1µF
Rg
recommended for obtaining the highest bandwidth with
minimal peaking. The resistor R provides DC bias for
the non-inverting input.
t
+
6.8µF
VEE
For |A | < 6, use linear interpolation on the nearest A
v
v
values to calculate the recommended value of R . For
f
Figure 1: Non-Inverting Gain
|A | ≥ 6, the minimum recommended R is 200Ω.
v
f
5
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VCC
Rt
Rg
Rref
6.8µF
+
+
Vo
1/2
CLC418
Vin
-
0.1µF
Rt
8
3(5)
2(6)
+
1(7)
Vo
1/2
CLC418
Rf
Vref
-
Rg
4
Rf
Vin
Figure 4: Level Shifting Circuit
DC Design (DC offsets)
The DC offset model shown in Fig. 5 is used to calculate
the output offset voltage. The equation for output offset
voltage is:
0.1µF
+
6.8µF
VEE
R
f
Figure 2: Inverting Gain
V = − V +I
R
1+
+ I
R
(
)
(
)
o
os
eq1
BN
BI
f
R
eq2
R
f
Select R to set the DC gain:
. At large gains,
R =
g
g
The current offset terms, I
and I , do not track
BI
each other. The specifications are stated in terms of
magnitude only. Therefore, the terms V , I , and I
can have either polarity. Matching the equivalent
resistance seen at both input pins does not reduce the
output offset voltage.
A
BN
v
R becomes small and will load the previous stage. This
g
os BN
BI
can be solved by driving R with a low impedance buffer
g
like the CLC111, or increasing R and R . See the
f
g
AC Design (small signal bandwidth) sub-section for
the tradeoffs.
IBN
DC gain accuracy is usually limited by the tolerance of R
f
+
and R .
+
g
Vo
1/2
Vos
CLC418
-
Req1
DC Gain (transimpedance)
-
RL
Figure 3 shows a transimpedance circuit where the
current I is injected at the inverting node. The current
IBI
Req2
Rf
in
source’s output resistance is much greater than R .
f
V
o
The DC transimpedance gain is:
A
=
= −R
f
R
I
in
The recommended R is 3kΩ. Parasitic capacitance at
f
Figure 5: DC Offset Model
DC Design (output loading)
the inverting node may require a slight increase of R to
f
maintain a flat frequency response.
R , R , and R load the op amp output. The equivalent
load seen by the output in Figure 5 is:
L
f
g
DC gain accuracy is usually limited by the tolerance of R .
f
VCC
R || (R + R ), non-inverting gain
L
f
eq2
R
=
6.8µF
L(eq)
R || R , inverting and transimpedance gain
+
L
f
The equivalent output load (R
) needs to be large
L(eq)
0.1µF
Rt
8
enough so that the output current can produce the
required output voltage swing.
3(5)
2(6)
+
1(7)
Vo
1/2
CLC418
-
AC Design (small signal bandwidth)
The CLC418 current-feedback amplifier bandwidth is a
4
Rf
0.1µF
function of the feedback resistor (R ), not of the DC voltage
Iin
f
gain (A ). The bandwidth is approximately proportional
V
+
1
6.8µF
.
to
As a rule, if R doubles, the bandwidth is cut in half.
f
R
VEE
f
Other AC specifications will also be degraded.
Figure 3: Transimpedance Gain
Decreasing R from the recommended value increases
f
peaking, and for very small values of R oscillation
will occur.
DC Design (level shifting)
Figure 4 shows a DC level shifting circuit for inverting
f
gain configurations. V produces a DC output level shift
ref
AC Design (minimum slew rate)
R
f
Slew rate influences the bandwidth of large signal
sinusoids. To determine an approximate value of slew
rate necessary to support a large sinusoid, use the
of −V
, which is independent of the DC output
ref
R
ref
produced by V .
in
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6
following equation:
SR > 5 f V
AC Design (crosstalk)
Crosstalk performance depends on the layout. Three
layout techniques that can reduce crosstalk are:
•
•
peak
where V
is the peak output sinusoidal voltage.
peak
■
Provide short symmetrical ground return paths for:
■
the inputs
the supply bypass capacitors
the load
The slew rate of the CLC418 in inverting gains is always
higher than in non-inverting gains.
■
■
AC Design (linear phase/constant group delay)
■
Provide a short, grounded guard trace that:
The recommended value of R produces minimal peaking
■
goes underneath the package
f
and a reasonably linear phase response. To improve
phase linearity when |A | < 6, increase R approximately
■
is 0.1” (3mm) from the package pins
is on top and bottom of the printed circuit
■
v
f
50% over its recommended value. Some adjustment of
board with connecting vias
R may be needed to achieve phase linearity for your
application. See the AC Design (small signal band-
f
■
Try different bypass capacitors to reduce high
frequency crosstalk
width) sub-section for other effects of changing R .
f
The CLC418’s evaluation board was used to produce the
Input-Referred Crosstalk plot.
Propagation delay is approximately equal to group delay.
Group delay is related to phase by this equation:
Capacitive Loads
Capacitive loads, such as found in A/D converters,
require a series resistor (R ) in the output to improve
d φ f
( )
≈ −
∆φ f
( )
1
1
τ
f = −
( )
gd
360° d f
360° ∆f
s
settling performance. The Settling Time vs. Capacitive
Load plot in the Typical Performance Characteristics
section provides the information for selecting this resistor.
where φ(f) is the phase in degrees. Linear phase implies
constant group delay. The technique for achieving linear
phase also produces a constant group delay.
Using a resistor in series with a reactive load will also
reduce the load’s effect on amplifier loop dynamics. For
instance, driving coaxial cables without an output series
resistor may cause peaking or oscillation.
AC Design (peaking)
Peaking is sometimes observed with the recommended
R . If a small increase in R does not solve the problem,
f
f
then investigate the possible causes and remedies
listed below:
Transmission Line Matching
One method for matching the characteristic impedance
of a transmission line is to place the appropriate
resistor at the input or output of the amplifier. Figure 6
shows the typical circuit configurations for matching
transmission lines.
■
Capacitance across R
f
■
Do not place a capacitor across R
f
■
Use a resistor with low parasitic
capacitance for R
f
■
■
A capacitive load
C6
Z0
R1
R3
R2
Rg
R5
■
Use a series resistor between the output
+
Z0
Vo
R7
1/2
and a capacitive load (see the Settling
+
-
CLC418
-
V1
V2
R6
Time versus C plot)
L
Z0
Rf
R4
Long traces and/or lead lengths between R
and the CLC418
f
+
-
■
Keep these traces as short as possible
Figure 6: Transmission Line Matching
For non-inverting and transimpedance gain configurations:
In non-inverting gain applications, R is connected
■
Extra capacitance between the inverting
g
directly to ground. The resistors R , R , R6, and R are
pin and ground (C )
1
2
7
g
equal to the characteristic impedance, Z , of the
o
■
See the Printed Circuit Board Layout
transmission line or cable. Use R to isolate the
3
sub-section below for suggestions on
amplifier from reactive loading caused by the transmis-
sion line, or by parasitics.
reducing C
g
■
Increase R if peaking is still observed
f
after reducing C
g
In inverting gain applications, R is connected directly to
3
ground. The resistors R , R , and R are equal to Z . The
For inverting gain configurations:
4
6
7
o
parallel combination of R and R is also equal to Z .
5
g
o
■
Inadequate ground plane at the non-inverting
pin and/or long traces between non-inverting
pin and ground
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
■
Place a 50 to 200Ω resistor between the
Use C to match the output transmission line over a greater
6
non-inverting pin and ground (see R in
Figure 2)
frequency range. It compensates for the increase of
the op amps output impedance with frequency.
t
7
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Thermal Design
Dynamic Range (noise)
To calculate the power dissipation for the CLC418, follow
these steps for each individual amplifier:
The output noise defines the lower end of the CLC418’s
useful dynamic range. Reduce the value of resistors in
the circuit to reduce noise.
1) Calculate the no-load op amp power:
P
= I • (V – V
)
amp
CC
CC
EE
See the App Note Noise Design of CFB Op Amp
Circuits for more details. Our SPICE models support noise
simulations.
2) Calculate the output stage’s RMS power:
P = (V – V ) • I , where V and I
load
are the RMS voltage and current across the
external load
3) Calculate the total op amp RMS power:
o
CC
load
load
load
Dynamic Range (distortion)
The distortion plots in the Typical Performance
Characteristics section show distortion as a function
of load resistance, frequency, and output amplitude.
Distortion places an upper limit on the CLC418’s
dynamic range.
P = P
+ P
t
amp
o
Now calculate the total power dissipated in the package:
4) Sum P for both op amps to obtain P
t
tot
To calculate the maximum allowable ambient tempera-
ture, solve the following equation: T = 175 – P
•
,
θ
amb
tot
JA
The CLC418’s output stage combines a voltage buffer
with a complementary common emitter current source.
The interaction between the buffer and the current
source produces a small amount of crossover distortion.
This distortion mechanism dominates at low output swing
and low resistance loads. To avoid this type of distortion,
use the CLC418 at high output swing.
where
is the thermal resistance from junction
θ
JA
to ambient in °C/W, and T
Thermal Resistance section contains the thermal
resistance for various packages.
is in °C. The Package
amb
Dynamic Range (input /output protection)
ESD diodes are present on all connected pins for protec-
tion from static voltage damage. For a signal that may
exceed the supply voltages, we recommend using diode
clamps at the amplifier’s input to limit the signals to less
than the supply voltages.
Realized output distortion is highly dependent upon the
external circuit. Some of the common external circuit
choices that can improve distortion are:
■
Short and equal return paths from the load to
the supplies
The CLC418’s output current can exceed the maximum
safe output current. To limit the output current to < 96mA:
■
De-coupling capacitors of the correct value
Higher load resistance
■
Limit the output voltage swing with diode
■
clamps at the input
V
o(max)
■
Make sure that
R
≥
Printed Circuit Board Layout
L
I
o(max)
High frequency op amp performance is strongly dependent
on proper layout, proper resistive termination and
adequate power supply decoupling. The most important
layout points to follow are:
V
is the output voltage swing limit, and I
is the
o(max)
o(max)
maximum safe output current.
Dynamic Range (input /output levels)
The Electrical Characteristics section specifies the
Common-Mode Input Range and Output Voltage
Range; these voltage ranges scale with the supplies.
Output Current is also specified in the Electrical
Characteristics section.
■
Use a ground plane
Bypass power supply pins with:
■
■
monolithic capacitors of about 0.1µF place
less than 0.1” (3mm) from the pin
■
tantalum capacitors of about 6.8µF for
Unity gain applications are limited by the Common-Mode
Input Range. At greater non-inverting gains, the Output
Voltage Range becomes the limiting factor. Inverting
gain applications are limited by the Output Voltage
Range (and by the previous amplifier’s ability to drive
large signal current swings or improved
power supply noise rejection;
we recommend a minimum of 2.2µF
for any circuit
R ). For transimpedance gain applications, the sum of
the input currents injected at the inverting input pin of
g
■
Minimize trace and lead lengths for components
between the inverting and output pins
V
■
Remove ground plane 0.1” (3mm) from all
input/output pads
max
the op amp needs to be: I
≤
, where V
is the
max
in
R
f
■
For prototyping, use flush-mount printed circuit
board pins; never use high profile DIP sockets.
Output Voltage Range (see the DC Gain (transimpedance)
sub-section for details).
Evaluation Board
The equivalent output load needs to be large enough
so that the minimum output current can produce the
required output voltage swing. See the DC Design
(output loading) sub-section for details.
Separate evaluation boards are available for proto-typing
and measurements. Additional information is available in
the evaluation board literature.
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8
2
SPICE Models
SPICE models provide a means to evaluate op amp
designs. Free SPICE models are available that:
n
Z
(jω)
o(418)
Return Loss ≈ -20 log
, dB
10
Z
o
where Z
(jω) is the output impedance of the CLC418,
o(418)
■
Support Berkeley SPICE 2G and its many
derivatives
and |Z
(jω)| << R .
o(418)
m
■
Reproduce typical DC, AC, Transient, and
Noise performance
Support room temperature simulations
The load voltage and current will fall in the ranges:
≤ n V
■
V
o
max
The readme file that accompanies the models lists the
released models, and provides a list of modeled
parameters. The application note Simulation
SPICE Models for Comlinear’s Op Amps contains
schematics and detailed information.
I
max
I
≤
o
n
The CLC418’s high output drive current and low
distortion make it a good choice for this application.
Lowpass Anti-aliasing Filter
with Delay Equalization
The circuit shown in Figure 7 is a 5th-order Butterworth
lowpass filter with group delay equalization. V needs to
CLC418 Applications
Differential Line Driver With Load
Impedance Conversion
in
be a voltage source with low output impedance. Section
The circuit shown in the Typical Application schematic
on the front page operates as a differential line driver.
The transformer converts the load impedance to
a value that best matches the CLC418’s output
capabilities. The single-ended input signal is
converted to a differential signal by the CLC418. The
line’s characteristic impedance is matched at both the
input and the output. The schematic shows Unshielded
Twisted Pair for the transmission line; other types of lines
can also be driven.
A
is
a
simple single-pole filter. Section
B
provides a single-pole allpass function for group delay
equalization. Sections C and D are Sallen-Key lowpass
biquad sections.
R1A
Vin
+
R1B
VoA
1/2
+
CLC418
C2A
VoB
1/2
-
U1A
RfA
CLC418
C2B
R3B
-
U1B
RfB
Set up the CLC418 as a difference amplifier:
V
R
R
d
f1
f2
= 2 1+
= 2
V
R
R
g2
g1
in
C5C
C5D
R1C R3C
C4C
R1D
αD
+
R3D
C4D
VoC
Make the best use of the CLC418’s output drive
capability as follows:
1/2
CLC418
+
Vo
1/2
CLC418
-
R1D
1- αD
U2C
RfC
-
U2D
RfD
2 V
max
R
+R
=
eq
m
I
max
RgD
where R
is the transformed value of the load
eq
impedance, V
is the Output Voltage Range, and I
max
max
is the maximum Output Current.
Figure 7: Lowpass Anti-aliasing Filter
Match the line’s characteristic impedance:
The filter specifications we built to are:
f = 10MHz (passband corner frequency)
R = Z
c
o
L
f = 20MHz (stopband corner frequency)
s
R
= R
eq
m
A = 3.01dB (maximum passband attenuation)
p
R
L
n =
A = 30dB
(minimum stopband attenuation)
(DC gain)
s
R
eq
H = 0dB
o
Select the transformer so that it loads the line with a
value very near Z over your frequency range. The out-
put impedance of the CLC418 also affects the match.
With an ideal transformer we obtain:
The designed component values are in the table below.
The pre-distorted values compensate for the finite band-
width of the CLC418.
o
9
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For more information on the design of Sallen-Key filters and
filter pre-distortion, see Comlinear’s App Notes on filters.
Value
Component
Ideal
Pre-distorted
Precision Full-Wave Rectifier
Figure 9 shows a precision full-wave rectifier using the
R
C
238Ω
67pF
3.01kΩ
314Ω
67pF
953Ω
953Ω
108Ω
1.06kΩ
22pF
100pF
3.01kΩ
256Ω
256Ω
900Ω
22pF
211Ω
300Ω
1A
2A
CLC418. When V > 0, D is on, D is off, V = 0 and an
in
1
2
2
R
fA
1B
2B
3B
overall non-inverting gain is achieved. When V < 0, D
in
1
R
C
R
is off, D is on, both V and V are positive, and an over-
2
1
2
all inverting gain is achieved. The output voltage of the
rectifier is:
R
fB
R
R
C
C
100Ω
1.07kΩ
1C
3C
4C
5C
R +R +R
2
5
7
R
1
V ,V < 0
in in
R +R
R
R
2
5
4
6
1+
1+
V =
o
R
R
fC
/α
3
R
227Ω
227Ω
850Ω
1D
D
R
R
R
2
7
5
>
V ,V
0
R
/(1-α )
D
in in
1D
R
1
R
C
C
3D
4D
5D
100pF
953Ω
953Ω
R2 V1 R5
D1
D2
R7
R
fD
R1
Vin
R
gD
-
-
Vo
1/2
1/2
CLC418
+
CLC418
Table 1: Filter Component Values
+
U1a
R3
U1b
R4
R6
The nearest standard values for capacitors and resistors
were used to build this filter. The resistors were 1%
tolerance, and the capacitors 5% tolerance. The ideal
and measured gains are shown in Figure 8.
20Ω
V2
C1
0
-10
-20
Figure 9: Precision Full-Wave Rectifier
Diodes D and D need to be Schottky or PIN diodes to
1
2
minimize delay.
Select the voltage gain for U1a (G < 0) and U1b (G ).
-30
1
2
Measured
G needs to be ≤ 1, approximately, to ensure realizable
2
-40
-50
values of R . The overall gain is:
4
V
o
= G G , V > 0
Ideal
1
2
in
-60
V
in
1
10
Frequency (MHz)
Set R = R to the recommended feedback resistor
2
3
value for the gain A = R . You may need to increase R
v
2
2
1
Figure 8: Lowpass Anti-aliasing Filter Response
and R slightly to compensate for the delays through D
3
and D .
To change the cutoff frequency of this filter, do the following:
2
Set R to the recommended feedback resistor value for
■
Determine the new cutoff frequency:
7
the gain A = (1 + G ).
f
v
2
3dB(418)
, where f
is the
f
≤
3dB(418)
c(new)
10
bandwidth of the CLC418
Calculate the ratio:
■
Scale (multiply) all frequency specifications and
plot axes by f /f
Make sure that your system requirements are met
R
R
R
R
R
1
7
2
2
3
7
3
1+
1+
− 1+
G −
2
R
G
c(new) c
R
R
2
4
=
■
■
■
R
R
R
6
7
3
2
G
+
Scale (multiply) all capacitor values by f /f
2
c c(new)
R
3
Set the resistors to the Ideal Values in the table
above (the pre-distorted values do not linearly
scale with frequency)
If this ratio is negative, reduce G and recalculate the
values up to this point.
2
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10
Calculate all other resistor values:
We built and tested a full-wave rectifier with the
following values:
R
2
R =
1
■
D = D = Schottky Diodes,
G
1
2
1
Digi-Key # SD101ACT-ND
R
7
■
■
■
■
■
R =
R = R = R = 1.00kΩ
2 3 7
5
G
2
R = 1.00kΩ
1
R
R = 1.50kΩ
5
5
R =
6
R = 882Ω
R
R
6
4
6
1+
R = 618Ω
4
The rectifier had equal inverting and non-inverting gains
for frequencies less than 10MHz. The -3dB bandwidth
was about 25MHz.
R = R −R
6
4
5
Notice that R and R are selected so that U1a and the
4
6
diodes see a balanced load for both polarities of V .
in
The capacitor C is optional. It helps compensate for the
1
difference between the gains V /V and V /V at high
o
1
o
2
frequencies. Both R and R must be > 0.
4
6
Ordering Information
Package Thermal Resistance
Model
Temperature Range
Description
Package
Plastic (AJP)
Surface Mount (AJE)
θJC
θJA
CLC418AJP
CLC418AJE
CLC418AJE-TR
CLC418AJE-TR13
CLC418ALC
-40 C to +85 C
8-pin PDIP
8-pin SOIC
8-pin SOIC, 750pc reel
8-pin SOIC, 2500pc reel
dice (commercial)
80 C/W
95 C/W
˚
˚
˚
˚
-40 C to +85 C
95 C/W
115 C/W
˚
˚
˚
˚
-40 C to +85 C
˚
˚
-40 C to +85 C
˚
˚
Reliability Information
-40 C to +85 C
˚
˚
Transistor Count
MTBF (based on limited test data)
76
34Mhr
11
http://www.national.com
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval
of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax: (+49) 0-180-530 85 86
E-mail: europe.support.nsc.com
Deutsch Tel: (+49) 0-180-530 85 85
English Tel: (+49) 0-180-532 78 32
Francais Tel: (+49) 0-180-532 93 58
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Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
N
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
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12
Lit #150418-003
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