CLC420AJE-TR13 [NSC]
High-Speed, Voltage Feedback Op Amp; 高速，电压反馈运算放大器
| 型号： | CLC420AJE-TR13 |
| 厂家： | 
National Semiconductor |
| 描述： | High-Speed, Voltage Feedback Op Amp |
| 文件： | 总10页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1999
CLC420
High-Speed, Voltage Feedback Op Amp
General Description
Applications
n Active filters/integrators
n Differential amplifiers
n Pin diode receivers
n Log amplifiers
The CLC420 is an operational amplifier designed for applica-
tions requiring matched inputs, integration or transimped-
ance amplification. Utilizing voltage feedback architecture,
the CLC420 offers a 300MHz bandwidth, a 1100V/µs slew
rate and
a 4mA supply current (power consumption of
n D/A converters
n Photo multiplier amplifiers
±
40mW, 5V supplies).
Applications such as differential amplifiers will benefit from
70dB common mode rejection ratio and an input offset cur-
rent of 0.2µA. With its unity-gain stability, 2pA/
Non-Inverting Frequency Response
current
noise and 3µA of input bias current, the CLC420 is designed
to meet the needs of filter applications and log amplifiers.
The low input offset current and current noise, combined
with a settling time of 18ns to 0.01% make the CLC420 ideal
for D/A converters, pin diode receivers and photo multipliers
amplifiers. All applications will find 70dB power supply rejec-
tion ratio attractive.
Features
n 300MHz small signal bandwidth
n 1100V/µs slew rate
n Unity-gain stability
n Low distortion, -60dBc at 20MHz
n 0.01% settling in 18ns
n 0.2µA input offset current
DS012752-19
n 2pA
current noise
Connection Diagram
DS012752-18
Pinout
DIP & SOIC
DS012752-20
2nd and 3rd Harmonic Distortion
© 1999 National Semiconductor Corporation
DS012752
www.national.com
Ordering Information
Package
Temperature Range
Packaging
Marking
NSC
Drawing
N08E
Industrial
8-pin plastic DIP
−40˚C to +85˚C
−40˚C to +85˚C
CLC420AJP
8-pin plastic SOIC
CLC420AJE
M08A
CLC420AJE-TR13
www.national.com
2
±
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Common Mode Input Voltage
Differential Input Voltage
Junction Temperature
VCC
10V
+150˚C
Operating Temperature Range
AJ:
−40˚C to +85˚C
−65˚C to +150˚C
10 sec
±
7V
Supply Voltage (VCC
)
Storage Temperature Range
Lead Solder Duration (+300˚C)
IOUT
(is short circuit protected to ground,
but maximum reliability will be
maintained if IOUT does not exceed
70mA, except A8D, B8D which should
not exceed 35mA over the military
temperature range)..
Electrical Characteristics
=
=
= =
5V, RL 100Ω, Rf 0Ω; unless specified
±
AV +1, VCC
Symbol
Parameter
Conditions
Typ
Max/Min (Note 2)
Units
Ambient Temperature
CLC420AJ
+25˚C
−40˚C
+25˚C
+85˚
Frequency Domain Response
<
>
>
>
>
>
>
>
>
>
130
SSBW
LSBW
SSBWI
LSBWI
-3dB bandwidth
VOUT 0..4VPP
300
40
200
200
MHz
MHz
MHz
MHz
<
>
>
>
VOUT 5VPP
20
65
30
25
65
35
20
45
30
=
=
<
Av −1, Rf 500Ω
VOUT 0.4VPP
100
60
=
=
<
VOUT 5VPP
Av −1, Rf 500Ω
gain flatness
peaking
<
VOUT 0.4VPP
<
<
<
GFPL
0.1MHz to
100MHz
0
1
0.6
0.6
dB
>
<
<
<
<
<
<
GFPH
GFR
peaking
rolloff
100MHz
0
5
1
3
1
3
2
dB
dB
0.1MHz to
100MHz
0.2
=
=
<
<
<
<
<
<
GFRI
LPD
rolloff, Av −1, Rf 500Ω
0.1MHz to
30MHz
0.2
0.9
1.4
1.8
1.4
1.8
1.6
2.5
dB
˚
linear phase deviation
0.1MHz to
100MHz
Time Domain Response
<
<
<
3
<
20
<
7.8
TRS
TRL
TRSI
rise and fall time
0.4V step
5V step
1.2
1.4
3.5
2
2
ns
ns
ns
<
<
25
20
=
<
<
rise and fall time,Av −1,
0.4V step
5.5
5.5
=
Rf 500Ω
<
<
<
<
<
<
<
<
<
<
<
<
TRLI
TSS
TSP
OS
5V step
2V step
2V step
0.4V step
5V step
5V step
6
12
10
18
25
35
9.5
10
18
25
25
ns
ns
±
settling time to 0.1%
18
25
25
±
0.01%
overshoot
18
ns
8
%
=
>
>
>
>
>
>
SR
slew rate, Av +2
1100
750
600
430
750
500
600
430
V/µs
V/µs
=
=
slew rate, Av −1, Rf 500Ω
SRI
Distortion And Noise Response
<
<
<
<
<
<
<
<
<
HD2
HD3
HD2
2nd harmonic distortion
3rd harmonic distortion
2nd harmonic distortion
2VPP, 20MHz
2VPP, 20MHz
=
−50
−53
−51
−40
−45
−40
−40
−45
−40
−40
−40
−40
dBc
dBc
dBc
Av −1 2VPP
,
=
20MHz, Rf 500
=
<
<
<
HD3
3rd harmonic distortion
Av −1,
−51
−40
−40
−35
dBc
=
Rf 500Ω2VPP
,
=
20MHz, Rf 500
input referred noise
voltage
<
<
<
6
VN
1MHz to
200MHz
4.2
5.3
5.3
nV/
3
www.national.com
Electrical Characteristics (Continued)
=
=
= =
5V, RL 100Ω, Rf 0Ω; unless specified
±
AV +1, VCC
Symbol Parameter
Distortion And Noise Response
ICN current
Conditions
Typ
Max/Min (Note 2)
Units
<
<
<
<
<
<
1MHz to
200MHz
2
2.9
2.6
2.3
pA/
Static DC Performance
<
<
<
<
<
VIO
input offset voltage (Note 3)
1
8
3.2
2
3.5
mV
µV/˚C
µA
DVIO
IB
average temperature coefficient
input bias current (Note 3)
average temperature coefficient
input offset current (Note 3)
average temperature coefficient
open loop gain (Note 3)
15
20
-
15
10
60
<
3
10
-
<
DIB
45
0.2
2
120
A/˚C
µA
<
<
>
>
>
<
<
IIO
2.6
1
2
10
56
60
65
<
>
>
>
DIIO
AOL
PSRR
CMRR
ICC
20
52
55
60
-
nA/˚C
µA
>
>
>
65
70
80
4
56
60
65
power supply rejection ratio
common mode rejection ratio
supply current (Note 3)
dB
dB
<
<
<
no
5
5
5
mA
load,quiescent
Miscellaneous Performance
>
>
<
>
<
RIND
CIND
RINC
CINC
RO
differential mode input
resistance
capacitance
resistance
capacitance
at DC
2
1
0.5
1
2
1
2
MΩ
pF
MΩ
pF
Ω
<
2
>
>
<
>
<
common mode input
1
0.25
0.5
0.5
<
<
<
2
1
2
2
<
output impedence
0.02
0.3
2.8
2.5
2.5
0.2
0.2
±
±
±
±
±
±
±
±
3
VO
output voltage range
output voltage range
common mode input range
no load
3.6
2.9
3.2
3
V
=
±
±
±
±
VOL
CMIR
RL 100Ω
2.5
2.8
2.5
2.8
V
for rated
V
performance
±
±
±
±
IO
output current
60
-
30
-
50
-
50
-
mA
Package Thermal Resistance
junction
to
case
CLC420AJP
CLC420AJP
CLC420AJE
CLC420AJE
65˚
C/W
junction
to
ambient
120˚
60˚
-
-
-
-
-
-
-
-
-
-
-
-
C/W
C/W
C/W
junction
to
case
junction
to
140˚
ambient
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: AJ-level: spec. is 100% tested at +25˚C.
www.national.com
4
Typical Performance Characteristics
Non-Inverting Frequency Response
Inverting Frequency Response
Frequency Response for Various
RLS
DS012752-2
DS012752-1
DS012752-3
Open Loop Gain and Phase
Bandwidth vs. Gain,
Transimpedance Configuration
2nd and 3rd Harmonic Distortion
DS012752-4
DS012752-6
DS012752-5
2-Tone, 3rd Order Intermodulation
Intercept
Equivalent Input Noise
PSRR, CMRR, and Closed Loop RO
DS012752-8
DS012752-9
DS012752-7
5
www.national.com
Typical Performance Characteristics (Continued)
Pulse Response
Settling Time
Long-Term Settling Time
DS012752-10
DS012752-11
DS012752-12
Settling Time vs. Capacitive Load
Settling Time vs. Gain
IB and IOS vs. Common-Mode
Voltage
DS012752-13
DS012752-15
DS012752-14
www.national.com
6
Application Division
DS012752-16
FIGURE 1. Recommended Non-Inverting Gain Circuit
DS012752-17
FIGURE 2. Recommended Inverting Gain Circuit
Description
Another point to remember is that the closed-loop bandwidth
is determined by the noise gain, not the signal gain of the cir-
cuit. Noise gain is the reciprocal of the attenuation in the
feedback network enclosing the op amp. For example, a
The CLC420 is a high-speed, slew-boosted, voltage feed-
back amplifier with unity-gain stability. These features along
with matched inputs, low input bias and noise currents, and
excellent CMRR render the CLC420 very attractive for active
filters, differential amplifiers, log amplifiers, and transimped-
ance amplifiers.
CLC420 setup as
a non-inverting amplifier with a
closed-loop gain of +1 (a noise gain of 1) has a 300MHz
bandwidth. When used as an inverting amplifier with a gain
of −1 (a noise gain of 2), the bandwidth is less, typically only
100MHz.
DC accuracy
Unlike current-feedback amplifiers, voltage-feedback ampli-
fiers have matched inputs. This means that the non-inverting
and inverting input bias current are well matched and track
over temperature, etc. As a result, by matching the resis-
tance looking out of the two inputs, these errors can be re-
duced to a small offset current term.
Full-power bandwidth, and slew-rate
The CLC420 combines exceptional full-power bandwidths
=
=
(40MHz, V0 5Vpp, Av +1) and slew rates (1100V/µs,
=
Av +1) with low (40mW) power consumption. These attrac-
tive results are achieved by using slew-boosting circuitry to
keep the slew rates high while consuming very little power.
Gain bandwidth product
In non-slew boosted amplifiers, full-power bandwidth can be
easily determined from slew-rate measurements, but in
slew-boosting amplifiers, such as the CLC420, you can’t. For
this reason we provide data for both.
Since the CLC420 is
a
voltage-feedback op-amp,
closed-loop bandwidth is approximately equal to the
gain-bandwidth product (typically 100MHz) divided by the
noise gain of the circuit (for noise gains greater than 5). At
lower noise gains, higher-order amplifier poles contribute to
higher closed-loop bandwidth. At low gains use the fre-
quency response performance plots given in the data sheet.
Slew rate is also different for inverting and non-inverting con-
figurations. This occurs because common-mode signal volt-
ages are present in non-inverting circuits but absent in in-
verting circuits. Once again data is provided for both.
7
www.national.com
From the “Transimpedance BW vs. Rf and Ci” plot, using
Application Division (Continued)
=
=
Ci 5pF it is determined from the two curves labeled Ci 5pF,
=
Transimpedance amplifier circuits
that Cf 1.5pF provides optimal compensation (no more than
0.5dB frequency response peaking) and a −3dB bandwidth
of approximately 27MHz.
Low inverting, input current noise (2pA/
) makes the
CLC420 ideal for high-sensitivity transimpedance amplifier
circuits for applications such as pin-diode optical receivers,
and detectors in receiver IFs. However, feedback resistors
4kΩ or greater are required if feedback resistor noise current
is going to be less than the input current noise contribution of
the op-amp.
Printed circuit layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. The amplifier is sensitive to stray
capacitance to ground at the output and inverting input:
Node connections should be small with minimal coupling to
the ground plane.
With feedback resistors this large, shunt capacitance on the
inverting input of the op-amp (from the pin-diode, etc.) will
unacceptably degrade phase margin causing frequency re-
sponse peaking or oscillations a small valued capacitor
shunting the feedback resistor solves this problem (Note:
This approach does not work for a current-feedback op-amp
configured for transimpedance applications). To determine
the value of this capacitor, refer to the “Transimpedance BW
vs. Rf and Ci” plot.
Parasitic or load capacitance directly on the output (pin 6)
will introduce additional phase shift in the loop degrading the
loop phase margin and leading to frequency response peak-
ing.
A small series resistor before this capacitance, if
present, effectively decouples this effect. The graphs on the
preceding page, “ Settling Time vs. CL”, illustrates the re-
quired resistor value and resulting performance vs. capaci-
tance.
For example, let’s assume an optical transimpedance re-
ceiver is being developed. Total capacitance from the invert-
ing input to ground, including the photodiode and strays is
5pF. A 5kΩ feedback resistor value has been determined to
provide best dynamic range based on the response of the
photodiode and the range of incident optical powers, etc.
Evaluation PC boards (part no. 730013 for through-hole and
CLC730027 for SOIC) are available for the CLC420.
www.national.com
8
Physical Dimensions inches (millimeters) unless otherwise noted
N08E - CLC420AJP
M08A - CLC420AJE or CLC420AJE-TR13
9
www.national.com
Notes
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Tel: 1-800-272-9959
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