CLC425A8B [NSC]
Ultra Low Noise Wideband Op Amp; 超低噪声宽带运算放大器
| 型号： | CLC425A8B |
| 厂家： | 
National Semiconductor |
| 描述： | Ultra Low Noise Wideband Op Amp |
| 文件： | 总9页 (文件大小：1277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
N
CLC425
Ultra Low Noise Wideband Op Amp
General Description
Features
The CLC425 combines a wide bandwidth (1.9GHz GBW) with very
lowinputnoise(1.05nV/√Hz, 1.6pA/√Hz)andlowdcerrors(100µV
VOS, 2µV/°C drift) to provide a very precise, wide dynamic-range
op amp offering closed-loop gains of ≥10.
■ 1.9GHz gain-bandwidth product
■ 1.05nV/√Hz input voltage noise
■ 0.8pA/√Hz @ Icc < 5mA
■ 100µV input offset voltage, 2µV/°C drift
■ 350V/µs slew rate
Singularlysuitedforverywidebandhigh-gainoperation,theCLC425
employs a traditional voltage-feedback topology providing all the
benefits of balanced inputs, such as low offsets and drifts, as well
as a 96dB open-loop gain, a 100dB CMRR and a 95dB PSRR.
■ 15mA to 5mA adjustable supply current
■ Gain range ±10 to ±1,000V/V
■ Evaluation boards & simulation
macromodel
■ 0.9dB NF @ R = 700Ω
s
The CLC425 also offers great flexibility with its externally adjustable
supply current, allowing designers to easily choose the optimum
set of power, bandwidth, noise and distortion performance.
Operating from ±5V power supplies, the CLC425 defaults to a
15mA quiescent current, or by adding one external resistor, the
supply current can be adjusted to less than 5mA.
Applications
■ Instrumentation sense amplifiers
■ Ultrasound pre-amps
■ Magnetic tape & disk pre-amps
■ Photo-diode transimpedance amplifiers
■ Wide band active filters
■ Low noise figure RF amplifiers
■ Professional audio systems
■ Low-noise loop filters for PLLs
The CLC425's combination of ultra-low noise, wide gain-band-
width, high slew rate and low dc errors will enable applications in
areas such as medical diagnostic ultrasound, magnetic tape & disk
storage, communications and opto-electronics to achieve maximum
high-frequency signal-to-noise ratios.
Equivalent Input Voltage Noise
10
The CLC425 is available in the following versions:
CLC425AJP
CLC425AJE
CLC425A8B
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
8-pin PDIP
8-pin SOIC
8-pin CERDIP,
MIL-STD-883, Level B
dice
dice, MIL-STD-883, Level B
5-pin SOT
CLC425ALC
CLC425AMC
CLC425AJM5
-40°C to +85°C
-55°C to +125°C
-40°C to +85°C
1.05nV/√Hz
1
100
1k
10k
100k
1M
10M 100M
Frequency (Hz)
DESC SMD number : 5962-93259.
Pinout
SOT23-5
Pinout
DIP & SOIC
Vo
VCC
NC
1
2
3
4
8
7
6
5
Rp (optional)
+Vcc
-
Vinv
Vnon-inv
-Vcc
VEE
+
Vout
Vnon-inv
Vinv
NC
1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
CLC425 Electrical Characteristics (VCC = ±5V; AV = +20; Rf =499
Ω
; Rg = 26.1
Ω
; RL = 100
Ω
; unless noted)
PARAMETERS
CONDITIONS
TYP
MIN/MAX RATINGS
UNITS
SYMBOL
Ambient Temperature
CLC425 AJ
+25°C
-40°C
+25°C
+85°C
FREQUENCY DOMAIN RESPONSE
gain bandwidth product
-3dB bandwidth
Vout < 0.4Vpp
1.9
95
40
1.5
75
30
1.5
75
30
1.0
50
20
GHz
MHz
MHz
GBW
SSBW
LSBW
Vout < 0.4Vpp
Vout < 5.0Vpp
Vout < 0.4Vpp
DC to 30MHz
DC to 30MHz
DC to 30MHz
gain flatness
peaking
rolloff
0.3
0.1
0.7
0.7
0.7
1.5
0.5
0.5
1.5
0.7
0.7
2.5
dB
dB
°
GFP
GFR
LPD
linear phase deviation
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.2%
overshoot
0.4V step
2V step
0.4V step
3.7
22
5
4.7
30
12
4.7
30
10
7.0
40
12
ns
ns
%
V/µs
TRS
TSS
OS
slew rate
2V step
350
250
250
200
SR
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
3rd harmonic distortion
3rd order intermodulation intercept
equivalent noise input
voltage
1Vpp, 10MHz
1Vpp, 10MHz
- 53
- 75
35
48
65
48
65
46
60
dBc
dBc
dBm
HD2
HD3
IMD
10MHz
1MHz to 100MHz
1MHz to 100MHz
RS = 700Ω
1.05
1.6
0.9
1.25
4.0
1.25
2.5
1.8
2.5
nV/√Hz VN
pA/√Hz ICN
dB
current
noise figure
NF
STATIC DC PERFORMANCE
open-loop gain
*input offset voltage
average drift
DC
96
± 100
± 2
77
86
86
± 1000
4
20
- 120
2.0
± 25
86
90
16
dB
µV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
AOL
VIO
DVIO
IB
DIB
IIO
DIIO
PSRR
CMRR
ICC
± 1000 ± 800
8
40
- 250
3.4
± 50
82
88
18
____
*input bias current
12
20
____
average drift
input offset current
average drift
power supply rejection ratio
common mode rejection ratio
*supply current
- 100
± 0.2
± 3
95
100
15
2.0
____
DC
DC
RL= ∞
88
92
16
MISCELLANEOUS PERFORMANCE
input resistance
common-mode
2
6
1.5
1.9
5
± 3.8
± 3.4
± 3.8
80
0.6
1
2
3
50
± 3.5
± 2.8
± 3.4
70
1.6
3
2
3
10
± 3.7
± 3.2
± 3.5
70
1.6
3
2
3
10
± 3.7
± 3.2
± 3.5
70
MΩ
kΩ
pF
pF
mΩ
V
V
V
mA
RINC
RIND
CINC
CIND
ROUT
VO
VOL
CMIR
IOP
differential-mode
common-mode
differential-mode
closed loop
RL= ∞
input capacitance
output resistance
output voltage range
RL=100Ω
input voltage range
output current
common mode
source
sink
80
45
55
55
mA
ION
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Vcc
Miscellaneous Ratings
±7V
Recommended gain range
±10 to ±1,000V/V
I
out short circuit protected to ground, however maximum reliabiliy
Notes:
is obtained if Iout does not exceed...
125mA
±Vcc
* AJ :100% tested at +25°C.
common-mode input voltage
maximum junction temperature
operating temperature range:
AJ
storage temperature range
lead temperature (soldering 10 sec)
ESD (human body model)
+150°C
Package Thermal Resistance
-40°C to +85°C
-65°C to +150°C
+300°C
Package
θJC
θJA
AJP
AJE
A8B
70°C/W
65°C/W
45°C/W
115°C/W
125°C/W
145°C/W
135°C/W
185°C/W
1000V
AJM5
Reliability Information
Transistor count
31
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2
3
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4
+Vcc
7
Total Input Noise vs. Source Resistance
6.8µF
0.1µF
In order to determine maximum signal-to-noise ratios
from the CLC425, an understanding of the interaction
between the amplifier's intrinsic noise sources and the
noise arising from its external resistors is necessary.
Vin
3
Rs
6
Vout
CLC425
Vs
RT
2
6.8µF
4
Figure 3 describes the noise model for the non-inverting
amplifier configuration showing all noise sources. In
addition to the intrinsic input voltage noise (en) and
current noise (in=in+=in-) sources, there also exists ther-
0.1µF
-Vcc
Rs
Rs || RT
=
eq
Rf
Av = 1 +
mal voltage noise (
) associated with each of
et =
4kTR
Rg
Rf
Rg
the external resistors. Equation 1 provides the general
form for total equivalent input voltage noise density (eni).
Equation 2 is a simplification of Equation 1 that assumes
Figure 1: Non-inverting Amplifier Configuration
Introduction
The CLC425 is a very wide gain-bandwidth, ultra-low
noise voltage feedback operational amplifier which en-
ables application areas such as medical diagnostic ultra-
sound, magnetic tape & disk storage and fiber-optics to
achieve maximum high-frequency signal-to-noise ratios.
The set of characteristic plots located in the "Typical
Performance" section illustrates many of the perfor-
mance trade-offs. The following discussion will enable
the proper selection of external components in order to
achieve optimum device performance.
en
Rs
eq
CLC425
+
in
√4kTRs
eq
Rf
Rg
√4kTRf
-
in
√4kTRg
4kT = 16.4e − 21 Joules
@ 25°C
Bias Current Cancellation
In order to cancel the bias current errors of the non-
inverting configuration, the parallel combination of the
gain-setting(Rg)andfeedback(Rf)resistorsshouldequal
Figure 3: Non-inverting Amplifer Noise Model
the equivalent source resistance (Rs ) as defined in
eq
2
2
Figure 1. Combining this constraint with the non-invert-
ing gain equation also seen in Figure 1, allows both Rf
and Rg to be determined explicitly from the following
eni
=
e2 + i Rs
+ 4kTRs + i R ||R
+ 4kT R ||R
n
n+
n−
f
g
f
g
eq
eq
equations: Rf=AvRs and Rg=Rf/(Av-1). When driven from
eq
Equation 1: General Noise Equation
a 0Ω source, such as that from the output of an op amp,
the non-inverting input of the CLC425 should be isolated
with at least a 25Ω series resistor.
Rf||Rg = Rs for bias current cancellation. Figure 4
eq
illustrates the equivalent noise model using this as-
sumption. Figure 5 is a plot of eni against equivalent
As seen in Figure 2, bias current cancellation is accom-
plished for the inverting configuration by placing a resis-
tor (Rb) on the non-inverting input equal in value to the
resistance seen by the inverting input (Rf||(Rg+Rs)). Rb is
recommended to be no less than 25Ω for best CLC425
performance. The additional noise contribution of Rb can
be minimized through the use of a shunt capacitor.
source resistance (Rs ) with all of the contributing volt-
eq
age noise sources of Equation 2 shown. This plot gives
the expected eni for a given Rs which assumes Rf||Rg =
eq
Rs for bias current cancellation. The total equivalent
output voltage noise (eno) is eni Av.
eq
√4kT2Rs
+Vcc
eq
en
6.8µF
Av
2Rs
eq
7
3
in
√2
0.1µF
Vout
CLC425
Rb
6
2
6.8µF
0.1µF
4
Figure 4: Noise Model with Rf||Rg = Rs
eq
Vin
-Vcc
Rs
Rg
Av = -
Rf
2
e = e2 + 2 i R
+ 4kT 2R
(
Vs
(
)
)
ni
n
n
seq
seq
Rf
Rg
Figure 2: Inverting Amplifier Configuration
Equation 2: Noise Equation with Rf||Rg = Rs
eq
5
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As seen in Figure 5, eni is dominated by the intrinsic
voltage noise (en) of the amplifier for equivalent source
resistances below 33.5Ω. Between 33.5Ω and 6.43kΩ,
The noise figure is related to the equivalent source
resistance (Rs ) and the parallel combination of Rf and
eq
Rg. To minimize noise figure, the following steps are
recommended:
e is dominated by the thermal noise (
) of
et =
ni
4kTRseq
theexternalresistors. Above6.43kΩ, eni isdominatedby
the amplifier's current noise ( ). The point at
• Minimize Rf||Rg
2inRseq
which the CLC425's voltage noise and current noise
contribute equally occurs for Rs =464Ω (i.e. ).
• Choose the optimum Rs (ROPT
)
en / 2in
eq
ROPT is the point at which the NF curve reaches a
minimum and is approximated by:
As an example, configured with a gain of +20V/V giving
a -3dB of 90MHz and driven from an Rs =25Ω, the
eq
ROPT (en/in)
CLC425 produces a total equivalent input noise voltage
(
) of 16.5µV .
eni 1.57 90MHz
rms
Figure 6 is a plot of NF vs Rs with Rf||Rg = 9.09 (Av = +10).
The NF curves for both Unterminated and Terminated
systems are shown. The Terminated curve assumes Rs
= RT. The table indicates the NF for various source
resistances including Rs = ROPT
.
Figure 5: Voltage Noise Density vs. Source Resistance
If bias current cancellation is not a requirement, then
Rf||Rg doesnotneedtoequalRs . Inthiscase, according
eq
Figure 6: Noise Figure vs Source Resistance
to Equation 1, Rf||Rg should be as low as possible in
order to minimize noise. Results similar to Equation 1
are obtained for the inverting configuration of Figure 2 if
Supply Current Adjustment
The CLC425's supply current can be externally adjusted
downward from its nominal value by adding an optional
resistor (Rp) between pin 8 and the negative supply as
shown in Figure 7. Several of the plots found within the plot
pages demonstrate the CLC425’s behavior at different
supply currents. The plot labeled “Icc vs. Rp” provides the
means for selecting Rp and shows the result of standard IC
process variation which is bounded by the 25°C curve.
Rs is replaced by Rb and Rg is replaced by Rg+Rs. With
eq
these substitutions, Equation 1 will yield an eni refered to
the non-inverting input. Refering eni to the inverting input
is easily accomplished by multiplying eni by the ratio of
non-inverting to inverting gains.
Noise Figure
Noise Figure (NF) is a measure of the noise degradation
caused by an amplifier.
+Vcc
2
3
Si / Ni
eni
7
NF = 10LOG
= 10LOG
6
2
So / No
CLC425
4
Vout
et
2
8
Rp
The Noise Figure formula is shown in Equation 3. The
addition of a terminating resistor RT, reduces the
external thermal noise but increases the resulting NF.
The NF is increased because RT reduces the input signal
amplitude thus reducing the input SNR.
-Vcc
Figure 7: External Supply Current Adjustment
Non-Inverting Gains Less Than 10V/V
Using the CLC425 at lower non-inverting gains requires
external compensation such as the shunt compensation
as shown in Figure 8. The quiescent supply current must
also be reduced to 5mA with Rp for stability. The com-
pensation capacitors are chosen to reduce frequency
response peaking to less than 1dB. The plot in the
"Typical Performance" section labeled “Differential Gain
andPhase”showsthevideoperformanceoftheCLC425
with this compensation circuitry.
2
2
2
en + in Rseq + R | | R
+ 4kTRseq + 4kT R | | R
(
)
(
)
f
g
f
g
NF = 10LOG
4kTRseq
Rseq = Rs for Unterminated Systems
Rseq = Rs II RT for Terminated Systems
Equation 3: Noise Figure Equation
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6
Cf
Icc=5mA
CLC425
Rs = 75Ω
+Vcc
75Ω
Cin
39pF
Rin
75Ω
Rf
75Ω
Rf
=
124Ω
CLC425
Av = −Iin Rf
Rg
=
124Ω
Cf
=
10pF
Rb
Figure 8: External Shunt Compensation
Figure 11: Transimpedance Amplifier Configuration
Inverting Gains Less Than 10V/V
The lag compensation of Figure 9 will achieve stability
for lower gains. Placing the network between the two
input terminals does not affect the closed-loop nor noise
gain, but is best used for the invering configuration
because of its affect on the non-inverting input imped-
ance.
Vin
Rg
Rf
Vout
Rout
R
C
CLC425
RL
Rb
Figure 12: Transimpedance Amplifier Frequency Response
Figure 9: External Lag Compensation
Single-Supply Operation
The CLC425 can be operated with single power supply
as shown iin Figure 10. Both the input and output are
capacitively coupled to set the dc operating point.
Vcc
Vcc
Vcc
Vcc
Vout =
+ AvVac
R
R
2
2
Vac
C
CLC425
Rout
C
RL
Figure 13: Current Noise Density vs. Feedback Resistance
Rf
Rg
2
C
en
4kT
ini
=
in2
+
+
Rf
Rf
Figure 10: Single Supply Operation
Low Noise Transimpedance Amplifier
Equation 4: Total Equivalent Input Refered Current
The circuit of Figure 11 implements a low-noise transim-
pedance amplifier commonly used with photo-diodes.
The transimpedance gain is set by Rf. The simulated
frequency response is shown in Figure 12 and shows
the influence Cf has over gain flatness. Equation 4
provides the total input current noise density (ini) equa-
tion for the basic transimpedance configuration and is
plotted against feedback resistance (Rf) showing all
contributing noise sources in Figure 13. This plot indi-
cates the expected total equivalent input current noise
density(ini)foragivenfeedbackresistance(Rf). Thetotal
equivalent output voltage noise density (eno) is ini Rf.
Very Low Noise Figure Amplifier
The circuit of Figure 14 implements a very low Noise
Figure amplifier using a step-up transformer combined
with a CLC425 and a CLC404. The circuit is configured
with a gain of 35.6dB. The circuit achieves measured
Noise Figures of less than 2.5dB in the 10-40MHz
region. 3rd order intercepts exceed +30dBm for frequen-
cies less than 40MHz and gain flatness of 0.5dB is measured
inthe1-50MHzpassbands. ApplicationNoteOA-14provides
greater detail on these low Noise Figure techniques.
7
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40kΩ
Vin
R = 681Ω
Vo
Pi
600Ω
CLC425
R1
C1
=
45.3Ω
50Ω
10Ω
Av=+10
CLC425
200Ω
1:4
Po
=
2200pF
50Ω
806Ω
CLC404
1pF
0.1µF
50Ω
Av=-3
180Ω
20Ω
Rf = 1kΩ
R2
=
200Ω
0.1µH
Rg
=
50Ω
50kΩ
20Ω
Mini-Circuits
T16-6T
Rf
Rg
L
=
C
=
470pF
Ko = 1+
Po
Pi
Gain =
= 35.6dB
Figure 14: Very Low Noise Figure Amplifier
Rf
Rf + Rg
sLRg
s2 LCR R + sL R + R + R R
g
Vo
sC1 R1 +1
sC R + R +1
= Ko
−
V
(
)
(
)
in
1
1
2
g
2
g
2
Low Noise Integrator
The CLC425 implements a deBoo integrator shown in
Figure 15. Integration linearity is maintained through
positive feedback. The CLC425's low input offset
voltage and matched inputs allowing bias current
cancellation provide for very precise integration. Stabil-
ity is maintained through the constraint on the circuit
elements.
Figure 17: Low Noise Magnetic Media Equalizer
Rf
Rg
Ko
Vo
V
;
Ko = 1+
in
sRaC
Rb
Ra
Vo
Vin
CLC425
Rf
C
R
50Ω
50Ω
Figure 18: Equalizer Frequency Response
Low-Noise Phase-Locked Loop Filter
Rg
The CLC425 is extremely useful as a Phase-Locked
Loop filter in such applications as frequency synthesiz-
ers and data synchronizers. The circuit of Figure 19
implements one possible PLL filter with the CLC425.
Rf
Rb
≥
,
R >> Ra
Ra ||R Rg
Rf
Cf
Figure 15: Low Noise Integrator
Vin
Vout
Rg
CLC425
High-Gain Sallen-Key Active Filters
The CLC425 is well suited for high-gain Sallen-Key type
ofactivefilters. Figure16showsthe2nd orderSallen-Key
low pass filter topology. Using component predistortion
methods as discussed in OA-21 enables the proper
Rb
selection of components for these high-frequency filters.
Figure 19: Phased-Locked Loop Filter
C1
Decreasing the Input Noise Voltage
R1
R2
The input noise voltage of the CLC425 can be reduced
fromitsalreadylow1.05nV/√Hzbyslightlyincreasingthe
supply current. Using a 50kΩ resistor to ground on pin 8,
as shown in the circuit of Figure 14, will increase the
quiescent current to ≈17mA and reduce the input noise
voltage to < 0.95nV/√Hz.
CLC425
Rf
C2
Rg
Printed Circuit Board Layout
Generally, a good high-frequency layout will keep power
supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes
to ground will cause frequency response peaking and
possible circuit oscillation, see OA-15 for more informa-
tion. National suggests the CLC730013-DIP,
CLC730027-SOIC, or CLC730068-SOT evaluation
board as a guide for high-frequency layout and as an aid
in device testing and characterization.
Figure 16: Sallen-Key Active Filter Topology
Low Noise Magnetic Media Equalizer
The CLC425 implements a high-performance low-noise
equalizer for such applications as magnetic tape
channelsasshowninFigure17. Thecircuitcombinesan
integrator with a bandpass filter to produce the low-
noise equalization. The circuit's simulated frequency
response is illustrated in Figure 18.
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8
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of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
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Corporation
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circuitry and specifications.
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12
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