CLC520AJE-TR13 [NSC]

IC 1 CHANNEL, VIDEO AMPLIFIER, PDSO14, PLASTIC, SOIC-14, Audio/Video Amplifier;


型号：	CLC520AJE-TR13
厂家：	National Semiconductor
描述：	IC 1 CHANNEL, VIDEO AMPLIFIER, PDSO14, PLASTIC, SOIC-14, Audio/Video Amplifier 放大器光电二极管商用集成电路
文件：	总13页 (文件大小：459K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

February 2001

CLC520

Amplifier with Voltage Controlled Gain, AGC +Amp

General Description

Features

n 160MHz, −3dB bandwidth

n 2000V/µsec slew rate

The CLC520 is a wideband DC-coupled amplifier with volt-

age controlled gain (AGC). The amplifier has a high imped-

ance, differential signal input; a high bandwidth, gain control

input; and a single-ended voltage output. Signal channel

performance is outstanding with 160MHz small signal band-

width, 0.5 degree linear phase deviation (to 60MHz) and

0.04% signal nonlinearity at 4V_PPoutput.

n 0.04% signal nonlinearity at 4V_PPoutput

n −43dB feedthrough at 30MHz

n User adjustable gain range

n Differential voltage input and single-ended voltage

output

Gain control is very flexible and easy to use. Maximum gain

may be set over a nominal range of 2 to 100 with one

external resistor. In addition, the gain control input provides

more than 40dB of voltage controlled gain adjustment from

the maximum gain setting. For example, a CLC520 may be

set for a maximum gain of 2 (or 6dB) for a voltage controlled

gain range from 40dB to less than 34dB. Alternatively, the

CLC520 could be set for a maximum gain of 100 or (40dB)

for a voltage controlled gain range from 40dB to less than

0dB.

Applications

n Wide bandwidth AGC systems

n Automatic signal leveling

n Video signal processing

n Voltage controlled filters

n Differential amplifier

n Amplitude modulation

The gain control bandwidth of 100MHz is superb for AGC/

ALC loop stabilization. And since the gain is minimum with a

zero volt input and maximum with a +2 volt input, driving the

control input is easy.

Gain vs. V_g

Finally, the CLC520 differential inputs, and ground refer-

enced voltage output take the trouble out of designing

DC-coupled AGC circuits for display normalizers; signal lev-

eling automatic circuits; etc.

Enhanced Solutions (Military/Aerospace)

SMD Number: 5962-91694

Space level versions also available.

For more information, visit http://www.national.com/mil

DS012756-40

Connection Diagram

DS012756-39

Gain vs. V_g

DS012756-29

Pinout

DIP & SOIC

DS012756

www.national.com

Ordering Information

Package

Temperature Range

Industrial

Part Number

Package

Marking

NSC

Drawing

N14A

14-pin plastic DIP

14-pin plastic SOIC

−40˚C to +85˚C

CLC520AJP

CLC520AJE

CLC520AJP

CLC520AJE

M14A, M14B

www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Junction Temperature

+150˚C

−40˚C to +85˚C

−65˚C to +150˚C

10 sec

Operating Temperature Range

Storage Temperature Range

Lead Solder Duration (+300˚C)

ESD (human body model)

500V

Supply Voltage (V_CC

I_OUT

)

Operating Ratings

Thermal Resistance

Output is short circuit protected to

ground, but maximum reliability will

be maintained if I_OUTdoes not

exceed...

60mA

Package

MDIP

(θ_JC

)

(θ_JA)

Common Mode Input Voltage

V_INDifferential Input Voltage

V_gDifferential Input Voltage

V_refDifferential Input Voltage

V_CC

10V

V_CC

55˚C/W

45˚C/W

105˚C/W

120˚C/W

SOIC

Electrical Characteristics

5V, R_L= 100Ω, R_f= 1kΩ, R_g= 182Ω, V_g= +2V; unless specified

A_V= +10, V_CC

Symbol

Parameter

Conditions

CLC520AJ

Typ

Max/Min (Note 2)

Units

Ambient Temperature

Frequency Domain Response

+25˚C

−40˚C

+25˚C

+85˚C

SSBW

LSBW

-3dB Bandwidth

V_OUT0.5V_PP

160

140

110

120

100

120

100

MHz

V_OUT0.5V_PP(AJE only)

V_OUT4.0V_PP

-3dB Bandwidth

Gain Control Channel

Gain Flatness

Peaking

V_OUT0.5V_PP

SBWC

V_IN= +0.2V, V_g= +1VDC

100

MHz

V_OUT0.5V_PP

GFPL

GFPH

GFRL

GFRH

LPD

FDTH

TRS

TRL

0.1MHz to 30MHz

0.1MHz to 20MHz

0.1MHz to 30MHz

0.1MHz to 60MHz

V_g= 0V, V_IN= -22dBm

0.5V Step

0.4

0.7

0.4

1.3

1.2

-31

3.7

0.3

0.5

0.3

0.4

0.7

0.4

1.3

1.2

-31

Peaking

Rolloff

0.1

0.5

-38

2.5

3.7

Rolloff

Linear Phase Deviation

Feedthrough

Rise and Fall Time

deg

-31

4.0V Step

Settling Time to 0.1%

2.0V Step

Overshoot

0.5V Step

1450

Slew Rate

4V Step

2000

−47

−60

1450

V/µsec

dBc

HD2

HD3

2nd Harmonic Distortion

3rd Harmonic Distortion

Equivalent Output Noise

2V_PP, 20MHz

−40

−50

−40

−50

−35

−45

(÷10 for input noise)

(Note 3)

SNF

Noise floor

1MHz to 200MHz

−132

−130

1000

−130

1000

−129

1100

dBm

(1Hz)

INV

Integrated noise

1MHz to 200MHz

at 3.58MHz

800

0.15

µV

Differential Gain (Note 4)

Differential PIase (Note 4)

at 3.58MHz

deg

Static, DC Performance

0.2

SGNL

Integral Signal Nonlinearity

V_OUT= 4V_PP

0.04

0.1

Gain Accuracy

R_f= 1kΩ, R_g= 182Ω

0.5

GACCU

VOS

For Nominal Max Gain = 20dB

Output Offset Voltage (Note 5)

1.0

0.5

150

400

120

–

150

300

DVOS

Average Temperature

Coefficient

100

µV/˚C

Input Bias Current (Note 5)

µA

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Electrical Characteristics (Continued)

5V, R_L= 100Ω, R_f= 1kΩ, R_g= 182Ω, V_g= +2V; unless specified

A_V= +10, V_CC

Symbol

Parameter

Conditions

Typ

Max/Min (Note 2)

Units

Static, DC Performance

165

DIB

Average Temperature

100

415

nA/˚C

Doefficient

IOS

Input Offset Current

0.5

µA

DIOS

Average Temperature

Coefficient

nA/˚C

250

PSS

CMRR

ICC

Power Supply Sensitivity

Common Mode Rejection Ratio

Supply Current (Note 5)

V_INSignal Input

Output Referred DC

Input Referred

No Load

200

mV/V

kΩ

RIN

Resistance

100

CIN

Capacitance

DMIR

CMIR

RINC

CINC

VGHI

VGLO

V_INDifferential Voltage Range

Common Mode Voltage Range

V_gControl Input

R_g= 182Ω only

280

250

210

2.2

750

1.4

Resistance

Capacitance

For Max Gain

For Min Gain

At DC

535

600

Ω

0.2

3.2

kΩ

V_gInput Voltage

1.6

0.4

0.1

Output Impedance

Output Voltage Range

Output Current

0.3

0.2

Ω

No Load

3.5

3.2

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined

from tested parameters.

Note 3: Measured at A

= 10, V = +2V

VMAX

Note 4: Differential gain and phase are measured at: A = +20, V = +2V, R = 150Ω, R = 2kΩ, R = 182Ω, equivalent video signal of 0-100 IRE with 40 IRE

at 3.58 MHz.

Note 5: AJ-level: spec. is 100% tested at +25˚C.

Typical Performance Characteristics (T_A= 25˚C, A_V= +10, V_CC

5V, R_L= 100Ω, R_f= 1kΩ, R_g

182Ω, V_g= +2V)

Frequency Response, A_VMAX

DS012756-30

DS012756-16

www.national.com

Typical Performance Characteristics (T_A= 25˚C, A_V= +10, V_CC

5V, R_L= 100Ω, R_f= 1kΩ, R_g

182Ω, V_g= +2V)) (Continued)

100

Frequency Response, A_VMAX

Large Signal Frequency Response

DS012756-19

DS012756-21

Small Signal Gain vs. R_f

2nd Harmonic Distortion

DS012756-41

DS012756-1

3rd Harmonic Distortion

2nd and 3rd Harmonic Distortion vs. V_g

DS012756-3

DS012756-2

www.national.com

Typical Performance Characteristics (T_A= 25˚C, A_V= +10, V_CC

5V, R_L= 100Ω, R_f= 1kΩ, R_g=

182Ω, V_g= +2V)) (Continued)

Gain vs. V_g

DS012756-40

DS012756-39

Large and Small Signal Pulse Response

Settling Time, V_g= 2V

DS012756-42

DS012756-13

Settling Time, V_g= 1.2V

Long-Term Settling Time

DS012756-14

DS012756-15

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Typical Performance Characteristics (T_A= 25˚C, A_V= +10, V_CC

5V, R_L= 100Ω, R_f= 1kΩ, R_g=

182Ω, V_g= +2V)) (Continued)

Settling Time vs. Capacitive Load, A_VMAX

Gain Control Channel Feedthrough

Differential Gain and Phase

Gain Control Settling Time

DS012756-17

DS012756-4

CMRR

DS012756-18

DS012756-5

PSRR

DS012756-43

DS012756-6

www.national.com

Typical Performance Characteristics (T_A= 25˚C, A_V= +10, V_CC

5V, R_L= 100Ω, R_f= 1kΩ, R_g=

182Ω, V_g= +2V)) (Continued)

Output Noise vs. V_g

Linearity, V_g= 0.6V to 1.6V

DS012756-44

DS012756-22

Linearity, V_g= 0.75V to 1.4V

Linearity, V_g= 0.9V to 1.2V

DS012756-45

DS012756-46

(+V_IN)−(−V_IN), the differential input voltage. This current con-

trols a current source which supplies two well matched tran-

sistors, Q1 and Q2.

Application Information

The current flowing through Q2 is converted to the final

output voltage using R_fand output amplifier, U1. By chang-

ing the fraction of the signal current I which flows through Q2

the gain is changed. This is done by changing the voltage

applied differentially to the bases of Q1 and Q2. For ex-

ample, with V_g= 0, Q1 is on and Q2 is off. With zero signal

current of flowing through Q2 into R_f, the CLC520 is set to

minimum gain. Conversely, with V_g= 2V, Q1 is off and all of

the signal current I flows through Q2 to R_fproducing maxi-

mum gain. With V_gset to 1.1V, the bases of Q1 and Q2 are

set to approximately the same voltage, causing their collec-

tor currents to equally divide the signal current I, and estab-

lish the gain at one half the maximum gain.

DS012756-7

FIGURE 1. CLC520 Simplified Schematic

Simplified Circuit Description

Typical application circuit

A simplified schematic for the CLC520 is given in Figure 1.

+V_INand −V_INare buffered with closed-loop voltage follow-

Figure 2 illustrates a voltage-controlled gain block offering

broadband performance in a 50Ω system environment. The

input signal is applied to pin 3 of the CLC520 and terminating

resistor R2. Gain control signals are applied to pin 2. The net

ers inducing

a signal current in R_gproportional to

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Application Information (Continued)

gain control port input impedance is 50Ω, set by the parallel

combination of R1 and the 750Ω input impedance of pin 2 of

the CLC520. R_fis set to the standard value, 1kΩ, and R_g

sets the maximum voltage gain to 10V/V. Output impedance

is set by R_oto 50Ω so with 50Ω source and load termina-

tions, the gain is approximately 14dB.

DS012756-28

FIGURE 3. CLC520 Offset Adjustment Circuitry

(other external elements not shown)

Selecting component values

Most applications of the CLC520 adjust the gain to maximize

the V_OUTsignal. When referred back to the input, this means

the input signal, signal-to-noise ratio is maximized. The

maximum allowed input amplitude and from system specifi-

cations, using maximum required gain R_fand R_gcan be

calculated.

The output stage op amp is a current-feedback type amplifier

optimized for R_f= 1kΩ. R_gcan then be computed as:

DS012756-8

FIGURE 2. CLC520 Typical Application Circuit

Capacitors C1-C6 provide broadband power supply bypass-

ing. C2 and C5 should be tantalum capacitors. All other

capacitors should be high quality ceramic capacitors (CK-05

or equivalent).

To determine whether the maximum input amplitude will

overdrive the CLC520, compute:

Adjusting offset

V_dmax= (R_g+3.0Ω) · 0.00135

Offset can be broken into two parts; an input-referred term

and an output-referred term. The input-referred offset shows

up as a variation in output voltage as V_gis changed. This can

be trimmed using the circuit in Figure 3 by placing a low

frequency square wave (V_IN= 0 to 2V, into V_gwith V_IN= 0V,

the input referred V_osterm shows up as a small square wave

riding a DC value. Adjust R₁to null the V_ossquare wave term

to zero. After adjusting the input-referred offset, adjust R2

(with V_IN= 0, V_g= 0) until V_OUTis zero. Finally, for inverting

applications V_INmay be applied to pin 6 and the offset

adjustment to pin 3. This offset trim does not improve output

offset temperature coefficient.

the maximum differential input voltage for linear operation. If

the maximum input amplitude exceeds the above V_dmaxlimit,

then CLC520 should either be moved to a location in the

signal chain where input amplitudes are reduced, or the

CLC520 gain A_VMAXshould be reduced or the values for R_g

and R_fshould be increased. The overall system performance

impact is different based on the choice made.

If the input amplitude is reduced, recompute the impact on

signal-to-noise ratio. If A_VMAXis reduced,

DS012756-47

FIGURE 4. CLC520 Noise Model

Post CLC520 amplifier gain, should be increased, or another

gain stage added to make up for reduced system gain..

To increase R_gand R_f, where V_dmax= (+V_IN)−(−V_IN) the

largest expected peak differential input voltage. Compute the

lowest acceptable value for R_g:

R_g740 ˚ V_dmax−3Ω

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Application Information (Continued)

Operating with R_glarger than this value insures linear op-

eration of the input buffers.

R_fmay be computed from selected R_gand A_VMAX

R_fshould be = 1kΩ for overall best performance, however

R_f1kΩ can be implemented if necessary using a loop gain

reducing resistor to ground on the inverting summing node of

the output amplifier (see application note QA-13 for details).

Printed Circuit Layout

DS012756-48

A good high frequency PCB layout including ground plane

construction and power supply bypassing close to the pack-

age are critical to achieving full performance. The amplifier is

sensitive to stray capacitance to ground at the

Inverting-input (pin12); keep node trace area small. Shunt

capacitance across the feedback resistor should not be used

to compensate for this effect.

FIGURE 5. Equivalent Input Noise Voltage (e_n) vs. R_g

Several points should be made concerning this model. First,

external component noise contributions need to be factored

in when computing total output referred noise. The only

exception is R_g, where its noise contribution is already fac-

tored in. Second, the model ignores flicker noise contribu-

tions. Applications where noise below approximately 100kHz

must be considered should use this model with caution.

Third, this model very accurately predicts output noise volt-

age for the typical application circuit (see above) but accu-

racy will degrade the component values deviate further from

those in the typical application circuit. In general, however,

the model should predict the equivalent output noise above

the flicker noise region to within a few dB of actual perfor-

mance over the normal range of A_VMAXand component

values.

For best performance at low maximum gains (A_VMAX10)

R_g+ and R_gconnections should be treated in a similar fash-

ion. Capacitance to ground should be minimized by remov-

ing the ground plane from under the resistor of R_g.

Parasitic or load capacitance directly on the output (pin 10)

degrades phase margin leading to frequency response

peaking. A small series resistor before this capacitance,

effectively reduces this effect (see Settling Time vs. Capaci-

tive Load).

Precision buffed resistors (PRP8351 series from Precision

Resistive Products) must be used for R_ffor rated perfor-

mance. Precision buffed resistors are suggested for R_gfor

low gain settings (A_VMAX10). Carbon composition resis-

tors and RN55D metal-film resistors may be used with re-

duced performance.

Evaluation PC boards (part no. 730021) for the CLC520 are

available.

Predicting the output noise

DS012756-10

Seven noise sources (e_n, i_n, i_i, i_io, i_no, e_no, E_core) are used to

model the CLC520 noise performance (Figure 4). e_n, i_n, and

i_imodel the equivalent input noise terms for the input buffer

while i_io, i_no, and e_nomodel the noise terms for the output

buffer. To simplify the model e_nincludes the effect of resistor

R_g(see Figure 5 for e_nvs. R_g). To simplify the model further,

R_biasis assumed noiseless and its noise contribution is

included in i_io.

FIGURE 6. Typical Circuit

An additional term E_coremimics the active device noise

contribution from the Gilbert multiplier core. Core noise is

theoretically zero when the multiplier is set to maximum gain

or zero gain (V_g1.6V or V_g0.63V respectively at room

temperature) and reaches a maximum of 37nV/ at

_VMAX/2.

DS012756-11

FIGURE 7. Noise Model for Typical Circuit

Calculating CLC520 output noise in a typical circuit

To calculate the noise in a CLC520 application, the noise

terms given for the amplifier as well as the noise terms of the

external components must be included. To clarify the tech-

niques used, output noise in a typical circuit will be calcu-

lated. (Figure 6)

The noise model is depicted in Figure 7. The diagram as-

sumes spot noise source with V_rms

and Amps_rms/

units. The Thevenin equivalent of the source and input ter-

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Using these equations, total calculated output noise for the

Application Information (Continued)

circuit was 20nV/

mid-gain, and 53nV/

at minimum gain, 49nV/

at maximum gain.

mination is used; 25Ω in series with a noise voltage source.

R_gis assumed noiseless since its effect is included in e_n.

The internal 5kΩ resistor at the CLC520 core output is also

assumed noiseless since its effect is included in i_io, The

noise contribution from R_fis modeled as a noise source.

The easiest way to analyze the output noise of this circuit is

to divide the noise power into three pieces; −input buffer

noise calculation, output buffer noise and core noise. The

input buffer varies with the gain. The output buffer term is

constant. The core noise term is zero at both maximum and

minimum gain and reaches peak at A_VMAX/2.

Since we assume all noise terms are uncorrelated, the

equivalent input noise voltage squared is given by:

DS012756-12

FIGURE 8. Automatic Gain Control (AGC) Loop

AGC circuits

i_idoes not contribute to the output buffer noise because the

input buffer inverting input is grounded. e_nis taken from

Figure 5.

Figure 8 shows a typical AGC circuit. The CLC520 is fol-

lowed up with a CLC401 for higher overall gain. The output

of the CLC401 is rectified and fed to an inverting integrator

using a CLC420 (wideband voltage feedback op amp).

When the output voltage, V_OUT, is too large the integrator

output voltage ramps down reducing the net gain of the

CLC520 and V_OUT. If the output voltage is too small, the

integrator ramps up increasing the net gain and the output

voltage. Actual output level is set with R1. To prevent shifts in

DC output voltage with DC changes in input signal level, trim

pot R2 is provided. AGC circuits are always limited in the

range of input signals over which constant output level can

be maintained. In this circuit, we would expect that reason-

able AGC action could be maintained over the gain adjust-

ment range of the CLC520 (at least 40dB). In practice,

rectifier dynamic range limits reduce this slightly.

The equivalent output buffer noise is given by:

i_nodoes not contribute to the output buffer noise because the

output buffer non-inverting input is grounded.

The core noise is already output referred and is 37nV/

V_g=1.1 (A_VMAX/2) and approaches zero as A goes to 0 or

A_VMAXSumming the noise power for each term gives the

total output noise power.

The total output noise voltage is given by:

Evaluation Board

Evaluation PC boards (part number 730029 for through-hole

and 730023 for SOIC) for the CLC520 are available.

Where A_Vis the input to output voltage gain, which varies

with V_g.

C accounts for the variation in core noise contribution as V_g

is adjusted. C=1 when gain A_Vis A_VMAX/2. C is zero at

A_VMAXand A_V= 0 and varies between 0 and 1 for all other

values.

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Physical Dimensions inches (millimeters) unless otherwise noted

14-Pin MDIP

NS Package Number N14A

14-Pin SOIC

NS Package Number M14A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Pin SOIC

NS Package Number M14B

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

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Europe

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Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

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Tel: 81-3-5639-7560

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Email: ap.support@nsc.com

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

CLC520AJE-TR13 [NSC]

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