CLC5602IM [NSC]
Dual, High Output, Video Amplifier; 双通道，高输出，视频放大器
| 型号： | CLC5602IM |
| 厂家： | 
National Semiconductor |
| 描述： | Dual, High Output, Video Amplifier |
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
N
CLC5602
Dual, High Output, Video Amplifier
General Description
Features
■
The National CLC5602 has a new output stage that delivers high
output drive current (130mA), but consumes minimal
quiescent supply current (1.5mA/ch) from a single 5V supply. Its
current feedback architecture, fabricated in an advanced comple-
mentary bipolar process, maintains consistent performance over
a wide range of gains and signal levels, and has a linear-phase
response up to one half of the -3dB frequency.
130mA output current
■
0.06%, 0.02° differential gain, phase
1.5mA/ch supply current
135MHz bandwidth (A = +2)
-87/-95dBc HD2/HD3 (1MHz)
15ns settling to 0.05%
300V/µs slew rate
■
■
■
■
■
■
■
v
Stable for capacitive loads up to 1000pf
Single 5V or ±5V supplies
The CLC5602 offers 0.1dB gain flatness to 22MHz and differen-
tial gain and phase errors of 0.06% and 0.02°. These features are
ideal for professional and consumer video applications.
Applications
■
Video line driver
The CLC5602 offers superior dynamic performance with a
135MHz small-signal bandwidth, 300V/µs slew rate and 5.7ns
■
ADSL/HDSL driver
■
Coaxial cable driver
rise/fall times (2V
). The combination of low quiescent power,
step
■
UTP differential line driver
high output current drive, and high-speed performance make
the CLC5602 well suited for many battery-powered personal
communication/computing systems.
■
Transformer/coil driver
■
High capacitive load driver
■
Portable/battery-powered applications
■
Differential A/D driver
The ability to drive low-impedance, highly capacitive loads,
makes the CLC5602 ideal for single ended cable applications.
It also drives low impedance loads with minimum distortion.
The CLC5602 will drive a 100Ω load with only -86/-85dBc
Maximum Output Voltage vs. RL
10
second/third harmonic distortion (A = +2, V = 2V , f = 1MHz).
With a 25Ω load, and the same conditions, it produces only -86/
9
8
v
out
pp
VCC = ±5V
-72dBc second/third harmonic distortion.
7
6
5
4
The CLC5602 can also be used for driving differential-input step-
up transformers for applications such as Asynchronous Digital
Subscriber Lines (ADSL) or High-Bit-Rate Digital Subscriber
Lines (HDSL).
3
2
1
Vs = +5V
When driving the input of high-resolution A/D converters, the
CLC5602 provides excellent -87/-95dBc second/third harmonic
10
100
1000
RL (Ω)
distortion (A = +2, V
= 2V , f = 1MHz, R = 1kΩ) and fast
v
out
pp L
settling time.
Typical Application
Differential Line Driver with Load Impedance Conversion
Pinout
DIP & SOIC
Rg2
Rf2
Vo1
+VCC
Vo2
Vd/2
Vin
Rt1
+
V
inv1
non-inv1
-VCC
1/2
Rm/2
Req
Io
-
CLC5602
1:n
-Vd/2
+
Vo
-
1/2
Zo
-
CLC5602
RL
V
V
inv2
Rf1
+
UTP
Rt2
Rm/2
Vnon-inv
2
Rg1
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
(A = +2, R = 750Ω, R = 100Ω,V = +5V1,Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
+5V Electrical Characteristics
v
f
L
s
PARAMETERS
CONDITIONS
TYP
MIN/MAX RATINGS
+25°C 0 to 70°C -40 to 85°C
UNITS
NOTES
Ambient Temperature
CLC5602IN/IM
+25°C
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 0.5Vpp
Vo = 2.0Vpp
Vo = 0.5Vpp
100
65
22
85
60
20
0.5
0.3
0.5
–
75
55
17
0.9
0.4
0.6
–
70
50
15
1.0
0.5
0.6
–
MHz
MHz
MHz
dB
dB
deg
%
-0.1dB bandwidth
gain peaking
gain rolloff
linear phase deviation
differential gain
differential phase
<200MHz, Vo = 0.5Vpp
<30MHz, Vo = 0.5Vpp
<30MHz, Vo = 0.5Vpp
NTSC, RL = 150Ω to -1V
NTSC, RL = 150Ω to -1V
0
0.1
0.3
0.04
0.09
–
–
–
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
2V step
1V step
2V step
2V step
6.1
25
10
8.5
35
20
9.2
50
22
10.0
80
22
ns
ns
%
slew rate
220
190
165
150
V/µs
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; R = 1kΩ
-77
-80
-63
-85
-82
-62
-74
-77
-59
-81
-79
-57
-71
-75
-57
-78
-76
-54
-71
-70
-57
-78
-76
-54
dBc
dBc
dBc
dBc
dBc
dBc
L
2Vpp, 5MHz
2Vpp, 1MHz
3rd harmonic distortion
2Vpp, 1MHz; R = 1kΩ
2Vpp, 5MHz
L
equivalent input noise
voltage (eni)
non-inverting current (ibn)
inverting current (ibi)
crosstalk (input referred)
>1MHz
>1MHz
>1MHz
10MHz, 1Vpp
3.4
6.3
8.7
-72
4.4
8.2
11.3
–
4.9
9.0
12.4
–
4.9
9.0
12.4
–
nV/√Hz
pA/√Hz
pA/√Hz
dB
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
input bias current (inverting)
average drift
power supply rejection ratio
common-mode rejection ratio
supply current per channel
1
7
5
25
3
10
48
49
1.5
4
–
12
–
10
–
45
47
1.7
5
6
mV
µV/˚C
µA
nA/˚C
µA
nA/˚C
dB
dB
A
A
A
15
15
60
12
20
43
45
1.8
15
16
60
13
20
43
45
1.8
DC
DC
RL= ∞
mA
A
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
input voltage range, High
input voltage range, Low
0.46
1.8
4.2
0.8
4.0
1.0
4.1
0.9
100
55
0.36
2.75
4.1
0.9
3.9
1.1
4.0
1.0
80
0.32
2.75
4.1
0.9
3.9
1.1
4.0
1.0
65
0.32
2.75
4.0
1.0
3.8
1.2
3.9
1.1
40
MΩ
pF
V
V
V
V
V
V
mA
mΩ
output voltage range, High
output voltage range, Low
output voltage range, High
output voltage range, Low
output current
RL = 100Ω
RL = 100Ω
RL = ∞
RL = ∞
B
output resistance, closed loop
DC
90
90
120
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes
Absolute Maximum Ratings
A) J-level: spec is 100% tested at +25°C.
B) The short circuit current can exceed the maximum safe
output current.
supply voltage (VCC - VEE
)
+14V
output current (see note C)
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
ESD rating (human body model)
140mA
VEE to VCC
+150°C
1) Vs = VCC - VEE
-65°C to +150°C
+300°C
Reliability Information
1000V
Transistor Count
MTBF (based on limited test data)
98
290Mhr
http://www.national.com
2
(A = +2, R = 750Ω, R = 100Ω, VCC = ±5V, unless specified)
±5V Electrical Characteristics
v
f
L
PARAMETERS
CONDITIONS
TYP
GUARANTEED MIN/MAX
+25°C 0 to 70°C -40 to 85°C
UNITS
NOTES
Ambient Temperature
CLC5602IN/IM
+25°C
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 1.0Vpp
Vo = 4.0Vpp
Vo = 1.0Vpp
135
48
20
115
45
18
0.5
0.3
0.3
0.18
0.04
105
42
15
0.9
0.4
0.4
–
100
40
12
1.0
0.5
0.4
–
MHz
MHz
MHz
dB
dB
deg
%
-0.1dB bandwidth
gain peaking
gain rolloff
linear phase deviation
differential gain
differential phase
<200MHz, Vo = 1.0Vpp
<30MHz, Vo = 1.0Vpp
<30MHz, Vo = 1.0Vpp
NTSC, RL=150Ω
0
0.1
0.15
0.06
0.02
NTSC, RL=150Ω
–
–
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
2V step
2V step
2V step
2V step
5.7
15
18
6.2
25
20
6.8
40
22
7.3
60
22
ns
ns
%
slew rate
300
225
190
175
V/µs
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; R = 1kΩ
-86
-87
-70
-85
-95
-66
-82
-83
-64
-81
-90
-64
-79
-80
-61
-78
-87
-61
-79
-80
-60
-78
-87
-60
dBc
dBc
dBc
dBc
dBc
dBc
L
2Vpp, 5MHz
2Vpp, 1MHz
3rd harmonic distortion
2Vpp, 1MHz; R = 1kΩ
2Vpp, 5MHz
L
equivalent input noise
voltage (eni)
non-inverting current (ibn)
inverting current (ibi)
crosstalk (input referred)
>1MHz
>1MHz
>1MHz
10MHz, 1Vpp
3.4
6.3
8.7
-72
4.4
8.2
11.3
–
4.9
9.0
12.4
–
4.9
9.0
12.4
–
nV/√Hz
pA/√Hz
pA/√Hz
dB
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
input bias current (inverting)
average drift
power supply rejection ratio
common-mode rejection ratio
supply current (per channel)
2
8
5
40
8
20
48
51
1.6
6
–
12
–
24
–
45
49
1.9
7
–
16
–
28
45
43
47
2.0
8
–
17
–
28
45
43
47
2.0
mV
µV/˚C
µA
nA/˚C
µA
nA/˚C
dB
dB
DC
DC
RL= ∞
mA
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
common-mode input range
output voltage range
0.59
1.45
0.47
2.15
0.43
2.15
0.43
2.15
MΩ
pF
V
V
V
±
±
±
4.2
3.8
4.0
±
±
±
4.1
3.6
3.8
±
±
±
4.1
3.6
3.8
±
±
±
4.0
3.5
3.7
RL = 100Ω
RL = ∞
output voltage range
output current
output resistance, closed loop
130
40
100
70
80
70
50
90
mA
mΩ
B
DC
Notes
Ordering Information
B) The short circuit current can exceed the maximum safe
output current.
Model
Temperature Range
Description
CLC5602IN
CLC5602IM
CLC5602IMX
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8-pin PDIP
8-pin SOIC
8-pin SOIC tape & reel
Package Thermal Resistance
Package
θJC
θJA
Plastic (IN)
Surface Mount (IM)
65°C/W
50°C/W
130°C/W
145°C/W
3
http://www.national.com
(A = +2, R = 750Ω, R = 100Ω, V = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
+5V Typical Performance
v
f
L
s
Non-Inverting Frequency Response
Inverting Frequency Response
Frequency Response vs. RL
Vo = 0.5Vpp
Vo = 0.5Vpp
Vo = 0.5Vpp
RL = 1kΩ
Av = +2
Rf = 649Ω
Av = -1
Rf = 649Ω
RL = 100Ω
Gain
Gain
Gain
Av = +1
Rf = 1.0kΩ
Av = -2
Rf = 649Ω
Phase
Phase
Phase
0
0
180
135
90
-90
RL = 25Ω
-90
-180
-270
-360
-450
-180
-270
-360
-450
Av = +5
Av = -5
Rf = 301Ω
Rf = 649Ω
45
Av = +10
Rf = 200Ω
Av = -10
Rf = 500Ω
0
-45
1M
10M
100M
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Frequency Response vs. Vo
Gain Flatness & Linear Phase
Open Loop Transimpedance Gain, Z(s)
0.5
0.4
0.3
0.2
0.1
0
140
120
100
80
225
180
135
90
Phase
Gain
Vo = 0.1Vpp
Gain
Vo = 1Vpp
Vo = 2Vpp
Phase
-0.1
-0.2
-0.3
60
45
40
0
1M
10M
100M
0
10
20
30
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (MHz)
Equivalent Input Noise
Frequency (Hz)
PSRR & CMRR
2nd & 3rd Harmonic Distortion
3.6
12.5
10
60
50
40
30
20
10
0
-30
-40
-50
-60
-70
-80
-90
-100
Vo = 2Vpp
PSRR
CMRR
3.5
3.4
3.3
3.2
3rd
RL = 1kΩ
Inverting Current 8.7pA/√Hz
Non-Inverting Current 7pA/√Hz
Voltage 3.35nV/√Hz
7.5
5
2nd
RL = 1kΩ
3rd
RL = 100Ω
2nd
RL = 100Ω
2.5
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
1M
10M
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
2nd & 3rd Harmonic Distortion, RL = 25Ω
2nd & 3rd Harmonic Distortion, RL = 100Ω
2nd & 3rd Harmonic Distortion, RL = 1kΩ
-20
-30
-40
-50
-60
-70
-80
-90
-40
-50
-50
-60
3rd, 10MHz
3rd, 10MHz
3rd, 10MHz
2nd, 10MHz
-60
-70
2nd, 10MHz
3rd, 1MHz
2nd, 10MHz
3rd, 1MHz
-70
-80
-80
2nd, 1MHz
3rd, 1MHz
-90
-90
2nd, 1MHz
2nd, 1MHz
-100
-100
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
Output Amplitude (Vpp)
Large & Small Signal Pulse Response
Closed Loop Output Resistance
IBI, IBN, VIO vs. Temperature
-1.5
1.0
0.5
0
3
100
VCC = ±5V
Large Signal
VIO
IBI
2
10
1
1
Small Signal
0
-0.5
-1.0
-1.5
-1
-2
-3
IBN
0.1
0.01
10k
100k
1M
10M
100M
-60
-20
20
60
100
140
Time (10ns/div)
Frequency (Hz)
Temperature (°C)
http://www.national.com
4
(A = +2, R = 750Ω, R = 100Ω, VCC = ±5V, unless specified)
±5V Typical Performance
v
f
L
Inverting Frequency Response
Vo = 1.0Vpp
Frequency Response
Frequency Response vs. RL
Vo = 1.0Vpp
Vo = 1.0Vpp
Gain
Av = -2
Av = +2
Rf = 649Ω
RL = 1kΩ
Rf = 649Ω
Gain
Gain
Av = -1
Av = +1
RL = 100Ω
Rf = 649Ω
Rf = 1.0kΩ
Phase
Phase
Phase
180
135
90
0
0
-45
-90
-90
-180
-270
-360
-450
Av = -5
Av = +5
RL = 25Ω
Rf = 649Ω
Rf = 301Ω
45
-135
-180
-225
Av = -10
Rf = 500Ω
Av = +10
Rf = 200Ω
0
-45
1M
10M
100M
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Frequency Response vs. Vo
Gain Flatness & Linear Phase
Small Signal Pulse Response
0.4
0.3
0.2
0.1
0
Vo = 5Vpp
Av = +2
Vo = 1Vpp
Gain
Vo = 0.1Vpp
Vo = 2Vpp
Phase
Av = -2
-0.1
1M
10M
100M
0
5
10
15
20
25
30
Time (10ns/div)
Frequency (Hz)
Frequency (MHz)
Large Signal Pulse Response
Differential Gain & Phase
2nd & 3rd Harmonic Distortion vs. Frequency
0
-0.04
-0.08
-0.12
-0.16
-0.2
0
-30
-40
-50
-60
-70
-80
-90
-100
Vo = 2Vpp
Av = +2
Gain Neg Sync
Gain Pos Sync
-0.04
-0.08
-0.12
-0.16
-0.2
2nd
RL = 100Ω
Phase Neg Sync
2nd
RL = 1kΩ
Phase Pos Sync
3rd
RL = 100Ω
3rd
RL = 1kΩ
Av = -2
Time (20ns/div)
1
2
3
4
1
10
Number of 150 Ω Loads
Frequency (MHz)
2nd & 3rd Harmonic Distortion, RL = 1kΩ
2nd & 3rd Harmonic Distortion, RL = 25Ω
2nd & 3rd Harmonic Distortion, RL = 100Ω
-50
-60
-30
-40
-50
-60
-70
-80
-90
-100
-40
-50
3rd, 10MHz
3rd, 10MHz
3rd, 10MHz
2nd, 10MHz
-60
-70
2nd, 10MHz
3rd, 1MHz
-70
2nd, 10MHz
3rd, 1MHz
-80
2nd, 1MHz
3rd, 1MHz
-80
-90
-90
2nd, 1MHz
-100
-110
-100
-110
2nd, 1MHz
0
1
2
3
4
5
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
Short Term Settling Time
Long Term Settling Time
IBI, IBN, VOS vs. Temperature
0.2
0.15
0.1
1.4
1.3
1.2
1.1
1
3
0.2
0.15
0.1
2
IBI
1
0.05
0
0.05
0
0
VOS
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
-0.2
-1
-2
-3
IBN
0.9
0.8
1
10
100
1000
10000
1µ
10
µ
100
µ
1m
10m
100m
-60
-20
20
60
100
140
Time (ns)
Time (s)
Temperature (°C)
5
http://www.national.com
(A = +2, R = 750Ω, R = 100Ω, VCC = ±5V, unless specified)
±5V Typical Channel Matching Performance
v
f
L
Channel Matching
Input Referred Crosstalk
Pulse Crosstalk
-20
-30
-40
-50
-60
-70
-80
-90
Vo = 1Vpp
Active Output
Channel
Inactive Output
Channel
Channel 2
Channel 1
1M
10M
100M
1M
10M
100M
Time (10ns/div)
Frequency (Hz)
Frequency (Hz)
CLC5602 OPERATION
The CLC5602 is a current feedback amplifier built in an
advanced complementary bipolar process. The CLC5602
operates from a single 5V supply or dual ±5V supplies.
Operating from a single supply, the CLC5602 has the
following features:
V
A
o
v
R
=
Equation 1
V
f
in
1+
Z(jω)
where:
■
■
■
A is the closed loop DC voltage gain
v
■
Provides 100mA of output current while
consuming 7.5mW of power
Offers low -80/-82dB 2nd and 3rd harmonic
R is the feedback resistor
f
■
Z(jω) is the CLC5602’s open loop
distortion
transimpedance gain
■
Provides BW > 60MHz and 1MHz distortion
Z jω
(
)
is the loop gain
■
< -65dBc at V = 2.0V
o
pp
R
f
The CLC5602 performance is further enhanced in ±5V
supply applications as indicated in the ±5V Electrical
Characteristics table and ±5V Typical Performance plots.
The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency, the
interaction between R and Z(jω) dominates the circuit
f
Current Feedback Amplifiers
performance. The value of the feedback resistor has a
Some of the key features of current feedback technology
are:
large affect on the circuits performance. Increasing R
has the following affects:
f
■
Independence of AC bandwidth and voltage gain
Inherently stable at unity gain
Adjustable frequency response with feedback resistor
High slew rate
■
Decreases loop gain
■
■
Decreases bandwidth
■
■
Reduces gain peaking
■
■
Lowers pulse response overshoot
■
Fast settling
■
Affects frequency response phase linearity
Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.
Refer to the Feedback Resistor Selection section for
more details on selecting a feedback resistor value.
CLC5602 DESIGN INFORMATION
Single Supply Operation (V = +5V, V = GND)
+4.2V. The typical output range with R =100Ω is +1.0V
CC
EE
L
The specifications given in the +5V Electrical Character-
istics table for single supply operation are measured with
to +4.0V.
For single supply DC coupled operation, keep input
signal levels above 0.8V DC. For input signals that drop
below 0.8V DC, AC coupling and level shifting the signal
are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in
the following 2 sections.
a common mode voltage (V ) of 2.5V. V is the volt-
cm
cm
age around which the inputs are applied and the
output voltages are specified.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5602 is typically +0.8V to
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6
VCC
DC Coupled Single Supply Operation
Figures 1 and 2 show the recommended non-inverting
and inverting configurations for input signals that remain
above 0.8V DC.
6.8µF
+
VCC
2
R
R
0.1µF
8
3
2
+
VCC
1/2
1
Vo
Note: Rt, RL and Rg are tied
CLC5602
Cc
6.8µF
Rg
to Vcm for minimum power
Vin
+
-
consumption and maximum
output swing.
4
Rf
0.1µF
8
3
2
Vin
+
1/2
1
Vo
RL
Vcm
R
f
CLC5602
V
= V
−
+ 2.5
o
in
Rt
R
g
-
4
Rf
1
low frequency cutoff =
2πR C
g
c
Vcm
Rg
R
R
V
o
f
Figure 4: AC Coupled Inverting Configuration
Dual Supply Operation
= A = 1+
v
V
Vcm
g
in
Figure 1: Non-Inverting Configuration
The CLC5602 operates on dual supplies as well as
single supplies. The non-inverting and inverting configu-
rations are shown in Figures 5 and 6.
VCC
Note: Rb, provides DC bias
for non-inverting input.
6.8µF
VCC
+
Rb, RL and Rt are tied
to Vcm for minimum power
consumption and maximum
output swing.
6.8µF
+
0.1µF
8
3
+
1/2
0.1µF
1
Vo
RL
Vcm
8
Vin
3
2
+
CLC5602
Rb
2
1/2
1
Vo
-
CLC5602
Rt
4
Vcm
Rt
Vcm
Rg
Rf
-
Vin
4
Rf
R
V
o
f
= A = 1+
v
0.1µF
Rg
V
R
g
in
R
V
Select Rt to yield
desired Rin = Rt || Rg
o
f
= A = −
v
+
V
R
g
in
6.8µF
VEE
Figure 2: Inverting Configuration
AC Coupled Single Supply Operation
Figure 5: Dual Supply Non-Inverting Configuration
Figures 3 and 4 show possible non-inverting and invert-
ing configurations for input signals that go below 0.8V
DC. The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
VCC
6.8µF
+
voltage divider biases the non-inverting input to V ÷ 2
CC
0.1µF
= 2.5V (For V = +5V).
Rb
Rg
8
3
2
CC
+
1/2
1
Vo
VCC
CLC5602
6.8µF
-
+
4
Rf
Vin
Rt
Note: Rb provides DC bias
for the non-inverting input.
R
Select Rt to yield desired
Rin = Rt || Rg.
0.1µF
Cc
0.1µF
8
3
2
Vin
+
1/2
1
Vo
+
CLC5602
VCC
2
Rf
Vo
R
6.8µF
-
= Av = −
4
Rf
V
Rg
in
VEE
Rg
C
Figure 6: Dual Supply Inverting Configuration
R
f
V
= V 1+
+ 2.5
o
in
R
g
1
R
low frequency cutoff =
, where: R
=
R >> R
source
in
2πR C
2
c
in
Figure 3: AC Coupled Non-Inverting Configuration
7
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Feedback Resistor Selection
Figure 8 shows typical inverting and non-inverting circuit
configurations for matching transmission lines.
The feedback resistor, R , affects the loop gain and
f
frequency response of a current feedback amplifier.
Optimum performance of the CLC5602, at a gain of
Non-inverting gain applications:
+2V/V, is achieved with R equal to 750Ω. The frequency
response plots in the Typical Performance sections
f
■
Connect R directly to ground.
g
■
■
Make R , R , R , and R equal to Z .
1
2
6
7
o
illustrate the recommended R for several gains. These
f
Use R to isolate the amplifier from reactive
3
recommended values of R provide the maximum band-
f
loading caused by the transmission line,
or by parasitics.
width with minimal peaking. Within limits, R can be
f
adjusted to optimize the frequency response.
■
C6
Decrease R to peak frequency response and
extend bandwidth
Z0
f
R1
R3
R2
Rg
R5
+
Z0
1/2
Vo
R7
+
-
CLC5602
V1
V2
R6
■
Increase R to roll off frequency response and
-
f
Z0
compress bandwidth
Rf
R4
+
-
As a rule of thumb, if the recommended R is doubled,
f
then the bandwidth will be cut in half.
Unity Gain Operation
Figure 8:Transmission Line Matching
The recommended R for unity gain (+1V/V) operation
f
is 1kΩ. R is left open. Parasitic capacitance at the
Inverting gain applications:
g
inverting node may require a slight increase in R to
maintain a flat frequency response.
f
■
Connect R directly to ground.
3
■
■
Make the resistors R , R , and R equal to Z .
4
6
7
o
Make R II R = Z .
Load Termination
5
g
o
The CLC5602 can source and sink near equal amounts
of current. For optimum performance, the load should be
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
tied to V
.
cm
Use C to match the output transmission line over a
6
greater frequency range. C compensates for the increase
of the amplifier’s output impedance with frequency.
Driving Cables and Capacitive Loads
6
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC5602 will
improve stability and settling performance. The
Power Dissipation
Follow these steps to determine the power consumption
of the CLC5602:
Frequency Response vs. C plot, shown below in
L
Figure 7, gives the recommended series resistance value
for optimum flatness at various capacitive loads.
1. Calculate the quiescent (no-load) power:
P
= I (V - V
)
amp
CC
CC
EE
2. Calculate the RMS power at the output stage:
P = (V - V ) (I ), where V and I
load
o
CC
load
load
load
Vo = 1Vpp
are the RMS voltage and current across the
external load.
CL = 10pF
Rs = 46.4Ω
CL = 100pF
Rs = 20Ω
3. Calculate the total RMS power:
P = P
+ P
CL = 1000pF
Rs = 6.7Ω
t
amp
o
+
The maximum power that the DIP and SOIC packages
can dissipate at a given temperature is illustrated in
Figure 9. The power derating curve for any CLC5602
package can be derived by utilizing the following
equation:
Rs
-
CL
1k
1k
1k
1M
10M
100M
Frequency (Hz)
(175° − T
)
amb
θ
Figure 7: Frequency Response vs. C
JA
L
where
Transmission Line Matching
One method for matching the characteristic impedance
T
= Ambient temperature (°C)
amb
θ
= Thermal resistance, from junction to ambient,
for a given package (°C/W)
(Z ) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
JA
o
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8
1.0
0.8
0.6
0.4
0.2
0
■
■
Support Berkeley SPICE 2G and its many derivatives
IN
IM
Reproduce typical DC, AC, Transient, and Noise
performance
■
Support room temperature simulations
The readme file that accompanies the diskette lists
released models, and provides a list of modeled parame-
ters. The application note OA-18, Simulation SPICE
Models for National’s Op Amps, contains schematics and
a reproduction of the readme file.
-40 -20
0
20 40 60 80 100 120 140 160 180
Ambient Temperature (°C)
Figure 9: Power Derating Curves
Application Circuits
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC5602 (CLC730038-DIP,
CLC730036-SOIC) and suggests their use as a guide for
high frequency layout and as an aid for device testing and
characterization.
Single Supply Cable Driver
The typical application shown below shows one of the
CLC5602 amplifiers driving 10m of 75Ω coaxial cable.
The CLC5602 is set for a gain of +2V/V to compensate
for the divide-by-two voltage drop at V .
o
+5V
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
6.8µF
+
5kΩ
0.1µF
10m of 75Ω
0.1µF
8
■
Vin
3
Include 6.8µF tantalum and 0.1µF ceramic
+
Coaxial Cable
75Ω
1/2
CLC5602
1
Vo
75Ω
capacitors on both supplies.
5kΩ
2
-
0.1µF
■
Place the 6.8µF capacitors within 0.75 inches
4
1kΩ
of the power pins.
1kΩ
■
Place the 0.1µF capacitors less than 0.1 inches
from the power pins.
0.1µF
■
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
Figure 10: Single Supply Cable Driver
■
Minimize all trace lengths to reduce series
inductances.
Vin = 10MHz, 0.5Vpp
■
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
Evaluation Board Information
A data sheet is available for the CLC730038/ CLC730036
evaluation boards. The evaluation board data sheet
provides:
■
Evaluation board schematics
20ns/div
■
Evaluation board layouts
■
General information about the boards
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
Figure 11: Response After 10m of Cable
Single Supply Lowpass Filter
Figures 12 and 13 illustrate a lowpass filter and design
equations. The circuit operates from a single supply of
+5V. The voltage divider biases the non-inverting input to
2.5V. And the input is AC coupled to prevent the need for
level shifting the input signal at the source. Use the
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:
design equations to determine R , R , C , and C based
1
2
1
2
on the desired Q and corner frequency.
9
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+5V
8
Differential Line Driver With Load
Impedance Conversion
0.1µF
The circuit shown in the Typical Application schematic
on the front page and in Figure 15, operates as a
differential line driver. The transformer converts the load
impedance to a value that best matches the CLC5602’s
output capabilites. The single-ended input signal is
converted to a differential signal by the CLC5602. The
line’s characteristic impedance is matched at both the
input and the output. The schematic shows Unshielded
Twisted Pair for the transmission line; other types of lines
can also be driven.
5kΩ
0.1µF
C1
1
R1
R2
3
2
Vin
+
0.1µF
1/2
CLC5602
Vo
100Ω
158Ω 158Ω
-
5kΩ
C2
4
Rf
100pF
1kΩ
1.698kΩ Rg
0.1µF
Figure 12: Lowpass Filter Topology
Rg2
Rf2
Vd/2
Vin
Rt1
R
+
1/2
CLC5602
f
Gain = K = 1+
Rm/2
Req
Io
-
1:n
-Vd/2
+
Vo
-
1/2
Zo
R
-
g
CLC5602
RL
Rf1
+
UTP
1
Rt2
Rm/2
Corner frequency = ω =
Rg1
c
R R C C
1 2
1 2
1
Q =
Figure 15: Differential Line Driver wtih
Load Impedance Conversion
R C
R C
R C
1 1
2
2
1
2
+
+ (1−K)
R C
R C
R C
2 2
1 1
2
1
Set up the CLC5602 as a difference amplifier:
For R = R = R and C = C = C
1
2
1
2
V
R
R
R
R
1
d
f1
f2
= 2 1+
= 2
ω =
c
V
RC
1
in
g1
g2
Q =
Make the best use of the CLC5602’s output drive
capability as follows:
(3 − K)
2 V
max
Figure 13: Design Equations
R
+R
=
eq
m
I
max
This example illustrates a lowpass filter with Q = 0.707
where R is the transformed value of the load imped-
and corner frequency f = 10MHz. A Q of 0.707 was
eq
c
ance, V
is the Output Voltage Range, and I
is the
chosen to achieve a maximally flat, Butterworth
response. Figure 14 indicates the filter response.
max
max
maximum Output Current.
Match the line’s characteristic impedance:
3
-3
-9
R = Z
L
o
R
= R
eq
m
R
L
n =
R
eq
Select the transformer so that it loads the line with a
-15
-21
value very near Z over frequency range. The output
o
impedance of the CLC5602 also affects the match. With
an ideal transformer we obtain:
1M
10M
100M
Frequency (Hz)
2
n
Z
jω
o 5602
(
)
(
)
Figure 14: Lowpass Response
ReturnLoss = −20 log
,dB
10
Z
o
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10
where Z
(jω) is the output impedance of the
The receiver output voltages are:
o(5602)
CLC5602 and |Z
(jω)| << R .
m
o(5602)
V
Z
(jω)
o(5602)
R
inB(A)
f2
V
≈ V
A +
1−
+
outA(B)
inA(B)
The load voltage and current will fall in the ranges:
≤ n V
2
R
R
m1
g2
V
o
max
where A is the attenuation of the cable, Z
output impedance of the CLC5602 (see the Closed-Loop
Output Resistance plot), and |Z (jω)| << R
(jω) is the
o(5602)
I
max
I
≤
o
n
.
m1
o(5602)
The CLC5602’s high output drive current and low
distortion make it a good choice for this application.
We selected the component values as follows:
■
R = 1.0kΩ, the recommended value for the
f1
Full Duplex Cable Driver
CLC5602 at unity gain
The circuit shown in Figure 16 below, operates as a full
duplex cable driver which allows simultaneous transmis-
sion and reception of signals on one transmission line.
The circuit on either side of the transmission line uses are
CLC5602 as a cable driver, and the second CLC5602 as
■
■
R
= Z = 50Ω, the characteristic impedance
o
m1
of the transmission line
R = R = 750Ω ≥ R , the recommended
f2
g2
m1
value for the CLC5602 at A = 2
v
R
a receiver. V is an attenuated version of Vi , while V
m1
oA
nA
oB
■
R
= (R ||R ) –
= 25Ω
t2
f2
g2
2
is an attenuated version of V
.
inB
These values give excellent isolation from the other input:
VinA
Rt1
VinB
+
+
Z0
Rm1
Rm1
1/2
1/2
V
CLC5602
CLC5602
oA(B)
Rt1
-
-
≈ −38dB, f = 5.0MHz
V
inB(A)
Rf1
Rf2
Rf1
Rf2
Rg2
Rg2
The CLC5602 provides large output current drive, while
consuming little supply current, at the nominal bias point.
It also produces low distortion with large signal swings
and heavy loads. These features make the CLC5602 an
excellent choice for driving transmission lines.
-
-
1/2
CLC5602
1/2
VoB
VoA
CLC5602
Rt2
Rt2
+
+
Figure 16: Full Duplex Cable Driver
is used to match the transmission line. R and R
g2
R
m1
f2
set the DC gain of the CLC5602, which is used in a
difference mode. R provides good CMRR and DC
t2
offset. The transmitting CLC5602’s are shown in a unity
gain configuration because they consume the least
power of any gain, for a given load. For proper operation
we need R = R .
f2
g2
11
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