CLC5802 [NSC]
Dual Low-Noise, Voltage Feedback Op Amp; 双路低噪声，电压反馈运算放大器
| 型号： | CLC5802 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual Low-Noise, Voltage Feedback Op Amp |
| 文件： | 总12页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2000
CLC5802
Dual Low-Noise, Voltage Feedback Op Amp
General Description
Features
±
The CLC5802 is a dual op amp that offers a traditional
voltage-feedback topology featuring unity-gain stability. Low
noise and very low harmonic distortion combine to form a
very wide dynamic-range op amp that operates within a
power supply range of 5V to 12V.
(TA = 25˚C, VS
=
5V, RL = 100Ω, Typical unless specified).
n Wide unity-gain bandwidth: 140MHz
n Ultra-low noise: 4nV/ , 2pA/
n Low distortion: −69/−66dBc (5MHz)
n Settling time: 18ns to 0.1%
n High output current: 70mA
n Supply voltage range: 5V to 12V
Each of the CLC5802’s closely matched channels provides a
140MHz unity-gain bandwidth with a very low input voltage
±
noise density (4nV/
). Low 2nd/3rd harmonic distortion
(−69/−66dBc) as well as high channel-to-channel isolation
(−61dB) make the CLC5802 a perfect wide dynamic-range
amplifier for I/Q channels and other application which require
low distortion and matching. With its fast and accurate set-
tling (18ns to 0.1%), the CLC5802 is also a excellent choice
for wide-dynamic range, anti-aliasing filters to buffer the in-
puts of hi-resolution analog-to-digital converters. Combining
the CLC5802 two tightly-matched amplifiers in a single
eight-pin SOIC reduces cost and board space for many com-
posite amplifier applications such as active filters, differential
line drivers/receivers, fast peak detectors and instrumenta-
tion amplifiers.
Applications
n General purpose dual op amp
n Low noise active filters
n Low noise integrators
n High-speed detectors
n Diff-in/diff-out instrumentation amp
n I/Q channel amplifiers
n Driver/receiver for transmission systems
Equivalent Input Noise
DS101341-16
Typical Application
Full Duplex Transmission
DS101341-28
© 2000 National Semiconductor Corporation
DS101341
www.national.com
Connection Diagram
8-Pin SOIC
DS101341-2
Top View
Ordering Information
Package
Part Number
Packaging
Marking
Transport Media
NSC
Drawing
M08A
8-pin SOIC
CLC5802IM
CLC5802IM
CLC5802IM
Rails
CLC5802IMX
2.5k Tape and Reel
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
−65˚C to +150˚C
+300˚C
Lead Temperature (soldering 10 sec)
Operating Rating(Note 1)
±
Supply Voltage
7V
Thermal Resistance (θJC
)
40˚C/W
115˚C/W
Short Circuit Current
(Note 3)
Thermal Resistance (θJA
Temperature Range
)
±
±
Common-Mode Input Voltage
Differential Input Voltage
Maximum Junction Temperature
VCC
10V
−40˚C to +85˚C
5V to 12V
Supply Voltage Range
+125˚C
Electrical Characteristics
±
5V, AV = +2V/V, Rf = 100Ω, Rg = 100Ω, RL= 100Ω; unless specified).
(TA = +25˚C, VCC
=
Symbol
Parameter
Conditions
Typ
Min/Max Ratings
Units
(Note 2)
+25˚C +25˚C
0˚C to
+70˚C
−40˚C
to
+85˚C
Frequency Domain Response
<
GBW
Gain Bandwidth Product
−3dB Bandwidth (AV = +1)
−3dB Bandwidth (AV = +2)
−3dB Bandwidth
VOUT 0.5VPP
120
140
75
90
110
50
<
VOUT 0.5VPP
SSBW
MHz
<
VOUT 0.5VPP
<
LSBW
GFP
VOUT 5.0VPP
40
25
<
Gain Flatness Peaking
DC to 200MHz, VOUT 0.5
0.0
0.6
dB
dB
VPP
<
GFR
LPD
Gain Flatness Rolloff
DC to 20MHz, VOUT 0.5
VPP
0.05
0.2
0.5
1.0
Linear Phase Deviation
DC to 20MHz
Deg
Time Domain Response
TRS
TSS
OS
Rise and Fall Time
Settling Time
Overshoot
1V step
6
18
1
8
22
5
ns
ns
2V step to 0.1%
1V step
%
SR
Slew Rate
5V step
450
275
V/µs
Distortion And Noise Response
HD2
HD3
VN
2nd Harmonic Distortion
3rd Harmonic Distortion
1VPP, 5MHz
−69
−66
4.0
−57
−54
4.5
dBc
dBc
nV/
1VPP, 5MHz
Equivalent Input Noise Voltage
1MHz to 100MHz
ICN
CT
Equivalent Input Noise Current
Crosstalk
1MHz to 100MHz
2.0
3.0
pA/
dB
Input referred, 10MHz
DC
−61
60
−58
56
Static, DC Performance
AOL
VIO
Open-Loop Gain
50
50
dB
mV
±
±
±
±
3.5
Input Offset Voltage (Note 4)
Offset Voltage Average Drift
Input Bias Current (Note 4)
Bias Current Average Drift
Input Offset Current
1.0
5
2.0
–
3.0
DVIO
IB
15
40
600
5
20
65
700
5
µV/˚C
µA
1.5
25
–
DIB
150
0.3
5
nA/˚C
µA
IIO
3
DIIO
PSRR
CMRR
ICC
Offset Current Average Drift
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Supply Current (Note 4)
–
25
55
52
13
50
55
52
15
nA/˚C
dB
DC
DC
63
60
11
57
54
12
dB
∞
Per Channel, RL
=
mA
3
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Electrical Characteristics (Continued)
±
5V, AV = +2V/V, Rf = 100Ω, Rg = 100Ω, RL= 100Ω; unless specified).
(TA = +25˚C, VCC
=
Symbol
Parameter
Conditions
Typ
Min/Max Ratings
Units
(Note 2)
+25˚C +25˚C
0˚C to
+70˚C
−40˚C
to
+85˚C
Miscellaneous Performance
RINC
RIND
CINC
CIND
ROUT
VO
Input Resistance
Common-Mode
500
200
2.0
250
50
125
25
125
25
kΩ
kΩ
pF
pF
Ω
Differential-Mode
Common-Mode
Differential-Mode
Closed Loop
∞
Input Capacitance
3.0
3.0
0.1
3.0
3.0
0.2
3.0
3.0
0.2
3.3
2.0
Output Resistance
0.05
±
±
±
±
Output Voltage Range
RL
=
3.6
3.5
3.3
V
±
±
±
±
±
±
VOL
CMIR
IO
RL = 100Ω
3.4
3.7
3.2
3.5
2.6
3.3
1.3
3.3
V
±
±
Input Voltage Range
Output Current
Common-Mode
V
±
±
±
±
20
70
50
40
mA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Operating Ratings indicate conditions for which
the device is intended to be functional, but specific performance is not guaranteed,
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 160mA.
Note 4: 100% tested at +25˚C.
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4
±
5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω,
Typical Performance Characteristics (TA = 25˚C, VCC
=
unless otherwise specified).
Non-Inverting Frequency Response
Inverting Frequency Response
DS101341-3
DS101341-4
Frequency Response vs. Load Resistance
Frequency Response vs. Output Amplitude
DS101341-5
DS101341-6
Frequency Response vs. Capacitive Load
Gain Flatness & Linear Phase Deviation
DS101341-8
DS101341-7
5
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±
5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω,
Typical Performance Characteristics (TA = 25˚C, VCC
=
unless otherwise specified).. (Continued)
Maximum Output Voltage vs. Load
Channel-to-Channel Crosstalk
DS101341-9
DS101341-10
Open-Loop Gain & Phase
2nd and 3rd Harmonic Distortion
DS101341-11
DS101341-12
2nd Harmonic Distortion vs. Output Voltage
3rd Harmonic Distortion vs. Output Voltage
DS101341-13
DS101341-14
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6
±
5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω,
Typical Performance Characteristics (TA = 25˚C, VCC
=
unless otherwise specified).. (Continued)
Closed-Loop Output Resistance
Equivalent Input Noise
DS101341-16
DS101341-15
2-Tone, 3rd order Intermodulation Intercept
Pulse Response (VOUT = 100mV)
DS101341-18
DS101341-17
Pulse Response (VOUT = 2V)
Settling Time vs. Capacitive Load
DS101341-19
DS101341-20
7
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±
Typical Performance Characteristics (TA = 25˚C, VCC
=
5V, Rg = 26.1Ω, Rf = 499Ω, RL = 100Ω,
unless otherwise specified).. (Continued)
Short-Term Settling Time
CMRR and PSRR
DS101341-21
DS101341-22
Typical DC Errors vs. Temperature
Output Voltage vs. Output Sourcing Current
DS101341-23
DS101341-37
Output Voltage vs. Output Sinking Current
DS101341-38
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8
Application Information
Low Noise Design
(B1). If the coax cable is lossless and Rf equals Rg, receiver
A2 (B2) will then reject the signals from driver A1 (B1) and
pass the signals from driver B1 (A1).
Ultimate low noise performance from circuit designs using
the CLC5802 requires the proper selection of external resis-
tors. By selecting appropriate low-valued resistors for Rf and
Rg, amplifier circuits using the CLC5802 can achieve output
noise that is approximately the equivalent voltage input
noise of 4nV/
multiplied by the desired gain (AV).
Each amplifier in the CLC5802 has an equivalent input noise
resistance which is optimum for matching source imped-
ances of approximately 2k. Using a transformer, any source
can be matched to achieve the lowest noise design.
For even lower noise performance than the CLC5802, con-
sider the CLC425, CLC426 or CLC5801 at 1.05, 1.6 and
DS101341-28
FIGURE 1.
2nV/
, respectively.
DC Bias Currents and Offset Voltages
The output of the receiver amplifier will be:
Cancellation of the output offset voltage due to input bias
currents is possible with the CLC5802. This is done by mak-
ing the resistance seen from the inverting and non-inverting
inputs equal. Once done, the residual output offset voltage
will be the input offset voltage (VOS) multiplied by the desired
gain (AV). Application Note OA-7 offers several solutions to
further reduce the output offset.
(1)
Care must be given to layout and component placement to
maintain a high frequency common-mode rejection. The plot
of Figure 2 show the simultaneous reception of signals trans-
mitted at 1MHz and 10MHz.
Output and Supply Considerations
±
With 5V supplies, the CLC5802 is capable of a typical out-
±
put swing of 3.6V under a no-load condition. Additional out-
put swing is possible with slightly higher supply voltages. For
loads of less than 50Ω, the output swing will be limited by the
CLC5802’s output current capability, typically 70mA.
Output settling time when driving capacitive loads can be im-
proved by the use of a series output resistor. See the plot la-
beled “Settling Time vs. Capacitive Load” in the Typical Per-
formance Characteristics section.
Layout
Proper power supply bypassing is critical to insure good high
frequency performance and low noise. De-coupling capaci-
tors of 0.1µF should be placed as close as possible to the
power supply pins. The use of surface mounted capacitors is
recommended due to their low series inductance.
DS101341-25
A good high frequency layout will keep power supply and
ground traces away from the inverting input and output pins.
Parasitic capacitance from these nodes to ground causes
frequency response peaking and possible circuit oscillation.
See OA-15 for more information. National suggests the
CLC730038 (through-hole) or the CLC730036 (SOIC) dual
op amp evaluation board as a guide for high frequency lay-
out and as an aid in device evaluation.
FIGURE 2.
Five Decade Integrator
A composite integrator, shown in Figure 3, uses the
CLC5802 dual op amp to increase the circuits usable fre-
quency range of operation. The transfer function of this cir-
cuit is:
Full Duplex Digital or Analog Transmission
(2)
Simultaneous transmission and reception of analog or digital
signals over a single coaxial cable or twisted-pair line can re-
duce cabling requirements. The CLC5802’s wide bandwidth
and high common-mode rejection in a differential amplifier
configuration allows full duplex transmission of video, tele-
phone, control and audio signals.
In the circuit shown in Figure 1, one of the CLC5802’s amps
is used as a “driver” and the other as a difference “receiver”
amplifier. The output impedance of the “driver” is essentially
zero. The two R’s are chosen to match the characteristic im-
pedance of the transmission line. The “driver” op amp gain
can be selected for unity or greater.
DS101341-27
FIGURE 3.
Receiver amplifier A2 (B2) is connected across R and forms
a differential amplifier for the signals transmitted by driver A1
9
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Application Information (Continued)
A resistive divider made from the 143Ω and 60.4Ω resistors
was chosen to reduce the loop-gain and stabilize the net-
work. The CLC5802 composite integrator provides integra-
tion over five decades of operation. R and C set the integra-
tor’s gain. Figure
4 shows the frequency and phase
response of the circuit in Figure 3 with R = 44.2Ω and C =
360pF.
DS101341-31
FIGURE 6.
A current source, built around Q1, provides the necessary
bias current for the second amplifier and prevents saturation
when power is applied. The resistor, R, closes the loop while
diode D2 prevents negative saturation when VIN is less than
VC. A MOS-type switch (not shown) can be used to reset the
capacitor’s voltage.
DS101341-29
The maximum speed of detection is limited by the delay of
the op amp and the diodes. The use of Schottky diodes will
provide faster response.
FIGURE 4.
K: R2/(R1 + R2)
Adjustable or Bandpass Equalizer
A0: Op amp low Frequency open loop gain
Positive Peak Detector
A “boost” equalizer can be made with the CLC5802 by sum-
ming a bandpass response with the input signal, as shown in
Figure 7.
The CLC5802’s dual amplifiers can be used to implement a
unity-gain peak detector circuit as shown in Figure 5.
DS101341-32
FIGURE 7.
The overall transfer function is shown in Equation (3).
DS101341-30
FIGURE 5.
(3)
The acquisition speed of this circuit is limited by the dynamic
resistance of the diode when charging Chold. A plot of the cir-
cuit’s performance is shown in Figure 6 with a 1MHz sinusoi-
dal input.
To build a boost circuit, use the design Equation 4 and 5.
(4)
(5)
Select R2 and C using Equation (4). Use reasonable values
for high frequency circuits - R2 between 10Ω and 5kΩ, C be-
tween 10pF and 2000pF. Use Equation (5) to determine the
parallel combination of Ra and Rb. Select Ra and Rb by ei-
ther the 10Ω to 5kΩ criteria or by other requirements based
on the impedance VIN is capable of driving. Finish the design
by determining the value of K from Equation (6).
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10
Application Information (Continued)
(6)
Figure 8 shows an example of the response of the circuit of
Figure 7, where fO is 2.3MHz. The component values are as
follows: Ra = 2.1kΩ, Rb = 68.5Ω, R2 = 4.22kΩ, R = 500Ω,
KR = 50Ω, C = 120pF.
DS101341-36
FIGURE 8.
11
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
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