COP244C-XXX/N [NSC]
Single-Chip 1k and 2k CMOS Microcontrollers; 单芯片1K和2K CMOS微控制器
| 型号： | COP244C-XXX/N |
| 厂家： | 
National Semiconductor |
| 描述： | Single-Chip 1k and 2k CMOS Microcontrollers |
| 文件： | 总24页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1992
COP224C/COP225C/COP226C/COP244C/COP245C
Single-Chip 1k and 2k CMOS Microcontrollers
General Description
Features
Y
Lowest power dissipation (600 mW typical)
The COP224C, COP225C, COP226C, COP244C and
COP245C fully static, Single-Chip CMOS Microcontrollers
are members of the COPSTM family, fabricated using dou-
ble-poly, silicon gate microCMOS technology. These Con-
troller Oriented Processors are complete microcomputers
containing all system timing, internal logic, ROM, RAM, and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include single supply oper-
ation, a variety of output configuration options, with an in-
struction set, internal architecture and I/O scheme de-
signed to facilitate keyboard input, display output and BCD
data manipulation. The COP224C and COP244C are 28 pin
chips. The COP225C and COP245C are 24-pin versions (4
inputs removed) and COP226C is 20-pin version with 15 I/O
lines. Standard test procedures and reliable high-density
techniques provide the medium to large volume customers
with a customized microcontroller at a low end-product cost.
These microcontrollers are appropriate choices in many de-
manding control environments especially those with human
interface.
Y
Fully static (can turn off the clock)
Y
Power saving IDLE state and HALT mode
Y
4.4 ms instruction time
Y
2k x 8 ROM, 128 x 4 RAM (COP244C/COP245C)
Y
1k x 8 ROM, 64 x 4 RAM (COP224C/COP225C/
COP226C)
Y
Y
Y
Y
Y
Y
23 I/O lines (COP244C and COP224C)
True vectored interrupt, plus restart
Three-level subroutine stack
Single supply operation (4.5V to 5.5V)
Programmable read/write 8-bit timer/event counter
Internal binary counter register with MICROWIRETM
serial I/O capability
Y
Y
Y
Y
General purpose and TRI-STATE outputs
É
LSTTL/CMOS output compatible
Software/hardware compatible with COP400 family
b
a
Military temperature ( 55 C to 125 C) operation
§
§
COPSTM, MicrobusTM, and MICROWIRETM are trademarks of National Semiconductor Corp.
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
Block Diagram
FIGURE 1
C
1995 National Semiconductor Corporation
TL/DD/8422
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
b
a
55 C to 125 C
Operating Temperature Range
Storage Temperature Range
Lead Temperature
§
§
a
65 C to 150 C
§
§
Supply Voltage (V
)
6V
CC
(soldering, 10 seconds)
300 C
§
b
a
0.3V
Voltage at any Pin
0.3V to V
CC
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
Total Allowable Source Current
Total Allowable Sink Current
Total Allowable Power Dissipation
25 mA
25 mA
150 mW
s
s
s
s
a
V
CC
b
DC Electrical Characteristics 55 C
a
a
125 C, 4.5V
T
A
5.5V unless otherwise specified
§
§
Parameter
Conditions
Min
Max
Units
Operating Voltage
4.5
5.5
V
V
Power Supply Ripple (Notes 4, 5)
Peak to Peak
0.25 V
CC
e
(tc is instruction cycle time)
e
Supply Current
(Note 1)
V
5.0V, tc 4.4 ms
CC
5
mA
e
e
0 kHz
HALT Mode Current (Note 2)
Input Voltage Levels
V
CC
5.0V, F
IN
200
mA
RESET, CKI, D (clock input)
0
Logic High
Logic Low
0.9 V
0.7 V
V
V
CC
0.1 V
0.2 V
CC
All Other Inputs
Logic High
V
V
CC
Logic Low
CC
b
a
10
Hi-Z Input Leakage
10
mA
Input Capacitance (Note 4)
7
pF
Output Voltage Levels (except CKO)
LSTTL Operation
Logic High
Standard Outputs
e
g
5.0V 10%
V
CC
eb
I
I
100 mA
2.7
V
V
OH
e
Logic Low
400 mA
0.6
0.2
OL
CMOS Operation
Logic High
eb
b
0.2
I
I
10 mA
V
V
V
OH
CC
e
Logic Low
10 mA
OL
CKO Current Levels (As Clock Out)
d
d
d
d
d
d
Sink
4
0.2
0.4
0.8
mA
mA
mA
mA
mA
mA
e
e
8
CKI
V
, V
CC OUT
V
CC
16
4
(
(
b
Source
0.2
e
CKI 0V, V
e
b
b
8
0V
0.4
0.8
OUT
16
Allowable Sink/Source Current per Pin
(Note 6)
5
mA
Allowable Loading on CKO (as HALT)
50
pF
Current Needed to Over-Ride HALT
(Note 3)
To Continue
To Halt
e
e
V
V
0.2 V
0.7 V
2.0
3.0
mA
mA
IN
CC
IN
CC
TRI-STATE or Open Drain
Leakage Current
b
a
10
10
mA
2
s
s
s
s
a
V
CC
b
AC Electrical Characteristics 55 C
a
a
125 C, 4.5V
T
A
5.5V unless otherwise specified.
§
§
Parameter
Conditions
Min
Max
Units
Instruction Cycle Time (tc)
4.4
DC
ms
d
d
d
Operating CKI
Frequency
4 mode
8 mode
16 mode
DC
DC
DC
0.9
1.8
3.6
MHz
MHz
MHz
(
e
e
e
Duty Cycle (Note 4)
Rise Time (Note 4)
Fall Time (Note 4)
f
f
f
3.6 MHz
40
60
60
40
%
ns
ns
1
1
1
3.6 MHz External Clock
3.6 MHz External Clock
e
e
g
30k 5%
d
82 pF 5% ( 4 Mode)
Instruction Cycle Time
RC Oscillator (Note 4)
R
C
g
6
18
ms
Inputs: (SeeFigure 3 ) (Note 4)
a
t
G Inputs
SI Input
tc/4 0.8
ms
ms
ms
ms
SETUP
0.33
All Others
1.9
t
0.4
HOLD
e
e
e
100 pF, R 5k
L
Output Propagation Delay
, t
V
OUT
1.5V, C
L
t
1.4
ms
PD1 PD0
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to V
with 5k
CC
resistors. See current drain equation on page 13.
Note 2: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to V , L lines in TRI-STATE mode and
CC
tied to ground, all outputs low and tied to ground.
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is not tested but guaranteed by design. Variation due to the device included.
Note 5: Voltage change must be less than 0.25 volts in a 1 ms period.
Note 6: SO output sink current must be limited to keep V less than 0.2 V
OL
when part is running in order to prevent entering test mode.
CC
s
s
RETS COP244CX DC Parameters Test Conditions 5.3V
V
CC
3V Unless Otherwise Specified
SBGRP 1
a
SBGRP 2 SBGRP 3
b
Drift
Parameter
a
25 C
§
125 C
§
55 C
§
Ý
Symbol
V
CC
Conditions
Test
Limits Units
(Note 1)
(25 C)
§
Min
Max
85
Min
Max
155
125
Min
Max
85
e
4V,
I
I
Supply Current
V
DD1
DD2
DD
mA
mA
e
F
64 kHz
IN
e
Halt Current
V
4V
35
35
DD
Input Voltage
Reset, CKI:
Logic High
V
V
9 V
9 V
9 V
V
V
IH1
CC
CC
CC
Logic Low
1 V
2 V
1 V
2 V
1 V
2 V
IL1
CC
CC
CC
All Other Inputs:
Logic High
V
V
7 V
7 V
7 V
V
V
IH2
IL2
CC
CC
CC
Logic Low
CC
CC
CC
Output Voltage
LSTTL Operation:
Logic High
e b
V
V
4.75V I
4.75V I
100 mA
10 mA
2.7
2.7
2.7
V
V
OH1
OH
e
Logic Low
400 mA
0.4
0.4
0.4
OL1
OL
CMOS Operation:
Logic High
e b
b
b
b
0.2
CC
V
V
4.75V I
4.75V I
V
0.2
V
0.2
V
V
V
OH2
OL2
OH
CC
CC
e
Logic Low
10 mA
0.2
0.2
0.2
OL
Output Current
Logic High
e
e
b
200
b
200
b
200
I
I
3V
3V
V
0V
100
100
100
mA
mA
OH
Logic Low
V
3V
OL
Input Leakage
High-Z
b
b
b
2.5
I
I
2.5
2.5
4
2.5
2.5
4
2.5
4
mA
mA
IN1
IN2
TRI-STATE or
Open Drain
b
b
b
4
4
4
RETS COP244CX
DEVICE: COP244C-XXX/883 FUNCTION: 4-BIT CMOS MICROCONTROLLER
3
s
s
3V Unless Otherwise Specified
RETS COP244CX AC Parameters Test Conditions 5.3V
V
CC
SBGRP 9
a
SBGRP 10 SBGRP 11
b
55 C
Drift
a
25 C
125 C
§
§
§
Min Max Min Max Min Max
Ý
Symbol
Parameter
V
CC
Conditions
Test
Limits Units
(25 C)
§
t
Instruction Cycle
Time (Note 1)
Mode Divided by 8,
e
CC
80
64
125
100
80
64
125
100
80
64
125
100
ms
V
DD
3V
e
F
Operating Clock
V
DD
3V,
kHz
IN
s s
30% Duty Cycle 50%
Frequency (Note 1)
Inputs
e
t
t
(Note 2)
V
4.5V
2
2
2
ms
ms
SETUP
Inputs
32
32
32
SETUP-G
For SKGZ & SKGBZ
(Note 2)
t
(Note 1)
0.6
0.6
0.6
ms
HOLD
e
e
100 pF
1.5V
t
t
Output Prop Delay
(Note 1)
R
5k, C
L
e
6
6
6
6
6
6
ms
ms
PD1
L
4.5V
V
PD2
OUT
RETS COP244CX
DEVICE: COP244C-XXXD/883 FUNCTION: 4-BIT CMOS MICROCONTROLLER
Note 1: Parameter tested go-no-go only.
Note 2: Guaranteed by design and not tested.
4
Connection Diagrams
S.O. Wide and DIP
S.O. Wide and DIP
Top View
TL/DD/8422–3
Top View
Order Number COP225C-XXX/N
or COP245C-XXX/N
See NS Molded Package Number N24A
TL/DD/8422–2
Order Number COP226C-XXX/N
See NS Molded Package Number N20A
Order Number COP225C-XXX/D
or COP245C-XXX/D
See NS Hermetic Package Number D24C
Order Number COP226C-XXX/D
See NS Hermetic Package Number D20A
Order Number COP226C-XXX/WM
See NS Surface Mount Package Number M20B
DIP
28 PLCC
Top View
TL/DD/8422–4
TL/DD/8422–13
Order Number COP224C-XXX/V
or COP244C-XXX/V
See NS PLCC Package Number V28A
Order Number COP224C-XXX/N
or COP244C-XXX/N
See NS Molded Package Number N28B
Order Number COP224C-XXX/D
or COP244C-XXX/D
See NS Hermetic Package Number D28C
FIGURE 2
5
Pin Descriptions
Pin
Description
Pin
Description
L7–L0
8-bit bidirectional
SK
Logic controlled
clock output
port with TRI-STATE
G3–G0
4-bit bidirectional
I/O port
CKI
Chip oscillator input
CKO
Oscillator output,
HALT I/O port or
general purpose input
D3–D0
4-bit output port
IN3–IN0
4-bit input port
(28 pin package only)
RESET
Reset input
SI
Serial input or
counter input
V
Most positive
power supply
CC
SO
Serial or general
purpose output
GND
Ground
Functional Description
The internal architecture is shown in Figure 1. Data paths
are illustrated in simplified form to depict how the various
logic elements communicate with each other in implement-
ing the instruction set of the device. Positive logic is used.
When a bit is set, it is a logic ‘‘1’’, when a bit is reset, it is a
logic ‘‘0’’.
RAM addressing is implemented by a 7-bit B register whose
upper 3 bits (Br) select 1 of 8 data registers and lower 4 bits
(Bd) select 1 of 16 4-bit digits in the selected data register.
Data memory consists of a 256-bit RAM for the COP224C/
c
225C/226C, organized as 4 data registers of 16
4-bits
digits. The B register is 6 bits long. Upper 2 bits (Br) select 1
of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit
digits in the selected data register. While the 4-bit contents
of the selected RAM digit (M) are usually loaded into or
from, or exchanged with, the A register (accumulator), it
may also be loaded into or from the Q latches or T counter
or loaded from the L ports. RAM addressing may also be
performed directly by the LDD and XAD instructions based
upon the immediate operand field of these instructions.
Caution:
The output options available on the COP224C/225C/226C
and COP244C/245C are not the same as those available
on the COP324C/325C/326C, COP344C/345C, COP424C/
425C/426C and COP444C/445C. Options not available on
the COP224C/225C/226C and COP244C/245C are: Option
2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value
0; Option 17 value 1; Option 30, Dual Clock, all values; Op-
tion 32, MicrobusTM, all values; Option 33 values 2, 4, and 6;
Option 34 all values; and Option 35 all values.
The Bd register also serves as a source register for 4-bit
data sent directly to the D outputs.
PROGRAM MEMORY
INTERNAL LOGIC
Program Memory consists of ROM, 1024 bytes for the
COP224C/225C/226C and 2048 bytes for the COP244C/
245C. These bytes of ROM may be program instructions,
constants or ROM addressing data.
The processor contains its own 4-bit A register (accumula-
tor) which is the source and destination register for most I/O,
arithmetic, logic, and data memory access operations. It can
also be used to load the Br and Bd portions of the B regis-
ter, to load and input 4 bits of the 8-bit Q latch or T counter,
to input 4 bits of L I/O ports data, to input 4-bit G, or IN
ports, and to perform data exchanges with the SIO register.
ROM addressing is accomplished by an 11-bit PC register
which selects one of the 8-bit words contained in ROM. A
new address is loaded into the PC register during each in-
struction cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next sequen-
tial 11-bit binary count value.
A 4-bit adder performs the arithmetic and logic functions,
storing the results in A. It also outputs a carry bit to the 1-bit
C register, most often employed to indicate arithmetic over-
flow. The C register in conjunction with the XAS instruction
and the EN register, also serves to control the SK output.
Three levels of subroutine nesting are implemented by a
three level deep stack. Each subroutine call or interrupt
pushes the next PC address into the stack. Each return
pops the stack back into the PC register.
The 8-bit T counter is a binary up counter which can be
loaded to and from M and A using CAMT and CTMA instruc-
tions. This counter may be operated in two modes depend-
ing on a mask-programmable option: as a timer or as an
external event counter. When the T counter overflows, an
DATA MEMORY
Data memory consists of a 512-bit RAM for the COP244C/
c
245C, organized as 8 data registers of 16
4-bit digits.
6
Functional Description (Continued)
overflow flag will be set (see SKT and IT instructions below).
The T counter is cleared on reset. A functional block dia-
gram of the timer/counter is illustrated in Figure 7.
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. The SK outputs SKL ANDed with
the instruction cycle clock.
Four general-purpose inputs, IN3–IN0, are provided.
1. With EN1 set, interrupt is enabled. Immediately following
an interrupt, EN1 is reset to disable further interrupts.
The D register provides 4 general-purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
2. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O port. Resetting EN2 disables the L driv-
ers, placing the L I/O port in a high-impedance input
state.
The G register contents are outputs to a 4-bit general-pur-
pose bidirectional I/O port.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded to or from M and A, as well as 8-bit data
from ROM. Its contents are outputted to the L I/O ports
when the L drivers are enabled under program control.
3. EN3, in conjunction with EN0, affects the SO output. With
EN0 set (binary counter option selected) SO will output
the value loaded into EN3. With EN0 reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift reg-
ister output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains set to ‘‘0’’.
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O port. Also, the contents of L may
be read directly into A and M.
The SIO register functions as a 4-bit serial-in/serial-out shift
register for MICROWIRE I/O and COPS peripherals, or as a
binary counter (depending on the contents of the EN regis-
ter). Its contents can be exchanged with A.
INTERRUPT
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK outputs SKL ANDed with the clock.
The following features are associated with interrupt proce-
dure and protocol and must be considered by the program-
mer when utilizing interrupts.
EN is an internal 4-bit register loaded by the LEI instruction.
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN regis-
ter:
a. The interrupt, once recognized as explained below,
pushes the next sequential program counter address
a
(PC 1) onto the stack. Any previous contents at the bot-
tom of the stack are lost. The program counter is set to
hex address 0FF (the last word of page 3) and EN1 is
reset.
0. The least significant bit of the enable register, EN0, se-
lects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With EN0 set, SIO is an asynchro-
nous binary counter, decrementing its value by one upon
each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output equals
the value of EN3. With EN0 reset, SIO is a serial shift
register left shifting 1 bit each instruction cycle time. The
data present at SI goes into the least significant bit of
b. An interrupt will be recognized only on the following con-
ditions:
1. EN1 has been set.
2. A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction
cycles wide has occurred on the IN input.
1
3. A currently executing instruction has been completed.
TL/DD/8422–5
FIGURE 3. Input/Output Timing Diagrams (divide by 8 mode)
TABLE I. Enable Register Modes Ð Bits EN0 and EN3
EN0 EN3
SIO
Shift
SI
SO
SK
e e
If SKL 1,SK clock
If SKL 0,SK
0
0
1
1
0
1
0
1
Input to Shift
0
e
e
0
Register Register
e e
Input to Shift Serial If SKL 1,SK clock
Shift
e
e
0
Register Register
out If SKL 0,SK
e
SK SKL
Binary
Counter Counter
Binary Input to
Counter Counter
Input to
0
1
e
SK SKL
7
Functional Description (Continued)
4. All successive transfer of control instructions and suc-
cessive LBIs have been completed (e.g. if the main
program is executing a JP instruction which transfers
program control to another JP instruction, the interrupt
will not be acknowledged until the second JP instruc-
tion has been executed).
TIMER
There are two modes selected by mask option:
a. Time-base counter. In this mode, the instruction cycle fre-
quency generated from CKI passes through a 2-bit divide-
by-4 prescaler. The output of this prescaler increments
the 8-bit T counter thus providing a 10-bit timer. The pre-
scaler is cleared during execution of a CAMT instruction
and on reset.
c. Upon acknowledgement of an interrupt, the skip logic
status is saved and later restored upon popping of the
stack. For example, if an interrupt occurs during the exe-
cution of ASC (Add with Carry, Skip on Carry) instruction
which results in carry, the skip logic status is saved and
program control is transferred to the interrupt servicing
routine at hex address 0FF. At the end of the interrupt
routine, a RET instruction is executed to pop the stack
and return program control to the instruction following the
original ASC. At this time, the skip logic is enabled and
skips this instruction because of the previous ASC carry.
Subroutines should not be nested within the interrupt
service routine, since their popping of the stack will en-
able any previously saved main program skips, interfering
with the orderly execution of the interrupt routine.
For example, using a 3.58 MHz crystal with a divide-by-16
option, the instruction cycle frequency of 223.70 kHz in-
crements the 10-bit timer every 4.47 ms. By presetting the
counter and detecting overflow, accurate timeouts be-
tween 17.88 ms (4 counts) and 4.577 ms (1024 counts)
are possible. Longer timeouts can be achieved by accu-
mulating, under software control, multiple overflows.
b. External event counter. In this mode, a low-going pulse
(‘‘1’’ to ‘‘0’’) at least 2 instruction cycles wide on the IN2
input will increment the 8-bit T counter.
Note: The IT instruction is not allowed in this mode.
d. The instruction at hex address 0FF must be a NOP.
e. An LEI instruction may be put immediately before the
RET instruction to re-enable interrupts.
INITIALIZATION
The internal reset logic will initialize the device upon power-
up if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz, other-
wise the external RC network shown in Figure 4 must be
connected to the RESET pin (the conditions in Figure 4
must be met). The RESET pin is configured as a Schmitt
trigger input. If not used, it should be connected to V
.
CC
Initialization will occur whenever a logic ‘‘0’’ is applied to the
RESET input, providing it stays low for at least three instruc-
tion cycle times.
Note: If CKI clock is less than 32 kHz, the internal reset logic (option
Ý
e
29 1) MUST be disabled and the external RC circuit must be used.
TL/DD/8422–7
Crystal or Resonator
Crystal
Value
Component Values
R1
R2
C1(pF)
C2(pF)
32 kHz
220k
5k
2k
20M
10M
1M
30
80
30
30
6–36
40
6–36
6–36
455 kHz
2.096 MHz
3.6 MHz
1k
1M
TL/DD/8422–6
FIGURE 4. Power-Up Circuit
RC Controlled Oscillator
Cycle
Time
Upon initialization, the PC register is cleared to 0 (ROM ad-
dress 0) and the A, B, C, D, EN, IL, T and G registers are
cleared. The SKL latch is set, thus enabling SK as a clock
output. Data Memory (RAM) is not cleared upon initializa-
tion. The first instruction at address 0 must be a CLRA
(clear A register).
R
C
V
CC
t
4.5V
30k
82 pF
6–18 ms
s
s
150k
Note: 15k
R
s
s
50 pF
C
150 pF
FIGURE 5. Oscillator Component Values
8
Functional Description (Continued)
the external driver returns to high impedance state.
By forcing a low level to CKO, the chip will continue
and CKO will stay low.
HALT MODE
The COP244C/245C/224C/225C/226C is a FULLY STAT-
IC circuit; therefore, the user may stop the system oscillator
at any time to halt the chip. The chip may also be halted by
the HALT instruction or by forcing CKO high when it is
mask-programmed as a HALT I/O port. Once in the HALT
mode, the internal circuitry does not receive any clock sig-
nal and is therefore frozen in the exact state it was in when
halted. All information is retained until continuing. The chip
may be awakened by one of two different methods:
As another option, CKO can be a general purpose in-
put, read into bit 2 of A (accumulator) upon execution
of an INIL instruction.
#
OSCILLATOR OPTIONS
There are three basic clock oscillator configurations avail-
able as shown by Figure 5.
a. Crystal Controlled Oscillator. CKI and CKO are connect-
ed to an external crystal. The instruction cycle time equals
the crystal frequency optionally divided by 4, 8 or 16.
Continue function: by forcing CKO low, if it mask-pro-
#
grammed as a HALT I/O port, the system clock is re-en-
abled and the circuit continues to operate from the point
where it was stopped.
b. External Oscillator. The external frequency is optionally
divided by 4, 8 or 16 to give the instruction cycle time.
CKO is the HALT I/O port or a general purpose input.
Restart: by forcing the RESET pin low (see Initializa-
tion).
#
c. RC Controlled Oscillator. CKI is configured as a single pin
RC controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
is the HALT I/O port or a general purpose input.
The HALT mode is the minimum power dissipation state.
CKO PIN OPTIONS
a. Two-pin oscillatorÐ(Crystal). See Figure 6a.
Figure 7 shows the clock and timer diagram.
In a crystal controlled oscillator system, CKO is used as
an output to the crystal network. The HALT mode may be
entered by program control (HALT instruction) which
forces CKO high, thus inhibiting the crystal network. The
circuit can be awakened only by forcing the RESET pin to
a logic ‘‘0’’ (restart).
COP245C AND COP225C 24-PIN PACKAGE OPTION
If the COP244C/224C is bonded in a 24-pin package, it be-
comes the COP245C/225C, illustrated in Figure 2, Connec-
tion diagrams. Note that the COP245C/225C does not con-
tain the four general purpose IN inputs (IN3–IN0). Use of
this option precludes, of course, use of the IN options, inter-
rupt feature, external event counter feature.
b. One-pin oscillatorÐ(RC or external). See Figure 6b.
If a one-pin oscillator system is chosen, two options are
available for CKO:
Note: If user selects the 24-pin package, options 9, 10, 19 and 20 must be
selected as a ‘‘2’’. See option list.
CKO can be selected as the HALT I/O port. In that
#
case, it is an I/O flip-flop which is an indicator of the
HALT status. An external signal can over-ride this pin
to start and stop the chip. By forcing a high level to
CKO, the chip will stop as soon as CKI is high and
CKO output will stay high to keep the chip stopped if
COP226C 20-PIN PACKAGE OPTION
If the COP225C is bonded as 20-pin device it becomes the
COP226C. Note that the COP226C contains all the
COP225C pins except D , D , G , and G .
0
1
0
1
Block Diagram
TL/DD/8422–8
FIGURE 6a. Halt ModeÐTwo-Pin Oscillator
9
Block Diagrams (Continued)
TL/DD/8422–9
FIGURE 6b. Halt ModeÐOne-Pin Oscillator
TL/DD/8422–10
FIGURE 7. Clock and Timer
10
Instruction Set
Table II is a symbol table providing internal architecture, in-
struction operand and operation symbols used in the in-
struction set table.
Instruction Operand Symbols
d
r
4-bit operand field, 0–15 binary (RAM digit select)
TABLE II. Instruction Set Table Symbols
3(2)-bit operand field, 0–7(3) binary
(RAM register select)
Symbol
Definition
a
y
11-bit operand field, 0–2047 (1023)
4-bit operand field, 0–15 (immediate data)
Internal Architecture Symbols
RAM(x) RAM addressed by variable x
ROM(x) ROM addressed by variable x
A
4-bit accumulator
B
7-bit RAM address register (6-bit for COP224C)
Upper 3 bits of B (register address)
(2-bit for COP224C)
Br
Operational Symbols
Bd
C
Lower 4 bits of B (digit address)
1-bit carry register
a
b
Plus
Minus
D
4-bit data output port
x
Ý
e
Replaces
EN
G
4-bit enable register
Is exchanged with
Is equal to
4-bit general purpose I/O port
two 1-bit (IN0 and IN3) latches
4-bit input port
IL
A
Z
:
One’s complement of A
Exclusive-or
Range of values
IN
L
8-bit TRI-STATE I/O port
4-bit contents of RAM addressed by B
11-bit ROM address program counter
8-bit latch for L port
M
PC
Q
Table III provides the mnemonic, operand, machine code
data flow, skip conditions and description of each instruc-
tion.
SA,SB,SC 11-bit 3-level subroutine stack
SIO
SK
SKL
T
4-bit shift register and counter
Logic-controlled clock output
1-bit latch for SK output
8-bit timer
TABLE III. COP244C/245C Instruction Set
Machine
Hex
Language
Code
Skip
Mnemonic
Operand
Data Flow
Description
Code
Conditions
(Binary)
ARITHMETIC INSTRUCTIONS
a
a
ASC
30
0011 0000
À
A
RAM(B)
x
A
Carry
Add with Carry, Skip on
Carry
CarrCyx
C
À
À
a
ADD
ADT
31
4A
b
0011 0001
À
A
A
A
RAM(B)
x
A
None
None
Carry
Add RAM to A
À
À
À
À
a
a
0100 1010
À
1010x
x
A
Add Ten to A
À
AISC
y
5
0101
y
y
A
Add Immediate. Skip on
i
Carry (y 0)
À
À
a
Carry
a
C
CASC
10
0001 0000
À
A
RAM(B)
x
x
A
Carry
Complement and Add with
Carry, Skip on Carry
À
À
C
CLRA
COMP
NOP
RC
00
40
44
32
22
02
0000 0000
À
0100 0100
0
x
x
A
None
None
None
None
None
None
Clear A
À
À
À
À
À
À
À
À
À
À
À
À
0100 0000
À
0011 0010
A
A
Ones complement of A to A
No Operation
Reset C
None
À
0010 0010
‘‘0’’
‘‘1’’
x
x
C
C
À
0000 0010
SC
Set C
À
Z
XOR
A
RAM(B)
x
A
Exclusive-OR RAM with A
À
11
Instruction Set (Continued)
TABLE III. COP244C/245C Instruction Set (Continued)
Machine
Language
Code
Hex
Skip
Mnemonic
Operand
Data Flow
Description
Code
Conditions
(Binary)
TRANSFER CONTROL INSTRUCTIONS
JID
FF
1111 1111
À
ROM (PC
10:8
A,M)
x
PC
None
None
Jump Indirect (Notes 1, 3)
Jump
7:0
À
À
b
JMP
a
a
6
0110 0 a
À
a
x
x
PC
10:8
À
À
À
bb
a
7:0
À
À
bb
JP
1
a
a
PC
None
Jump within Page (Note 4)
6:0
6:0
À
À
11
À
5:0
(pages 2, 3 only)
or
bb
bb
a
a
x
PC
5:0
À
À
À
(all other pages)
a
JSRP
JSR
a
a
10
a
PC x xSB
x
x
SC
SC
None
Jump to Subroutine Page
(Note 5)
000101xPSCA
x
5:0
À
À
À
10:6
a
PC
5:0
b
a
6
0110 1 a
À
x
SA
x
SB
None
None
Jump to Subroutine
a
a
PxC 1PC
10:8
À
À
À
À
bb
7:0
À
0100 1001
RET
48
0100 1000
À
SC
x
x
SB
x
x
SA
SA
x
x
PC
PC
Return from Subroutine
À
À
À
À
RETSK
49
SC
SB
Always Skip
on Return
Return from Subroutine
then Skip
À
0011 1000
HALT
IT
33
38
33
39
0011 0011
À
None
HALT Processor
À
À
À
À
À
À
À
À
À
0011 0011
À
IDLE till Timer
0011 1001
À
None
Overflows then Continues
MEMORY REFERENCE INSTRUCTIONS
CAMT
CTMA
CAMQ
CQMA
LD
33
3F
0011 0011
À
A
x
T
RAM(B)7x:4
T
3:0
None
Copy A, RAM to T
À
À
0011 1111
À
À
À
33
2F
0011 0011
À
T
7:4xRAM(B)
À
À
À
À
0010 1111
À
T3:0x
A
None
None
Copy T to RAM, A
Copy A, RAM to Q
33
0011 0011
À
A
x
RAM(B)
Q
7:4
À
À
À
À
3C
0011 1100
À
x
7:4xRAM(B)
3:0x
Q
3:0
33
0011 0011
À
Q
Q
None
None
None
None
None
Copy Q to RAM, A
À
À
À
À
2C
0010 1100
À
A
b
r
5
00
r
0101
RAM(B)
x
xBr
A
Load RAM into A,
À
À
À
À
e
(r 0:3)
Z
Br
r
Exclusive-OR Br with r
LDD
r,d
23
bb
0010 0011
À
RAM(r,d)
x
A
Load A with RAM pointed
to directly by r,d
À
À
À
À
0
r
d
À
À
À
LQID
RMB
BF
1011 1111
À
,A,M)
10:8
x
Q
Load Q Indirect (Note 3)
RSBOxM(PSCC
À
0100 0101
À
0xRAM(B)
0
1
2
3
4C
45
42
43
0100 1100
À
x
Reset RAM Bit
0
À
À
À
À
À
À
À
À
0xRAM(B)
1
2
3
0100 0010
À
0100 0011
À
0
0xRRAAMM((BB))
SMB
0
1
2
3
4D
47
46
4B
0100 1101
À
x
1xRAM(B)
None
Set RAM Bit
1xRAM(B)
0
1
2
3
À
À
À
À
À
À
À
À
0100 0111
À
0100 0110
À
0100 1011
À
1
1xRRAAMM((BB))
12
Instruction Set (Continued)
TABLE III. COP244C/245C Instruction Set (Continued)
Machine
Language
Code
Hex
Skip
Mnemonic
Operand
Data Flow
Description
Code
Conditions
(Binary)
MEMORY REFERENCE INSTRUCTIONS (Continued)
b
STII
y
7
0111
y
y
x
RAM(B)
x
None
None
None
Store Memory Immediate
1 and Increment Bd
À
À
À
À
a
Bd
1
Bd
b
X
r
6
00
r
0110
RAM(B)Ý
x
A
Exchange RAM with A,
Exclusive-OR Br with r
À
À
À
e
(r 0:3)
Z
Br
r
Br
XAD
XDS
r,d
r
23
bb
0010 0011
À
RAM(r,d)
Ý
A
Exchange A with RAM
Pointed to Directly by r,d
À
À
1
r
d
À
À
À
À
b
7
00 r 0111
À
RAM(B)
Ý
A
Bd
Exchange RAM with A
and Decrement Bd.
À
À
À
À
e
(r 0:3)
b
Z
Bd
Br
x
Bd
decrements
past 0
r
1 xBr
Exclusive-OR Br with r
b
XIS
r
4
00
r
0100
RAM(B)
Ý
A
Bd
Exchange RAM with A
and Increment Bd,
À
À
À
e
(r 0:3)
a
Bd
Br
1
x
increments
past 15
r
xBBrd
Exclusive-OR Br with r
Z
REGISTER REFERENCE INSTRUCTIONS
CAB
CBA
LBI
50
4E
0101 0000
À
00 r (d–1)
A
x
Bdx
Bd
None
None
Copy A to Bd
Copy Bd to A
À
À
À
À
À
0100 1110
À
A
bb
r,d
r,d
x
B
Skip until
not a LBI
Load B Immediate with r,d
(Note 6)
À
À
À
e
(r 0:3:
e
d
0,9:15)
or
33
bb
0011 0011
À
À
À
1
r
d
À
À
À
À
(any r, any d)
LEI
y
33
b
0011 0011
y
x
EN
None
None
Load EN Immediate (Note 7)
Exchange A with Br (Note 8)
À
À
À
À
À
À
6
0110
y
À
XABR
12
0001 0010
A
Ý
Br
À
À
TEST INSTRUCTIONS
e
e
SKC
20
21
0010 0000
C
A
‘‘1’’
Skip if C is True
À
À
À
À
SKE
0010 0001
À
RAM(B)
Skip if A Equals RAM
À
e
SKGZ
33
21
0011 0011
G
0
Skip if G is Zero
(all 4 bits)
3:0
À
À
À
0000 0001
À
À
0010 0001
À
0001 0001
SKGBZ
33
01
11
03
13
0011 0011
À
1st byte
2nd byte
Skip if G Bit is Zero
À
À
À
À
À
À
À
À
À
À
e
e
e
e
0
1
2
3
G
G
G
G
0
0
0
0
0
À
1
2
3
À
0000 0001
0000 0011
À
0001 0001
0001 0011
*
À
0000 0011
e
e
e
e
SKMBZ
SKT
0
1
2
3
01
11
03
13
RAM(B)
RAM(B)
RAM(B)
RAM(B)
0
0
0
0
Skip if RAM Bit is Zero
0
1
2
3
À
À
À
À
À
À
À
À
À
À
0100 0001
À
0001 0011
À
41
A time-base
counter carry
has occurred
since last test
Skip on Timer
(Note 3)
À
À
À
13
Instruction Set (Continued)
TABLE III. COP244C/245C Instruction Set (Continued)
Machine
Language
Code
Hex
Skip
Mnemonic
Operand
Data Flow
Description
Code
Conditions
(Binary)
INPUT/OUTPUT INSTRUCTIONS
ING
ININ
INIL
INL
33
2A
0011 0011
À
G
x
A
None
None
None
None
None
None
None
None
Input G Ports to A
À
À
À
À
0010 1010
À
33
28
0011 0011
À
IN
x
A
Input IN Inputs to A
(Note 2)
À
À
À
À
0010 1000
À
33
29
0011 0011
À
IL , CKO,‘‘0’’, IL0x
A
Input IL Latches to A
(Note 3)
3
À
À
À
À
0010 1001
À
33
2E
0011 0011
À
L
7:4xRAM(B)
Input L Ports to RAM,A
À
À
À
À
0010 1110
À
L
3:0x
x
A
OBD
OGI
OMG
XAS
33
3E
0011 0011
À
Bd
D
Output Bd to D Outputs
À
À
À
À
0011 1110
À
y
33
b
0011 0011
À
y
x
G
Output to G Ports
Immediate
À
À
À
5
0101
y
À
À
33
3A
0011 0011
À
RAM(B)
x
G
Output RAM to G Ports
À
À
À
0011 1010
À
À
4F
0100 1111
À
A
Ý
SIO, C
x
SKL
Exchange A with SIO
(Note 3)
À
À
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
0 signifies the least significant bit (low-order, right-most bit). For example, A indicates the most significant (left-most) bit of the 4-bit A register.
3
Note 2: The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, JID, LQID, INIL, and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 5: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
e
e.g., to load the lower four bits of B(Bd) with the value 9 (1001 ), the lower 4 bits of the LBI instruction equal 8 (1000 ). To load 0, the lower 4 bits of the LBI
Note 6: LBI is a single-byte instruction if d
0, 9, 10, 11, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the ‘‘d’’ data minus 1,
2
2
instruction should equal 15 (1111 ).
2
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
Note 8: For 2K ROM devices, A
Ý
Br (0
x
A3). For 1K ROM devices, A
Ý
Br (0,0
x
A3, A2).
14
Description of Selected Instructions
pulse stays low for at least two instruction cycles. Execution
of an INIL inputs IL3 and IL0 into A3 and A0 respectively,
and resets these latches to allow them to respond to subse-
quent low-going pulses on the IN3 and IN0 lines. If CKO is
mask programmed as a general purpose input, an INIL will
input the state of CKO into A2. If CKO has not been so
programmed, a ‘‘1’’ will be placed in A2. A0 is input into A1.
IL latches are cleared on reset. IL latches are not available
on the COP245C/225C, and COP226C.
XAS INSTRUCTION
XAS (Exchange A with SIO) copies C to the SKL latch and
exchanges the accumulator with the 4-bit contents of the
SIO register. The contents of SIO will contain serial-in/seri-
al-out shift register or binary counter data, depending on the
value of the EN register. If SIO is selected as a shift register,
an XAS instruction can be performed once every 4 instruc-
tion cycles to effect a continuous data stream.
LQID INSTRUCTION
INSTRUCTION SET NOTES
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 11-bit word
PC10:PC8,A,M. LQID can be used for table lookup or code
a. The first word of a program (ROM address 0) must be a
CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, they are
still fetched from the program memory. Thus program
paths take the same number of cycles whether instruc-
tions are skipped or executed except for JID, and LQID.
a
struction ‘‘pushes’’ the stack (PC
1
conversion such as BCD to seven-sxegment. The LQID in-
SA
x
SB
x
SC)
AxPC7:4, RAM(B)
PC8 unchanged. The ROM data pointed to by the new ad-
and replaces the leastxsignPifCic3a:n0t, 8lebaitvsinogf thPeCP1C0,aPsCfo9lloawnsd:
c. The ROM is organized into pages of 64 words each. The
Program Counter is a 11-bit binary counter, and will count
through page boundaries. If a JP, JSRP, JID, or LQID is
the last word of a page, it operates as if it were in the next
page. For example: a JP located in the last word of a
page will jump to a location in the next page. Also, a JID
or LQID located in the last word of every fourth page (i.e.
hex address 0FF, 1FF, 2FF, 3FF, 4FF, etc.) will access
data in the next group of four pages.
stack is ‘‘popped’’ (SC
x
SB
x
SA
dress is fetched and loaded into thexQ lPatCc)h,erse.stNoerixntg, tthhee
stiaovne. dSivnacleueLQofIDPCputsohecsonStBinxue sSeCqu, ethnetiaplrepvroiogurasmcoenxteecnuts-
of SC are lost.
Note: LQID uses 2 instruction cycles if executed, one if skipped.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 11-bit word, PC10:8,A,M. PC10,PC9 and PC8 are not
affected by JID.
Note: The COP224C/225C/226C needs only 10 bits to address its ROM.
Therefore, the eleventh bit (P10) is ignored.
Power Dissipation
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, the user should run
at the lowest speed and voltage that his application will al-
low. The user should take care that all pins swing to full
supply levels to insure that outputs are not loaded down and
that inputs are not at some intermediate level which may
draw current. Any input with a slow rise or fall time will draw
additional current. A crystal or resonator generated clock
input will draw additional current. For example, a 500 kHz
crystal input will typically draw 100 mA more than a square-
wave input. An R/C oscillator will draw even more current
since the input is a slow rising signal.
Note: JID uses 2 instruction cycles if executed, one if skipped.
SKT INSTRUCTION
The SKT (Skip On Timer) instruction tests the state of the T
counter overflow latch (see internal logic, above), executing
the next program instruction if the latch is not set. If the
latch has been set since the previous test, the next program
instruction is skipped and the latch is reset. The features
associated with this instruction allow the processor to gen-
erate its own time-base for real-time processing, rather than
relying on an external input signal.
Note: If the most significant bit of the T counter is a 1 when a CAMT instruc-
tion loads the counter, the overflow flag will be set. The following
sample of codes should be used when loading the counter:
If using an external squarewave oscillator, the following
equation can be used to calculate operating current drain.
CAMT ; load T counter
e
a
Q
c
c
70 Fi
a c c
V 2400 Fi/Dv where:
I
I
V
CO
I
SKT
; skip if overflow flag is set and reset it
e
chip operating current drain in microamps
NOP
CO
e
I
quiescent leakage current (from curve)
Q
IT INSTRUCTION
e
Fi CKI frequency in MegaHertz
The IT (idle till timer) instruction halts the processor and
puts it in an idle state until the time-base counter overflows.
This idle state reduces current drain since all logic (except
the oscillator and time base counter) is stopped. IT instruc-
tion is not allowed if the T counter is mask-programmed as
e
V
chip V in volts
CC
e
Dv divide by option selected
For example at 5 volts V and 400 kHz (divide by 4)
CC
e
an external event counter (option 31 1).
Ý
e
e
a
a
c
c
70 0.4
a c c
5 2400 0.4/4
I
I
120
5
CO
CO
a
e
INIL INSTRUCTION
120 140 1200 1460 mA
INIL (Input IL Latches to A) inputs 2 latches, IL3 and IL0,
CKO and 0 into A. The IL3 and IL0 latches are set if a low-
going pulse (‘‘1’’ to ‘‘0’’) has occurred on the IN3 and IN0
inputs since the last INIL instruction, provided the input
15
Power Dissipation (Continued)
If an IT instruction is executed, the chip goes into the IDLE
mode until the timer overflows. In IDLE mode, the current
drain can be calculated from the following equation:
I/O OPTIONS
Outputs have the following optional configurations, illustrat-
ed in Figure 8 :
e
a c c
V 70 Fi
Ici
I
Q
a. Standard Ð A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
For example, at 5 volts V
and 400 kHz
CC
to V , compatible with CMOS and LSTTL.
CC
e
Ici 120
a
c c e
5 70 0.4 260 mA
b. Open Drain Ð An N-channel device to ground only, al-
lowing external pull-up as required by the user’s applica-
tion.
The total average current will then be the weighted average
of the operating current and the idle current:
c. Standard TRI-STATE L Output Ð A CMOS output buffer
similar to a. which may be disabled by program control.
To
Ti
e
c
a
c
Ici
d. Open-Drain TRI-STATE L Output Ð This has the N-chan-
nel device to ground only.
Ita
I
CO
a
To Ti
a
To Ti
e
where: Ita total average current
All inputs have the following option:
e
I
operating current
CO
e. Hi-Z input which must be driven by the users logic.
e
Ici idle current
All output drivers use two common devices numbered 1 to
) curves
OUT
are given in Figure 9 for each of these devices to allow the
designer to effectively use these I/O configurations.
e
To operating time
2. Minimum and maximum current (I
and V
OUT
e
Ti idle time
TL/DD/8422–11
c. Standard TRI-STATE ‘‘L’’ Output
d. Open Drain TRI-STATE
‘‘L’’ Output
e. Hi-Z Input
FIGURE 8. Input/Output Configurations
16
Power Dissipation (Continued)
Minimum Sink Current
(Except CKO)
Minimum Source Current
(Except CKO)
Maximum Quiescent Current
TL/DD/8422–12
FIGURE 9. Input/Output Characteristics
Option List
The COP244C/245C/224C/225C/COP226C mask-pro-
grammable options are assigned numbers which corre-
spond with the COP244C/224C pins.
Option 4: RESET input
e
1: Hi-Z input
Option 5: L7 Driver
The following is a list of options. The options are pro-
grammed at the same time as the ROM pattern to provide
the user with the hardware flexibility to interface to various
I/O components using little or no external circuitry.
e
e
0: Standard TRI-STATE push-pull output
2: Open-drain TRI-STATE output
Option 6: L6 Driver Ð (same as option 5)
Option 7: L5 Driver Ð (same as option 5)
Option 8: L4 Driver Ð (same as option 5)
Option 9: IN1 input
Caution:
The output options available on the COP224C/225C/226C
and COP244C/245C are not the same as those available
on the COP324C/325C/326C, COP344C/345C, COP424C/
425C/426C and COP444C/445C. Options not available on
the COP224C/225C/226C and COP244C/245C are: Option
2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value
0; Option 17 value 1; Option 30, Dual Clock, all values; Op-
tion 32, Microbus, all values; Option 33 values 2 4, and 6;
Option 34 all values; and Option 35 all values.
e
e
1: Hi-Z input, mandatory for 28 Pin Package
2: Mandatory for 20 and 24 Pin Packages
Option 10: IN2 input Ð (same as option 9)
e
Option 11 0:
V
Pin Ð no option available
CC
Option 12: L3 Driver Ð (same as option 5)
Option 13: L2 Driver Ð (same as option 5)
Option 14: L1 Driver Ð (same as option 5)
Option 15: L0 Driver Ð (same as option 5)
Option 16: SI input Ð (same as option 4)
Option 17: SO Driver
PLEASE FILL OUT THE OPTION TABLE on the next page.
Photocopy the option data and send it in with your disk or
EPROM.
e
Option 1 0: Ground Pin Ð no options available
Option 2: CKO Pin
e
e
0: clock generator output to crystal/resonator
0: Standard push-pull output
e
e
1: HALT I/O port
2: Open-drain output
e
3: general purpose input, high-Z
Option 3: CKI input
Option 18: SK Driver Ð (same as option 17)
Option 19: IN0 Input Ð (same as option 9)
Option 20: IN3 Input Ð (same as option 9)
Option 21: G0 I/O Port Ð (same as option 17)
Option 22: G1 I/O Port Ð (same as option 17)
Option 23: G2 I/O Port Ð (same as option 17)
Option 24: G3 I/O Port Ð (same as option 17)
Option 25: D3 Output Ð (same as option 17)
Option 26: D2 Output Ð (same as option 17)
Option 27: D1 Output Ð (same as option 17)
e
e
e
e
e
e
e
0: Crystal controlled oscillator input divide by 4
1: Crystal controlled oscillator input divide by 8
2: Crystal controlled oscillator input divide by 16
4: Single-pin RC controlled oscillator (divide by 4)
5: External oscillator input divide by 4
6: External oscillator input divide by 8
7: External oscillator input divide by 16
17
Option List (Continued)
Option 28: D0 Output Ð (same as option 17)
Option 29: Internal Initialization Logic
Option 33: COP bonding. See note.
(1k and 2k Microcontroller)
e
e
e
e
0: Normal operation
0: 28-pin package
1: 24-pin package
1: No internal initialization logic
e
Option 30 0: No Option Available
Option 31: Timer
(1k Microcontroller only)
e
3: 20-pin package
e
e
e
0: Time-base counter
5: 24- and 20-pin package
e
Ý
Ý
9, 10, 19, and 20
1: External event counter
Note:ÐIf opt.
e
must 1.
33
0
then opt.
e
Option 32 0: No Option Available
e
e
If opt. 33 1 then opt. 9, 10, 19 and 20 must 2, and
Ý
Ý
e
option 31 must 0.
Ý
e
e
If opt. 33 3 or 5 then opt. 9, 10, 19, 20 must 2 and
Ý
opt. 21, 22, 31 must 0.
Ý
e
Ý
e
Option 34 0: No Option Available
e
Option 35 0: No Option Available
Option Table
The following option information is to be sent to National along with the EPROM.
OPTION DATA
OPTION DATA
0
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
OPTION 1 VALUE
OPTION 2 VALUE
OPTION 3 VALUE
OPTION 4 VALUE
OPTION 5 VALUE
OPTION 6 VALUE
OPTION 7 VALUE
OPTION 8 VALUE
OPTION 9 VALUE
OPTION 10 VALUE
OPTION 11 VALUE
OPTION 12 VALUE
OPTION 13 VALUE
OPTION 14 VALUE
OPTION 15 VALUE
OPTION 16 VALUE
OPTION 17 VALUE
OPTION 18 VALUE
IS: GROUND PIN
IS: CKO PIN
OPTION 19 VALUE
OPTION 20 VALUE
OPTION 21 VALUE
OPTION 22 VALUE
OPTION 23 VALUE
OPTION 24 VALUE
OPTION 25 VALUE
OPTION 26 VALUE
OPTION 27 VALUE
OPTION 28 VALUE
OPTION 29 VALUE
OPTION 30 VALUE
OPTION 31 VALUE
OPTION 32 VALUE
OPTION 33 VALUE
OPTION 34 VALUE
OPTION 35 VALUE
IS: IN0 INPUT
IS: IN3 INPUT
IS: G0 I/O PORT
IS: G1 I/O PORT
IS: G2 I/O PORT
IS: G3 I/O PORT
IS: D3 OUTPUT
IS: D2 OUTPUT
IS: D1 OUTPUT
IS: D0 OUTPUT
IS: INT INIT LOGIC
IS: N/A
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
IS: CKI INPUT
IS: RESET INPUT
IS: L7 DRIVER
IS: L6 DRIVER
IS: L5 DRIVER
IS: L4 DRIVER
IS: IN1 INPUT
IS: IN2 INPUT
IS: VCC PIN
1
0
0
0
IS: L3 DRIVER
IS: L2 DRIVER
IS: L1 DRIVER
IS: L0 DRIVER
IS: SI INPUT
IS: TIMER
IS: N/A
IS: COP BONDING
IS: N/A
1
0
0
IS: SO DRIVER
IS: SK DRIVER
IS: N/A
18
19
Physical Dimensions inches (millimeters)
20-Lead Hermetic Dual-In-Line Package (D)
Order Number COP226C-XXX/D
NS Package Number D20A
20
Physical Dimensions inches (millimeters) (Continued)
24-Lead Hermetic Dual-In-Line Package (D)
Order Number COP225C-XXX/D or COP245C-XXX/D
NS Package Number D24C
28-Lead Hermetic Dual-In-Line Package (D)
Order Number COP224C-XXX/D or COP244C-XXX/D
NS Package Number D28C
21
Physical Dimensions inches (millimeters) (Continued)
20-Lead Surface Mount Package (M)
Order Number COP226C-XXX/WM
NS Package Number M20B
20-Lead Molded Dual-In-Line Package (N)
Order Number COP226C-XXX/N
NS Package Number N20A
22
Physical Dimensions inches (millimeters) (Continued)
24-Lead Molded Dual-In-Line Package (N)
Order Number COP225C-XXX/N or COP245C-XXX/N
NS Package Number N24A
28-Lead Molded Dual-In-Line Package (N)
Order Number COP224C-XXX/N or COP244C-XXX/N
NS Package Number N28B
23
Physical Dimensions inches (millimeters) (Continued)
Plastic Leaded Chip Carrier (V)
Order Number COP224C-XXX/V or COP244C-XXX/V
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明