COP881C-XXX/N [NSC]
COP880C Microcontroller; COP880C微控制器
| 型号： | COP881C-XXX/N |
| 厂家： | 
National Semiconductor |
| 描述： | COP880C Microcontroller |
| 文件： | 总31页 (文件大小：501K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package (N)
and 28 Wide SO (WM)
DS010802-23
Top View
Order Number COP882C-XXX/N, COP982C-XXX/N,
COP882C-XXX/WM, COP982C-XXX/WM,
COP982C-XXX/N or COP982CH-XXX/WM
DS010802-5
Top View
Order Number COP881C-XXX/N, COP981C-XXX/N,
COP881C-XXX/WM, COP981C-XXX/WM,
COP981CH-XXX/N or COP981CH-XXX/WM
Dual-In-Line Package
Plastic Chip Carrier
DS010802-3
DS010802-4
Top View
Order Number COP680C-XXX/V, COP880C-XXX/V,
COP980C-XXX/V or COP980CH-XXX/V
Top View
Order Number COP680C-XXX/N, COP880C-XXX/N,
COP980C-XXX/N or COP980CH-XXX/N
FIGURE 2. Connection Diagrams
3
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COP980C/COP981C/COP982C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
50 mA
60 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at any Pin
)
7V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
COP98xC; 0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter Condition
Operating Voltage
Min
Typ
Max
Units
98XC
2.3
4.0
4.0
6.0
V
V
V
98XCH
Power Supply Ripple (Note 2)
Supply Current
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz
(Note 3)
Peak to Peak
0.1 VCC
VCC = 6V, tc = 1 µs
6.0
4.4
2.2
1.4
mA
mA
mA
mA
VCC = 6V, tc = 2.5 µs
VCC = 4.0V, tc = 2.5 µs
VCC = 4.0V, tc = 10 µs
<
<
HALT Current
(Note 4)
VCC = 6V, CKI = 0 MHz
VCC = 4.0V, CKI = 0 MHz
0.7
0.4
8
5
µA
µA
Input Levels
RESET, CKI
Logic High
0.9 VCC
0.7 VCC
V
V
Logic Low
0.1 VCC
All Other Inputs
Logic High
V
V
Logic Low
0.2 VCC
+1.0
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
Output Current Levels
D Outputs
VCC = 6.0V
−1.0
−40
µA
µA
V
VCC = 6.0V, VIN = 0V
−250
0.35 VCC
Source
VCC = 4.5V, VOH = 3.8V
VCC = 2.3V, VOH = 1.6V
VCC = 4.5V, VOL = 1.0V
VCC = 2.3V, VOL = 0.4V
−0.4
−0.2
10
mA
mA
mA
mA
Sink
2
All Others
Source (Weak Pull-Up)
VCC = 4.5V, VOH = 3.2V
VCC = 2.3V, VOH = 1.6V
VCC = 4.5V, VOH = 3.8V
VCC = 2.3V, VOH = 1.6V
VCC = 4.5V, VOL = 0.4V
VCC = 2.3V, VOL = 0.4V
VCC = 6.0V
−10
−2.5
−0.4
−0.2
1.6
−110
−33
µA
µA
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
mA
mA
µA
0.7
TRI-STATE Leakage
Allowable Sink/Source
Current Per Pin
−1.0
+1.0
D Outputs (Sink)
All Others
15
3
mA
mA
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4
DC Electrical Characteristics (Continued)
COP98xC; 0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Maximum Input Current (Note 5)
Without Latchup (Room Temp)
RAM Retention Voltage, Vr
(Note 6)
Condition
Min
Typ
Max
Units
±
Room Temp
100
mA
500 ns Rise and
Fall Time (Min)
2.0
V
Input Capacitance
7
pF
pF
Load Capacitance on D2
1000
COP980C/COP981C/COP982C
Note 2: Rate of voltage change must be less than 0.5V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L, C and G ports TRI-STATE
CC
and tied to ground, all outputs low and tied to ground.
Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V and the pins will
CC
have sink current to V
when biased at voltages greater than V
(the pins do not have source current when biased at a voltage below V ). The effective
CC CC
CC
resistance to V
is 750Ω (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
CC
Note 6: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
AC Electrical Characteristics
0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
Crystal/Resonator or External
(Div-by 10)
Condition
Min
Typ
Max
Units
VCC ≥ 4.0V
1
DC
DC
DC
DC
60
12
8
µs
µs
µs
µs
%
2.3V ≤ VCC ≤ 4.0V
VCC ≥ 4.0V
2.5
3
R/C Oscillator Mode
(Div-by 10)
2.3V ≤ VCC ≤ 4.0V
fr = Max
7.5
40
CKI Clock Duty Cycle (Note 7)
Rise Time (Note 7)
Fall Time (Note 7)
Inputs
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
ns
ns
tSETUP
VCC ≥ 4.0V
200
500
60
ns
ns
ns
ns
2.3V ≤ VCC ≤ 4.0V
VCC ≥ 4.0V
tHOLD
2.3V ≤ VCC ≤ 4.0V
CL = 100 pF, RL = 2.2 kΩ
150
Output Propagation Delay
tPD1, tPD0
SO, SK
VCC ≥ 4.0V
0.7
1.75
1
µs
µs
µs
µs
ns
ns
2.3V ≤ VCC ≤ 4.0V
VCC ≥ 4.0V
All Others
2.3V ≤ VCC ≤ 4.0V
2.5
™
MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
20
56
Propagation Delay (tUPD
Input Pulse Width
)
220
ns
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width
tC
tC
tC
tC
1.0
µs
Note 7: Parameter characterized but not production tested.
5
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COP880C/COP881C/COP882C
Absolute Maximum Ratings (Note 8)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 8: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
50 mA
60 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at any Pin
)
7V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
COP88xC; −40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter Condition
Operating Voltage
Min
Typ
Max
6.0
Units
2.5
V
V
Power Supply Ripple (Note 9)
Supply Current
CKI = 10 MHz
CKI = 4 MHz
CKI = 4 MHz
CKI = 1 MHz
(Note 10)
Peak to Peak
0.1 VCC
VCC = 6V, tc = 1 µs
6.0
4.4
2.2
1.4
mA
mA
mA
mA
VCC = 6V, tc = 2.5 µs
VCC = 4.0V, tc = 2.5 µs
VCC = 4.0V, tc = 10 µs
<
HALT Current
(Note 11)
VCC = 6V, CKI = 0 MHz
VCC = 3.5V, CKI = 0 MHz
1
10
6
µA
µA
<
0.5
Input Levels
RESET, CKI
Logic High
0.9 VCC
0.7 VCC
V
V
Logic Low
0.1 VCC
All Other Inputs
Logic High
V
V
Logic Low
0.2 VCC
+2
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
Output Current Levels
D Outputs
VCC = 6.0V
−2
µA
µA
V
VCC = 6.0V, VIN = 0V
−40
−250
0.35 VCC
Source
VCC = 4.5V, VOH = 3.8V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOL = 1.0V
VCC = 2.5V, VOL = 0.4V
−0.4
−0.2
10
mA
mA
mA
mA
Sink
2
All Others
Source (Weak Pull-Up)
VCC = 4.5V, VOH = 3.2V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOH = 3.8V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOL = 0.4V
VCC = 2.5V, VOL = 0.4V
VCC = 6.0V
−10
−2.5
−0.4
−0.2
1.6
−110
−33
µA
µA
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
mA
mA
µA
0.7
TRI-STATE Leakage
Allowable Sink/Source
Current Per Pin
−2.0
+2.0
D Outputs (Sink)
15
3
mA
mA
All Others
Maximum Input Current (Note 12)
Without Latchup (Room Temp)
±
Room Temp
100
mA
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6
DC Electrical Characteristics (Continued)
COP88xC; −40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
RAM Retention Voltage, Vr
(Note 13)
Condition
500 ns Rise and
Fall Time (Min)
Min
Typ
Max
Units
2.0
V
Input Capacitance
7
pF
pF
Load Capacitance on D2
1000
COP880C/COP881C/COP882C
Note 9: Rate of voltage change must be less than 0.5V/ms.
Note 10: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 11: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L, C and G ports TRI-STATE
CC
and tied to ground, all outputs low and tied to ground.
Note 12: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V and the pins will
CC
have sink current to V
when biased at voltages greater than V
(the pins do not have source current when biased at a voltage below V ). The effective
CC CC
CC
resistance to V
is 750Ω (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
CC
Note 13: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
Crystal/Resonator or External
(Div-by 10)
Condition
Min
Typ
Max
Units
VCC ≥ 4.5V
1
DC
DC
DC
DC
60
12
8
µs
µs
µs
µs
%
<
2.5V ≤ VCC 4.5V
2.5
3
R/C Oscillator Mode
(Div-by 10)
VCC ≥ 4.5V
<
2.5V ≤ VCC 4.5V
7.5
40
CKI Clock Duty Cycle (Note 14)
Rise Time (Note 14)
Fall Time (Note 14)
Inputs
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
ns
ns
tSETUP
VCC ≥ 4.5V
200
500
60
ns
ns
ns
ns
<
2.5V ≤ VCC 4.5V
tHOLD
VCC ≥ 4.5V
<
2.5V ≤ VCC 4.5V
150
Output Propagation Delay
CL = 100 pF, RL = 2.2 kΩ
tPD1, tPD0
SO, SK
VCC ≥ 4.5V
0.7
1.75
1
µs
µs
µs
µs
ns
ns
<
2.5V ≤ VCC 4.5V
All Others
VCC ≥ 4.5V
<
2.5V ≤ VCC 4.5V
2.5
MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output
20
56
Propagation Delay (tUPD
Input Pulse Width
)
220
ns
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width
tC
tC
tC
tC
1.0
µs
Note 14: Parameter characterized but not production tested.
7
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Timing Diagram
DS010802-2
FIGURE 3. MICROWIRE/PLUS Timing
COP680C/COP681C/COP682C
Absolute Maximum Ratings (Note 16)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current Out of GND Pin (Sink)
Storage Temperature Range
Note 15: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
40 mA
48 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at Any Pin
)
6V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
COP68xC: −55˚C ≤ TA ≤ +125˚C unless otherwise specified
Parameter Condition
Operating Voltage
Min
Typ
Max
5.5
Units
4.5
V
V
Power Supply Ripple (Note 17)
Supply Current (Note 18)
CKI = 10 MHz
Peak to Peak
0.1 VCC
VCC = 5.5V, tc = 1 µs
VCC = 5.5V, tc = 2.5 µs
VCC = 5.5V, CKI = 0 MHz
8.0
4.4
30
mA
mA
µA
CKI = 4 MHz
<
HALT Current (Note 19)
Input Levels
10
RESET, CKI
Logic High
0.9 VCC
0.7 VCC
V
V
Logic Low
0.1 VCC
All Other Inputs
Logic High
V
V
Logic Low
0.2 VCC
+5
Hi-Z Input Leakage
Input Pullup Current
G Port Input Hysteresis
Output Current Levels
D Outputs
VCC = 5.5V
−5
µA
µA
V
VCC = 5.5V, VIN = 0V
−35
−300
0.35 VCC
Source
VCC = 4.5V, VOH = 3.8V
VCC = 4.5V, VOL = 1.0V
−0.35
9
mA
mA
Sink
All Others
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Allowable Sink/Source Current per Pin
D Outputs (Sink)
All Others
VCC = 4.5V, VOH = 3.2V
VCC = 4.5V, VOH = 3.2V
VCC = 4.5V, VOL = 0.4V
VCC = 5.5V
−9
−0.35
1.4
−120
+5.0
µA
mA
mA
µA
−5.0
12
mA
mA
2.5
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8
DC Electrical Characteristics (Continued)
COP68xC: −55˚C ≤ TA ≤ +125˚C unless otherwise specified
Parameter
Maximum Input Current (Room Temp)
without Latchup (Note 20)
RAM Retention Voltage, Vr (Note 21)
Input Capacitance
Condition
Min
Typ
Max
Units
±
Room Temp
100
mA
V
500 ns Rise and Fall Time (Min)
2.5
7
pF
pF
Load Capacitance on D2
1000
Note 16: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when
operating the device at absolute maximum ratings.
Note 17: Rate of voltage change must be less than 0.5V/ms.
Note 18: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 19: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L and G ports TRI-STATE
CC
and tied to ground, all outputs low and tied to ground.
Note 20: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V and the pins will
CC
have sink current to V
when biased at voltages greater than V
(the pins do not have source current when biased at a voltage below V ). The effective
CC CC
CC
resistance to V
is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
CC
Note 21: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
COP680C/COP681C/COP682C
AC Electrical Characteristics
−55˚C ≤ TA ≤ +125˚C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
Ext. or Crystal/Resonant
(Div-by 10)
Condition
Min
1
Typ
Max
DC
60
Units
µs
VCC ≥ 4.5V
CKI Clock Duty Cycle
(Note 22)
fr = Max
40
%
Rise Time (Note 22)
Fall Time (Note 22)
MICROWIRE Setup Time (tUWS
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
12
8
ns
ns
ns
ns
ns
)
20
56
MICROWIRE Hold Time (tUWH
MICROWIRE Output Valid
)
220
Time (tUPD
)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width
tC
tC
tC
tC
1
µs
Note 22: Parameter characterized but not production tested.
9
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Typical Performance Characteristics (−40˚C ≤ TA ≤ +85˚C)
Hall—IDD
Dynamic—IDD (Crystal Clock Option)
DS010802-16
DS010802-18
DS010802-20
DS010802-17
DS010802-19
DS010802-21
Port L/C/G Weak Pull-Up
Port L/C/G Push-Pull Source Current
Port L/C/G Push-Pull Sink Current
Port D Source Current
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10
Typical Performance Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued)
Port D Sink Current
DS010802-22
Pin Descriptions
Con-
Data
Port G Setup
VCC and GND are the power supply pins.
fig.
0
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunc-
tion with CKO). See Oscillator description.
0
1
0
1
Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
0
1
RESET is the master reset input. See Reset description.
1
Push-Pull One Output
PORT I is an 8-bit Hi-Z input port. The 28-pin device does not
have a full complement of Port I pins. The unavailable pins
are not terminated i.e., they are floating. A read operation for
these unterminated pins will return unpredictable values.
The user must ensure that the software takes this into ac-
count by either masking or restricting the accesses to bit
operations. The unterminated Port I pins will draw power
only when addressed.
Since G6 and G7 are input only pins, any attempt by the user
to configure them as outputs by writing a one to the configu-
ration register will be disregarded. Reading the G6 and G7
configuration bits will return zeros. The device will be placed
in the HALT mode by writing to the G7 bit in the G-port data
register.
Six pins of Port G have alternate features:
G0 INTR (an external interrupt)
PORT L is an 8-bit I/O port.
PORT C is a 4-bit I/O port.
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
Three memory locations are allocated for the L, G and C
ports, one each for data register, configuration register and
the input pins. Reading bits 4–7 of the C-Configuration reg-
ister, data register, and input pins returns undefined data.
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
There are two registers associated with the L and C ports: a
data register and a configuration register. Therefore, each L
and C I/O bit can be individually configured under software
control as shown below:
Pins G1 and G2 currently do not have any alternate func-
tions.
PORT D is an 8-bit output port that is preset high when
RESET goes low. Care must be exercised with the D2 pin
operation. At RESET, the external loads on this pin must
ensure that the output voltages stay above 0.9 VCC to pre-
vent the chip from entering special modes. Also, keep the
external loading on D2 to less than 1000 pF.
Con-
Data
Ports L and C Setup
fig.
0
0
1
0
1
Hi-Z Input (TRI-STATE Output)
Input with Pull-Up (Weak One Output)
Push-Pull Zero Output
0
1
1
Push-Pull One Output
Functional Description
On the 28-pin part, it is recommended that all bits of Port C
be configured as outputs.
Figure 1 shows the block diagram of the internal architec-
ture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each
other in implementing the instruction set of the device.
PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input
pins (G6, G7). All eight G-pins have Schmitt Triggers on the
inputs.
ALU AND CPU REGISTERS
There are two registers associated with the G port: a data
register and a configuration register. Therefore, each G port
bit can be individually configured under software control as
shown below:
The ALU can do an 8-bit addition, subtraction, logical or shift
operation in one cycle time.
There are five CPU registers:
A is the 8-bit Accumulator register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
11
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Functional Description (Continued)
B is the 8-bit address register, can be auto incremented or
decremented.
X is the 8-bit alternate address register, can be incremented
or decremented.
SP is the 8-bit stack pointer, points to subroutine stack (in
RAM).
DS010802-6
B, X and SP registers are mapped into the on chip RAM. The
B and X registers are used to address the on chip RAM. The
SP register is used to address the stack in RAM during
subroutine calls and returns.
RC ≥ 5X Power Supply Rise Time
FIGURE 4. Recommended Reset Circuit
OSCILLATOR CIRCUITS
PROGRAM MEMORY
Figure 5 shows the three clock oscillator configurations.
Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data. The
program memory is addressed by the 15-bit program
counter (PC). ROM can be indirectly read by the LAID in-
struction for table lookup.
A. CRYSTAL OSCILLATOR
The device can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.
Table 1 shows the component values required for various
standard crystal values.
DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the
instruction or indirectly by the B, X and SP registers.
B. EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKO is
available as a general purpose input and/or HALT restart
control.
The device has 128 bytes of RAM. Sixteen bytes of RAM are
mapped as “registers” that can be loaded immediately, dec-
remented or tested. Three specific registers: B, X and SP are
mapped into this space, the other bytes are available for
general usage.
C. R/C OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt
trigger oscillator. CKO is available as a general purpose
input and/or HALT restart control.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except the A & PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. A is not
memory mapped, but bit operations can be still performed on
it.
Table 2 shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
Note: RAM contents are undefined upon power-up.
RESET
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the ports L, G and C are
placed in the TRI-STATE mode and the Port D is set high.
The PC, PSW and CNTRL registers are cleared. The data
and configuration registers for Ports L, G and C are cleared.
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
DS010802-7
FIGURE 5. Crystal and R-C Connection Diagrams
OSCILLATOR MASK OPTIONS
The device can be driven by clock inputs between DC and
10 MHz.
TABLE 1. Crystal Oscillator Configuration, TA = 25˚C
R1
(kΩ)
0
R2
(MΩ)
1
C1
(pF)
30
C2
(pF)
CKI Freq
(MHz)
10
Conditions
30–36
30–36
100–150
VCC = 5V
VCC = 2.5V
VCC = 5V
0
1
30
4
5.6
1
200
0.455
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12
Functional Description (Continued)
TABLE 2. RC Oscillator Configuration, TA = 25˚C
R
C
CKI Freq.
(MHz)
Instr. Cycle
(µs)
Conditions
(kΩ)
3.3
5.6
6.8
(pF)
82
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
VCC = 5V
VCC = 5V
VCC = 5V
100
100
Note 23: (R/C Oscillator Configuration): 3k ≤ R ≤ 200k, 50 pF ≤ C ≤ 200 pF.
The device has three mask options for configuring the clock
input. The CKI and CKO pins are automatically configured
upon selecting a particular option.
ENI and ENTI bits select external and timer interrupt respec-
tively. Thus the user can select either or both sources to
interrupt the microcontroller when GIE is enabled.
•
•
•
Crystal (CKI/10); CKO for crystal configuration
External (CKI/10); CKO available as G7 input
R/C (CKI/10); CKO available as G7 input
IEDG selects the external interrupt edge (0 = rising edge,
1 = falling edge). The user can get an interrupt on both rising
and falling edges by toggling the state of IEDG bit after each
interrupt.
G7 can be used either as a general purpose input or as a
control input to continue from the HALT mode.
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two bits
to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
HALT MODE
The device supports a power saving mode of operation:
HALT. The controller is placed in the HALT mode by setting
the G7 data bit, alternatively the user can stop the clock
input. In the HALT mode all internal processor activities
including the clock oscillator are stopped. The fully static
architecture freezes the state of the controller and retains all
information until continuing. In the HALT mode, power re-
quirements are minimal as it draws only leakage currents
and output current. The applied voltage (VCC) may be de-
creased down to Vr (minimum RAM retention voltage) with-
out altering the state of the machine.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other inter-
rupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address 00FFH and resumes execution from
that address. This process takes 7 cycles to complete. At the
end of the interrupt subroutine, any of the following three
instructions return the processor back to the main program:
RET, RETSK or RETI. Either one of the three instructions will
pop the stack into the program counter (PC). The stack
pointer is then incremented twice. The RETI instruction ad-
ditionally sets the GIE bit to re-enable further interrupts.
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET line reinitializes the
microcontroller and starts executing from the address
0000H. A low to high transition on the CKO pin (only if the
external or R/C clock option selected) causes the microcon-
troller to continue with no reinitialization from the address
following the HALT instruction. This also resets the G7 data
bit.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
Note: There is always the possibility of an interrupt occurring during an
instruction which is attempting to reset the GIE bit or any other inter-
rupt enable bit. If this occurs when a single cycle instruction is being
used to reset the interrupt enable bit, the interrupt enable bit will be
reset but an interrupt may still occur. This is because interrupt process-
ing is started at the same time as the interrupt bit is being reset. To
avoid this scenario, the user should always use a two, three or four
cycle instruction to reset interrupt enable bits.
INTERRUPTS
There are three interrupt sources, as shown below.
A maskable interrupt on external G0 input (positive or nega-
tive edge sensitive under software control)
A maskable interrupt on timer underflow or timer capture
A non-maskable software/error interrupt on opcode zero
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
13
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Functional Description (Continued)
DS010802-8
FIGURE 6. Interrupt Block Diagram
where,
DETECTION OF ILLEGAL CONDITIONS
The device contains a hardware mechanism that allows it to
detect illegal conditions which may occur from coding errors,
noise and “brown out” voltage drop situations. Specifically it
detects cases of executing out of undefined ROM area and
unbalanced stack situations.
tC is the instruction cycle clock.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The devoce may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 8 shows how
two COP880C microcontrollers and several peripherals may
be interconnected using the MICROWIRE/PLUS arrange-
ment.
Reading an undefined ROM location returns 00 (hexadeci-
mal) as its contents. The opcode for a software interrupt is
also “00”. Thus a program accessing undefined ROM will
cause a software interrupt.
Reading an undefined RAM location returns an FF (hexa-
decimal). The subroutine stack grows down for each subrou-
tine call. By initializing the stack pointer to the top of RAM,
the first unbalanced return instruction will cause the stack
pointer to address undefined RAM. As a result the program
will attempt to execute from FFFF (hexadecimal), which is an
undefined ROM location and will trigger a software interrupt.
Master MICROWIRE/PLUS Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE/
PLUS Master always initiates all data exchanges. (See Fig-
ure 8). The MSEL bit in the CNTRL register must be set to
enable the SO and SK functions onto the G Port. The SO
and SK pins must also be selected as outputs by setting
appropriate bits in the Port G configuration register. Table 4
summarizes the bit settings required for Master mode of
operation.
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with any of National
Semiconductor’s MICROWIRE peripherals (i.e. A/D convert-
ers, display drivers, EEPROMS, etc.) and with other micro-
controllers which support the MICROWIRE/PLUS interface.
It consists of an 8-bit serial shift register (SIO) with serial
data input (SI), serial data output (SO) and serial shift clock
(SK). Figure 7 shows the block diagram of the MICROWIRE/
PLUS interface.
SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by appropriately
setting up the Port G configuration register. Table 4 summa-
rizes the settings required to enter the Slave mode of opera-
tion.
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS
interface with the internal clock source is called the Master
mode of operation. Similarly, operating the MICROWIRE/
PLUS interface with an external shift clock is called the Slave
mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated. (See Figure 8.)
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. The SK
clock rate is selected by the two bits, SL0 and SL1, in the
CNTRL register. Table 3 details the different clock rates that
may be selected.
TABLE 3.
SL1
0
SL0
SK Cycle Time
0
1
x
2tC
4tC
8tC
0
1
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14
Functional Description (Continued)
TABLE 4.
G4
G5
G4
G5
G6
Config. Config.
Fun.
Fun. Fun.
Operation
Bit
Bit
1
1
SO
Int.
SK
SI
SI
SI
SI
MICROWIRE
Master
0
1
0
1
0
0
TRI-STATE
SO
Int.
SK
MICROWIRE
Master
Ext.
SK
MICROWIRE
Slave
TRI-STATE
Ext.
SK
MICROWIRE
Slave
DS010802-9
TIMER/COUNTER
FIGURE 7. MICROWIRE/PLUS Block Diagram
The device has a powerful 16-bit timer with an associated
16-bit register enabling them to perform extensive timer
functions. The timer T1 and its register R1 are each orga-
nized as two 8-bit read/write registers. Control bits in the
register CNTRL allow the timer to be started and stopped
under software control. The timer-register pair can be oper-
ated in one of three possible modes. Table 5 details various
timer operating modes and their requisite control settings.
MODE 1. TIMER WITH AUTO-LOAD REGISTER
In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the reg-
ister R1 gets automatically reloaded into the timer which
continues to count down. The timer underflow can be pro-
grammed to interrupt the microcontroller. A bit in the control
register CNTRL enables the TIO (G3) pin to toggle upon
timer underflows. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See Figure 9.)
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRL program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt. (See Figure 9)
MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure external fre-
quencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occur-
rence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRL allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger edge.
(See Figure 10.)
15
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Functional Description (Continued)
DS010802-10
FIGURE 8. MICROWIRE/PLUS Application
TABLE 5. Timer Operating Modes
CNTRL
Bits
Timer
Operation Mode
T Interrupt
Counts
7 6 5
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
On
External Counter W/Auto-Load Reg.
External Counter W/Auto-Load Reg.
Not Allowed
Timer Underflow
Timer Underflow
Not Allowed
TIO Pos. Edge
TIO Neg. Edge
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Timer W/Auto-Load Reg.
Timer W/Auto-Load Reg./Toggle TIO Out
Timer W/Capture Register
Timer W/Capture Register
Timer Underflow
Timer Underflow
TIO Pos. Edge
TIO Neg. Edge
tC
tC
tC
tC
DS010802-12
DS010802-11
FIGURE 10. Timer Capture Mode Block Diagram
FIGURE 9. Timer/Counter Auto
Reload Mode Block Diagram
TIMER PWM APPLICATION
Figure 11 shows how a minimal component D/A converter
can be built out of the Timer-Register pair in the Auto-Reload
mode. The timer is placed in the “Timer with auto reload”
mode and the TIO pin is selected as the timer output. At the
outset the TIO pin is set high, the timer T1 holds the on time
and the register R1 holds the signal off time. Setting TRUN
bit starts the timer which counts down at the instruction cycle
rate. The underflow toggles the TIO output and copies the off
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16
DIRECT
Functional Description (Continued)
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
time into the timer, which continues to run. By alternately
loading in the on time and the off time at each successive
interrupt a PWM frequency can be easily generated.
IMMEDIATE
The instruction contains an 8-bit immediate field as the
operand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically increments
or decrements the B or X register after executing the instruc-
tion.
RELATIVE
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from −31 to +32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruc-
tion). There are no “pages” when using JP, all 15 bits of PC
are used.
DS010802-13
FIGURE 11. Timer Application
Control Registers
CNTRL REGISTER (ADDRESS X’00EE)
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
The Timer and MICROWIRE/PLUS control register contains
the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by
Address
Contents
IEDG
External interrupt edge polarity select
(0 = rising edge, 1 = falling edge)
00 to 6F On Chip RAM Bytes
70 to 7F Unused RAM Address Space (Reads as all Ones)
80 to BF Expansion Space for future use
MSEL
Enable MICROWIRE/PLUS functions SO and
SK
C0 to
CF
Expansion Space for I/O and Registers
TRUN
TC3
Start/Stop the Timer/Counter (1 = run, 0 = stop)
Timer input edge polarity select (0 = rising
edge, 1 = falling edge)
D0 to
DF
On Chip I/O and Registers
D0
D1
Port L Data Register
TC2
TC1
Selects the capture mode
Selects the timer mode
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
D2
TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0
D3
BIT
7
BIT
0
D4
Port G Data Register
D5
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
D6
PSW REGISTER (ADDRESS X’00EF)
D7
The PSW register contains the following select bits:
D8
GIE
ENI
Global interrupt enable
External interrupt enable
D9
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
DA
BUSY MICROWIRE/PLUS busy shifting
IPND External interrupt pending
ENTI Timer interrupt enable
DB
DC
DD–DF
Port D Data Register
Reserved for Port D
TPND Timer interrupt pending
E0 to EF On Chip Functions and Registers
C
Carry Flag
E0–E7
E8
Reserved for Future Parts
Reserved
HC
Half carry Flag
E9
MICROWIRE/PLUS Shift Register
Timer Lower Byte
HC
C
TPND ENTI
IPND BUSY ENI
GIE
EA
BIT
7
BIT
0
EB
Timer Upper Byte
EC
ED
EE
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register
Addressing Modes
EF
REGISTER INDIRECT
F0 to FF On Chip RAM Mapped as Registers
This is the “normal” mode of addressing. The operand is the
memory addressed by the B register or X register.
FC
FD
X Register
SP Register
17
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PU upper 7 bits of PC
PL lower 8 bits of PC
Memory Map (Continued)
Address
Contents
C
1-bit of PSW register for carry
FE
B Register
HC Half Carry
GIE 1-bit of PSW register for global interrupt enable
Reading unused memory locations below 7FH will return all
ones. Reading other unused memory locations will return
undefined data.
Symbols
[B]
[X]
Memory indirectly addressed by B register
Memory indirectly addressed by X register
Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
Mem Direct address memory or [B]
MemI Direct address memory or [B] or Immediate data
Imm 8-bit Immediate data
Reg
Register memory: addresses F0 to FF (Includes B, X
and SP)
A
B
X
8-bit Accumulator register
8-bit Address register
8-bit Address register
Bit
←
↔
Bit number (0 to 7)
Loaded with
Exchanged with
SP 8-bit Stack pointer register
PC 15-bit Program counter register
Instruction Set
←
ADD
ADC
add
A
A
A + MemI
←
←
add with carry
A + MemI + C, C
Carry
Carry
←
HC
Half Carry
←
←
SUBC
subtract with carry
A
A + MemI +C, C
←
HC
Half Carry
A and MemI
A or MemI
←
AND
OR
Logical AND
A
A
A
←
←
Logical OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
Logical Exclusive-OR
IF equal
A xor MemI
Compare A and MemI, Do next if A = MemI
>
Compare A and MemI, Do next if A MemI
IF greater than
IF B not equal
Decrement Reg. ,skip if zero
Set bit
≠
Do next if lower 4 bits of B Imm
←
Reg
1 to bit,
Reg − 1, skip if Reg goes to 0
Mem (bit= 0 to 7 immediate)
RBIT
IFBIT
Reset bit
If bit
0 to bit,
Mem
If bit,
Mem is true, do next instr.
↔
←
X
Exchange A with memory
Load A with memory
A
A
Mem
LD A
LD mem
LD Reg
X
MemI
←
Load Direct memory Immed.
Load Register memory Immed.
Exchange A with memory [B]
Exchange A with memory [X]
Load A with memory [B]
Load A with memory [X]
Load Memory Immediate
Clear A
Mem
Reg
Imm
Imm
←
↔
←
←
←
←
±
B 1)
A
[B]
[X]
[B]
[X]
(B
(X
(B
(X
↔
±
X 1)
X
A
←
±
B 1)
LD A
LD A
LD M
CLRA
INCA
DECA
LAID
DCORA
RRCA
A
←
±
X 1)
A
←
←
B 1)
±
[B]
Imm (B
←
A
A
A
A
A
C
0
←
←
←
←
→
Increment A
A + 1
A − 1
Decrement A
Load A indirect from ROM
DECIMAL CORRECT A
ROTATE A RIGHT THRU C
ROM(PU,A)
BCD correction (follows ADC, SUBC)
→
→
→
A0 C
A7
…
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18
Instruction Set (Continued)
Instruction Set (Continued)
↔
A3 … A0
SWAPA
SC
Swap nibbles of A
A7 … A4
←
←
←
Set C
C
C
1, HC
1
0
←
0, HC
RC
Reset C
IFC
If C
If C is true, do next instruction
IFNC
JMPL
JMP
JP
If not C
If C is not true, do next instruction
←
ii (ii = 15 bits, 0 to 32k)
Jump absolute long
Jump absolute
Jump relative short
Jump subroutine long
Jump subroutine
Jump indirect
PC
PC11..0
←
i (i = 12 bits)
PC + r (r is −31 to +32, not 1)
←
PC
←
←
←
←
←
ii
JSRL
JSR
[SP]
[SP]
PL,[SP-1]
PL,[SP-1]
PU,SP-2,PC
←
PU,SP-2,PC11.. 0
i
←
ROM(PU,A)
JID
PL
←
←
←
←
RET
RETSK
RETI
INTR
NOP
Return from subroutine
Return and Skip
Return from Interrupt
Generate an interrupt
No operation
SP+2,PL
SP+2,PL
SP+2,PL
[SP],PU
[SP],PU
[SP],PU
[SP-1]
[SP-1],Skip next instruction
←
←
←
[SP-1],GIE
1
←
←
←
PU,SP-2,PC 0FF
[SP]
PL,[SP−1]
←
PC
PC + 1
19
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Instruction Set (Continued)
0 – 3
B i t s
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20
See the BYTES and CYCLES per INSTRUCTION table for
details.
Instruction Execution Time
Most instructions are single byte (with immediate addressing
mode instruction taking two bytes).
BYTES and CYCLES per
INSTRUCTION
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Most single instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
Arithmetic and Logic Instructions
[B]
Direct
3/4
Immed.
2/2
ADD
ADC
SUBC
AND
OR
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
2/2
3/4
2/2
3/4
2/2
3/4
2/2
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
3/4
2/2
3/4
2/2
3/4
2/2
1/3
3/4
3/4
3/4
1/1
1/1
1/1
Memory Transfer Instructions
Register
Indirect
[B] [X]
Register Indirect
Auto Incr & Decr
Direct
Immed.
[B+, B−]
1/2
[X+, X−]
1/3
X A, (Note 24)
LD A, (Note 24)
LD B,Imm
1/1 1/3
1/1 1/3
2/3
2/3
2/2
1/1
2/3
1/2
1/3
<
(If B 16)
>
(If B 15)
LD B,Imm
LD Mem,Imm
LD Reg,Imm
2/2
3/3
2/2
2/3
>
Memory location addressed by B or X or directly.
Note 24:
=
Instructions Using A & C
JMP
JP
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
1/1
JSRL
JSR
JID
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
RET
RETSK
RETI
INTR
NOP
RC
The following table shows the instructions assigned to un-
used opcodes. This table is for information only. The opera-
tions performed are subject to change without notice. Do not
use these opcodes.
IFC
IFNC
Transfer of Control Instructions
JMPL
3/4
21
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•
OTP/EPROM Programmer Support: Covering needs
from engineering prototype, pilot production to full pro-
duction environments.
BYTES and CYCLES per
INSTRUCTION (Continued)
iceMASTER (IM) IN-CIRCUIT EMULATION
Unused
Opcode
60
Instruction
Unused
Opcode
A9
Instruction
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool developed and marketed by Met-
aLink Corporation to support the whole COP8 family of
products. National is a resale vendor for these products.
NOP
NOP
NOP
61
AF
LD A, [B]
→
HC
62
NOP
B1
C
See Figure 12 for configuration.
63
NOP
B4
NOP
NOP
The iceMASTER IM-COP8/400 with its device specific
COP8 Probe provides a rich feature set for developing,
testing and maintaining product:
67
NOP
B5
8C
RET
B7
X A, [X]
NOP
•
Real-time in-circuit emulation; full 2.4V–5.5V operation
range, full DC-10 MHz clock. Chip options are program-
mable or jumper selectable.
99
NOP
B9
9F
LD [B], #i
X A, [B]
NOP
BF
LD A, [X]
A7
•
•
Direct connection to application board by package com-
patible socket or surface mount assembly.
A8
Full 32 kbyte of loadable programming space that over-
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on the
probe as necessary.
Option List
The mask programmable options are listed out below. The
options are programmed at the same time as the ROM
pattern to provide the user with hardware flexibility to use a
variety of oscillator configuration.
•
Full 4k frame synchronous trace memory. Address, in-
struction, and 8 unspecified, circuit connectable trace
lines. Display can be HLL source (e.g., C source), as-
sembly or mixed.
OPTION 1: CKI INPUT
•
•
A full 64k hardware configurable break, trace on, trace off
control, and pass count increment events.
= 1 Crystal (CKI/10) CKO for crystal configuration
= 2 External (CKI/10) CKO available as G7 input
Tool
set
integrated
interactive
symbolic
= 3 R/C
(CKI/10) CKO available as G7 input
debugger—supports both assembler (COFF) and C
Compiler (.COD) linked object formats.
OPTION 2: BONDING
= 1 44-Pin PLCC
= 2 40-Pin DIP
•
•
•
•
Real time performance profiling analysis; selectable
bucket definition.
Watch windows, content updated automatically at each
execution break.
= 3 28-Pin SO
= 4 28-Pin DIP
Instruction by instruction memory/register changes dis-
played on source window when in single step operation.
The following option information is to be sent to National
along with the EPROM.
Single base unit and debugger software reconfigurable to
support the entire COP8 family; only the probe personal-
ity needs to change. Debugger software is processor
customized, and reconfigured from a master model file.
Option Data
Option 1 Value__is: CKI Input
Option 2 Value__is: COP Bonding
•
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
•
•
Halt/Idle mode notification.
Development Support
On-line HELP customized to specific processor using
master model file.
SUMMARY
™
•
iceMASTER
: IM-COP8/400—Full feature in-circuit
•
Includes a copy of COP8-DEV-IBMA assembler and
linker SDK.
emulation for all COP8 products. A full set of COP8 Basic
and Feature Family device and package specific probes
are available.
•
•
COP8 Debug Module: Moderate cost in-circuit emulation
and development programming unit.
COP8
Evaluation
and
Programming
Unit:
EPU-COP880C—low cost In-circuit simulation and de-
velopment programming unit.
•
•
Assembler: COP8-DEV-IBMA. A DOS installable cross
development Assembler, Linker, Librarian and Utility Soft-
ware Development Tool Kit.
C Compiler: COP8C. A DOS installable cross develop-
ment Software Tool Kit.
www.national.com
22
Development Support (Continued)
iceMASTER Probe
MHW-880C20DWPC
MHW-880C28DWPC
MHW-880CJ40DWPC
MHW-880CJ44PWPC
DIP to SO Adapters
MHW-SOIC20
20 DIP
28 DIP
40 DIP
44 PLCC
IM Order Information
Base Unit
IM-COP8/400-1
iceMASTER base unit,
110V power supply
iceMASTER base unit,
220V power supply
IM-COP8/400-2
20 SO
28 DIP
MHW-SOIC28
DS010802-24
FIGURE 12. COP8 iceMASTER Environment
23
www.national.com
•
•
Debugger software is processor customized, and recon-
figured from a master model file.
Development Support (Continued)
iceMASTER DEBUG MODULE (DM)
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
The iceMASTER Debug Module is a PC based, combination
in-circuit emulation tool and COP8 based OTP/EPROM pro-
gramming tool developed and marketed by MetaLink Corpo-
ration to support the whole COP8 family of products. Na-
tional is a resale vendor for these products.
•
•
Halt/Idle mode notification.
Programming menu supports full product line of program-
mable OTP and EPROM COP8 products. Program data
is taken directly from the overlay RAM.
See Figure 13 for configuration.
•
Programming of 44 PLCC and 68 PLCC parts requires
external programming. adapters.
The iceMASTER Debug Module is a moderate cost devel-
opment tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product fami-
lies. Summary of features is as follows:
•
•
Includes wallmount power supply.
On-board VPP generator from 5V input or connection to
external supply supported. Rquires VPP level adjustment
per the family programming specification (correct level is
provided on an on-screen pop-down display).
•
Real-time in-circuit emulation; full operating voltage
range operation, full DC-10 MHz clock.
•
•
On-line HELP customized to specific processor using
master model file.
•
All processor I/O pins can be cabled to an application
development board with package compatible cable to
socket and surface mount assembly.
Includes a copy of COP8-DEV-IBMA assembler and
linker SDK.
•
•
•
Full 32 kbyte of loadable programming space that over-
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
DM Order Information
Debug Model Unit
COP8-DM/880C
Cable Adapters
100 frames of synchronous trace memory. The display
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the
trace memory.
DM-COP8/20D
20 DIP
Configured break points; uses INTR instruction which is
modestly intrusive.
DM-COP8/28D
28 DIP
DM-COP8/40D
40 DIP
•
•
Software—only supported features are selectable.
DM-COP8/44P
44 PLCC
Tool
set
integrated
interactive
symbolic
debugger—supports both assembler (COFF) and C
Compiler (.COD) SDK linked object formats.
DIP to SO Adapters
DM-COP8/20D-SO
DM-COP8/28D-SO
20 SO
28 SO
•
Instruction by instruction memory/register changes dis-
played when in single step operation.
DS010802-25
FIGURE 13. COP8-DM Environment
www.national.com
24
•
Tool
set
integrated
interactive
symbolic
Development Support (Continued)
debugger—supports both assembler (COFF) and C
Compiler (.COD) SDK linked object formats.
iceMASTER EVALUATION PROGRAMMING UNIT (EPU)
The iceMASTER EPU-COP880C is a PC based, in-circuit
simulation tool to support the feature family COP8 products.
•
•
•
•
Instruction by instruction memory/register changes dis-
played when in single step operation.
See Figure 14 for configuration.
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
The simulation capability is a very low cost means of evalu-
ating the general COP8 architecture. In addition, the EPU
has programming capability, with added adapters, for pro-
gramming the whole COP8 product family of OTP and
EPROM products. The product includes the following fea-
tures:
Halt/Idle mode notification. Restart requires special han-
dling.
Programming menu supports full product line of program-
mable OTP and EPROM COP8 products. Only a 40 ZIF
socket is available on the EPU unit. Adapters are avail-
able for other part package configurations.
•
Non-real-time in-circuit simulation. Program overlay
memory is PC resident; instructions are downloaded over
RS-232 as executed. Approximate performance is
20 kHz.
•
•
Integral wall mount power supply provides 5V and devel-
ops the required VPP to program parts.
Includes a copy of COP8-DEV-IBMA assembler, linker
SDK.
•
•
Includes a 40 pin DIP cable adapter. Other target pack-
ages are not supported. All processor I/O pins are cabled
to the application development environment.
EPU Order Information
Evaluation Programming Unit
Full 32 kbyte of loadable programmable space that over-
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
EPU-COP880C
Evaluation Programming Unit
with debugger and programmer
control software with 40 ZIF
programming socket.
•
•
On-chip timer and WATCHDOG execution are not well
synchronized to the instruction simulation.
100 frames of synchronous trace memory. The display
can be HLL source (e.g., C source), assembly or mixed.
The most recent history prior to a break is available in the
trace memory.
General Programming Adapters
COP8-PGMA-DS
28 and 20 DIP and SOIC adapter
COP8-PGMA-DS44P 28 and 20 DIP and SOIC plus 44
PLCC adapter
•
•
Up to eight software configured break points; uses INTR
instruction which is modestly intrusive.
Common look-feel debugger software across all Met-
aLink products—only supported features are selectable.
DS010802-26
FIGURE 14. EPU-COP8 Tool Environment
25
www.national.com
COP8 C COMPILER
Development Support (Continued)
A C Compiler is developed and marketed by Byte Craft
Limited. The COP8C compiler is a fully integrated develop-
ment tool specifically designed to support the compact em-
bedded configuration of the COP8 family of products.
COP8 ASSEMBLER/LINKER SOFTWARE
DEVELOPMENT TOOL KIT
National Semiconductor offers a relocateable COP8 macro
cross assembler, linker, librarian and utility software devel-
opment tool kit. Features are summarized as follows:
Features are summarized as follows:
•
ANSI C with some restrictions and extensions that opti-
mize development for the COP8 embedded application.
•
•
•
•
•
•
•
•
Basic and Feature Family instruction set by “device” type.
Nested macro capability.
#
•
BITS data type extension. Register declaration pragma
Extensive set of assembler directives.
Supported on PC/DOS platform.
with direct bit level definitions.
•
•
C language support for interrupt routines.
Generates National standard COFF output files.
Integrated Linker and Librarian.
Expert system, rule based code geration and optimiza-
tion.
•
Performs consistency checks against the architectural
definitions of the target COP8 device.
Integrated utilities to generate ROM code file outputs.
DUMPCOFF utility.
•
•
Generates program memory code.
This product is integrated as a part of MetaLink tools as a
development kit, fully supported by the MetaLink debugger.
It may be ordered separately or it is bundled with the Met-
aLink products at no additional cost.
Supports linking of compiled object or COP8 assembled
object formats.
•
•
Global optimization of linked code.
Symbolic debug load format fully sourced level supported
by the MetaLink debugger.
Order Information
Assembler SDK:
INDUSTRY WIDE OTP/EPROM PROGRAMMING
SUPPORT
COP8-DEV-IBMA Assembler SDK on installable 3.5"
PC/DOS Floppy Disk Drive format.
Periodic upgrades and most recent
version is available on National’s
BBS and Internet.
Programming support, in addition to the MetaLink develop-
ment tools, is provided by a full range of independent ap-
proved vendors to meet the needs from the engineering
laboratory to full production.
Approved List
Manufacturer
North
America
Europe
Asia
BP
(800) 225-2102
(713) 688-4600
Fax: (713) 688-0920
(800) 426-1045
(206) 881-6444
Fax: (206) 882-1043
(510) 623-8860
+49-8152-4183
+852-234-16611
+852-2710-8121
Microsystems
+49-8856-932616
Data I/O
+44-0734-440011
Call Asia
Call
North America
HI–LO
+886-2-764-0215
Fax: +886-2-756-6403
ICE
(800) 624-8949
(919) 430-7915
(800) 638-2423
(602) 926-0797
Fax: (602) 693-0681
(408) 263-6667
+44-1226-767404
Fax: 0-1226-370-434
+49-80 9156 96-0
Fax: +49-80 9123 86
Technology
MetaLink
+852-737-1800
Systems
General
+41-1-9450300
+886-2-917-3005
Fax: +886-2-911-1283
Needhams
(916) 924-8037
Fax: (916) 924-8065
www.national.com
26
DIAL-A-HELPER via FTP
Development Support (Continued)
ftp nscmicro.nsc.com
AVAILABLE LITERATURE
user:
anonymous
For more information, please see the COP8 Basic Family
User’s Manual, Literature Number 620895, COP8 Feature
Family User’s Manual, Literature Number 620897 and Na-
tional’s Family of 8-bit Microcontrollers COP8 Selection
Guide, Literature Number 630009.
@
username yourhost.site.domain
password:
DIAL-A-HELPER via WorldWide Web Browser
ftp://nscmicro.nsc.com
DIAL-A-HELPER SERVICE
National Semiconductor on the WorldWide Web
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Infor-
mation System that may be accessed as a Bulletin Board
System (BBS) via data modem, as an FTP site on the
Internet via standard FTP client application or as an FTP site
on the Internet using a standard Internet browser such as
Netscape or Mosaic.
See us on the WorldWide Web at: http://www.national.com
CUSTOMER RESPONSE CENTER
Complete product information and technical support is avail-
able from National’s customer response centers.
CANADA/U.S.: Tel:
email:
(800)272-9959
@
support tevm2.nsc.com
The Dial-A-Helper system provides access to an automated
information storage and retrieval system . The system capa-
bilities include a MESSAGE SECTION (electronic mail,
when accessed as a BBS) for communications to and from
the Microcontroller Applications Group and a FILE SECTION
which consists of several file areas where valuable applica-
tion software and utilities could be found.
@
EUROPE:
email:
europe.support nsc.com
Deutsch Tel:
English Tel:
Français Tel:
Italiano Tel:
Tel:
+49 (0) 180-530 85 85
+49 (0) 180-532 78 32
+49 (0) 180-532 93 58
+49 (0) 180-534 16 80
+81-043-299-2309
(+86) 10-6856-8601
(+86) 21-6415-4092
(+852) 2737-1600
(+82) 2-3771-6909
(+60-4) 644-9061
JAPAN:
DIAL-A-HELPER BBS via a Standard Modem
S.E. ASIA:
Beijing Tel:
Shanghai Tel:
Hong Kong Tel:
Korea Tel:
Malaysia Tel:
Singapore Tel:
Taiwan Tel:
Tel:
Modem:
CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427
EUROPE:
Baud:
(+49) 0-8141-351332
14.4k
(+65) 255-2226
Set-Up:
Length:
Parity:
8-Bit
None
1
+886-2-521-3288
AUSTRALIA:
INDIA:
(+61) 3-9558-9999
(+91) 80-559-9467
Stop Bit:
Tel:
Operation:
24 Hours, 7 Days
27
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
Small Outline Molded Dual-In-Line Package (M)
Order Number COP882C-XXX/WM, COP982C-XXX/WM, COP682C-XXX/WM or COP982CH-XXX/WM
NS Package Number M20B
Small Outline Molded Dual-In-Line Package (M)
Order Number COP881C-XXX/WM, COP981C-XXX/WM, COP681C-XXX/WM or COP981CH-XXX/WM
NS Package Number M28B
www.national.com
28
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number COP882C-XXX/N, COP682C-XXX/N, COP982C-XXX/N or COP982CH-XXX/N
NS Package Number N20B
Molded Dual-In-Line Package (N)
Order Number COP881C-XXX/N, COP681C-XXX/N, COP981C-XXX/N or COP981CH-XXX/N
NS Package Number N28B
29
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number COP880C-XXX/N, COP680C-XXX/N, COP980C-XXX/N or COP980CH-XXX/N
NS Package Number N40A
Plastic Leaded Chip Carrier (V)
Order Number COP880C-XXX/V, COP680C-XXX/V, COP980C-XXX/V or COP980CH-XXX/V
NS Package Number V44A
www.national.com
30
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 180-530 85 86
Email: support@nsc.com
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
COP881CMHD-1
IC 8-BIT, UVPROM, 10 MHz, MICROCONTROLLER, CDIP28, WINDOWED, CERAMIC, DIP-28, Microcontroller
TI
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