COP888CG-XXX/V [NSC]
8-Bit Microcontroller with UART and Three Multi-Function Timers; 8位微控制器的UART及三幅多功能定时器
| 型号： | COP888CG-XXX/V |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit Microcontroller with UART and Three Multi-Function Timers |
| 文件： | 总42页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1996
COP884CG/COP888CG 8-Bit Microcontroller
with UART and Three Multi-Function Timers
Y
Schmitt trigger inputs on Port G
General Description
The COP888 family of microcontrollers uses an 8-bit single
Y
Packages:
Ð 44 PLCC with 40 I/O pins
chip core architecture fabricated with National Semiconduc-
Ð 40 DIP with 36 I/O pins
Ð 28 DIP with 24 I/O pins
2
tor’s M CMOSTM process technology. The COP888CG is a
member of this expandable 8-bit core processor family of
Ð 28 SO with 24 I/O pins
microcontrollers.
(Continued)
CPU/Instruction Set Feature
Y
Key Features
Y
1 ms instruction cycle time
Full duplex UART
Y
Fourteen multi-source vectored interrupts servicing
Ð External interrupt with selectable edge
Ð Idle timer T0
Y
Three 16-bit timers, each with two 16-bit registers sup-
porting:
Ð Processor independent PWM mode
Ð External event counter mode
Ð Input capture mode
Ð Three timers (each with 2 interrupts)
Ð MICROWIRE/PLUS
Ð Multi-Input WAke Up
Ð Software trap
Ð UART (2)
Y
Y
Y
Quiet design (low radiated emissions)
4 kbytes of on-chip ROM
192 bytes of on-chip RAM
Ð Default VIS (default interrupt)
Versatile and easy to use instruction set
8-bit Stack Pointer (SP)Ðstack in RAM
Two 8-bit register indirect data memory pointers (B, X)
Y
Y
Y
Additional Peripheral Features
Y
Idle timer
Y
Multi-Input Wake Up (MIWU) with optional interrupts (8)
Y
Two analog comparators
WATCHDOGTM and Clock Monitor logic
Fully Static CMOS
Y
Y
Y
Y
k
1 mA)
Low current drain (typically
Y
MICROWIRE/PLUSTM serial I/O
Single supply operation: 2.5V to 6.0V
b
a
Temperature range: 40 C to 85 C
§
§
I/O Features
Y
Memory mapped I/O
Development Support
Y
Y
Software selectable I/O options (TRI-STATE output,
É
push-pull output, weak pull-up input, high impedance in-
put)
Emulation and OTP devices
Y
Real time emulation and full program debug offered by
MetaLink Development System
Y
High current outputs
Block Diagram
TL/DD/9765–1
FIGURE 1. Block Diagram
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
2
MICROWIRE/PLUSTM, M CMOSTM, COP8TM microcontrollers, MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation.
iceMASTERTM is a trademark of MetaLink Corporation.
C
1996 National Semiconductor Corporation
TL/DD/9765
RRD-B30M106/Printed in U. S. A.
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General Description (Continued)
They are fully static parts, fabricated using double-metal sili-
con gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, three 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), full duplex
UART, two comparators, and two power savings modes
(HALT and IDLE), both with a multi-sourced wakeup/inter-
rupt capability. This multi-sourced interrupt capability may
also be used independent of the HALT or IDLE modes.
Each I/O pin has software selectable configurations. The
device operates over a voltage range of 2.5V to 6V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum of 1 ms per instruction rate.
The device has reduced EMI emissions. Low radiated emis-
sions are achieved by gradual turn-on output drivers and
internal I
filters on the chip logic and crystal oscillator.
CC
Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
TL/DD/9765–2
Top View
Order Number COP888CG-XXX/V
See NS Plastic Chip Package Number V44A
TL/DD/9765–4
Top View
Order Number COP888CG-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
TL/DD/9765–5
Top View
Order Number COP884CG-XXX/N or COP884CG-XXX/WM
See NS Molded Package Number N28A OR M28B
FIGURE 2a. Connection Diagrams
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2
Connection Diagrams (Continued)
Pinouts for 28-, 40- and 44-Pin Packages
28-Pin
Pack.
40-Pin
Pack.
44-Pin
Pack.
Port
L0
Type
I/O
Alt. Fun
MIWU
Alt. Fun
11
12
13
14
15
16
17
18
17
18
19
20
21
22
23
24
17
18
19
20
25
26
27
28
L1
L2
L3
L4
L5
L6
L7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
MIWU
CKX
TDX
RDX
T2A
T2B
T3A
T3B
G0
G1
G2
G3
G4
G5
G6
G7
I/O
INT
25
26
27
28
1
35
36
37
38
3
39
40
41
42
3
WDOUT
I/O
T1B
I/O
T1A
I/O
SO
I/O
SK
2
4
4
I
SI
3
5
5
I/CKO
HALT Restart
4
6
6
D0
D1
D2
D3
O
O
O
O
19
20
21
22
25
26
27
28
29
30
31
32
I0
I1
I2
I3
I
I
I
I
7
8
9
9
b
a
COMP1IN
COMP1IN
10
11
12
10
11
12
9
COMP1OUT
10
b
a
I4
I5
I6
I7
I
I
I
I
COMP2IN
COMP2IN
13
14
15
16
13
14
15
16
COMP2OUT
D4
D5
D6
D7
O
O
O
O
29
30
31
32
33
34
35
36
C0
C1
C2
C3
C4
C5
C6
C7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
39
40
1
43
44
1
2
2
21
22
23
24
V
6
23
5
8
33
7
8
37
7
CC
GND
CKI
RESET
24
34
38
3
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Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Total Current out of GND Pin (Sink)
Storage Temperature Range
110 mA
b
a
65 C to 140 C
§
§
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
Supply Voltage (V
)
CC
7V
b
a
0.3V
Voltage at Any Pin
Total Current into V Pin (Source)
0.3V to V
CC
100 mA
CC
s
s
a
b
DC Electrical Characteristics 40 C
T
A
85 C unless otherwise specified
§
§
Parameter
Operating Voltage
Conditions
Min
Typ
Max
Units
2.5
6
V
V
Power Supply Ripple (Note 1)
Supply Current (Note 2)
Peak-to-Peak
0.1 V
CC
e
e
e
e
e
e
e
e
e
e
CKI
CKI
CKI
CKI
10 MHz
4 MHz
4 MHz
1 MHz
V
CC
V
CC
V
CC
V
CC
6V, t
6V, t
1 ms
8.0
4.5
2.5
1.4
mA
mA
mA
mA
c
2.5 ms
c
e
4.0V, t
4.0V, t
2.5 ms
10 ms
c
c
e
k
e
e
e
HALT Current (Note 3)
V
V
6V, CKI
0 MHz
1
10
6
mA
mA
CC
k
0.5
e
4.0V, CKI
0 MHz
CC
IDLE Current
e
e
e
e
e
e
e
e
CKI
CKI
CKI
10 MHz
4 MHz
1 MHz
V
CC
V
CC
V
CC
6V, t
6V, t
1 ms
3.5
2.5
0.7
mA
mA
mA
c
2.5 ms
c
e
4.0V, t
10 ms
c
Input Levels
RESET
Logic High
0.8 V
0.7 V
0.7 V
V
V
CC
CC
CC
Logic Low
0.2 V
0.2 V
0.2 V
CC
CC
CC
CKI (External and Crystal Osc. Modes)
Logic High
V
V
Logic Low
All Other Inputs
Logic High
V
V
Logic Low
e
e
b
a
2
Hi-Z Input Leakage
V
V
6V
2
mA
mA
V
CC
e
b
b
250
0.35 V
Input Pullup Current
6V, V
0V
40
CC
IN
G and L Port Input Hysteresis
CC
Output Current Levels
D Outputs
e
e
e
e
e
OH
b
b
Source
V
CC
V
CC
V
CC
V
CC
4V, V
3.3V
0.4
0.2
mA
mA
mA
mA
e
2.5V, V
OH
1.8V
1V
e
Sink
4V, V
OL
10
2.0
e
2.5V, V
OL
0.4V
All Others
e
e
e
e
e
e
e
b
b
100
b
33
Source (Weak Pull-Up Mode)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
4V, V
OH
2.7V
10
2.5
0.4
0.2
mA
mA
mA
mA
mA
mA
e
b
b
b
2.5V, V
OH
1.8V
e
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
4V, V
OH
3.3V
e
2.5V, V
OH
1.8V
e
4V, V
OL
0.4V
1.6
0.7
e
2.5V, V
0.4V
OL
e
b
a
2
TRI-STATE Leakage
V
CC
6.0V
2
mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a crystal/resonator oscillator, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L, C, and G0–G5 configured
CC
as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.
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4
s
s
a
b
DC Electrical Characteristics 40 C
T
A
85 C unless otherwise specified (Continued)
§
§
Parameter
Conditions
Min
Typ
Max
Units
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others
15
3
mA
mA
e
25 C
Maximum Input Current
without Latchup
T
A
§
g
100
mA
V
RAM Retention Voltage, V
500 ns Rise
and Fall Time (Min)
r
2
Input Capacitance
7
pF
pF
Load Capacitance on D2
1000
s
s
a
b
AC Electrical Characteristics 40 C
T
A
85 C unless otherwise specified
§
§
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t )
c
s
s
6V
Crystal, Resonator,
R/C Oscillator
4V
V
1
DC
DC
DC
DC
ms
ms
ms
ms
CC
s
k
2.5V
V
4V
2.5
3
CC
s
s
4V
V
CC
6V
s
k
4V
2.5V
V
7.5
CC
Inputs
s
s
6V
t
4V
V
200
500
60
ns
ns
ns
ns
SETUP
CC
s
k
2.5V
V
4V
CC
s
s
t
4V
V
CC
6V
HOLD
s
k
4V
2.5V
V
150
CC
e
e
100 pF
Output Propagation Delay (Note 4)
, t
R
L
2.2k, C
L
t
PD1 PD0
s
s
6V
SO, SK
4V
V
0.7
1.75
1
ms
ms
ms
ms
CC
s
k
2.5V
V
4V
CC
s
s
All Others
4V
V
CC
6V
s
k
4V
2.5V
V
2.5
CC
MICROWIRETM Setup Time (t
)
20
56
ns
ns
ns
UWS
MICROWIRE Hold Time (t
)
UWH
MICROWIRE Output Propagation Delay (t
)
220
UPD
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
1
1
1
1
t
c
t
c
t
c
t
c
Reset Pulse Width
1
ms
Note 4: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
5
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e
e
25 C
Comparators AC and DC Characteristics V
5V, T
§
CC
A
Parameter
Input Offset Voltage
Conditions
Min
Typ
Max
Units
mV
V
s
s
b
V
CC
g
g
25
0.4V
V
IN
1.5V
10
b
1.5
Input Common Mode Voltage Range
Low Level Output Current
0.4
1.6
1.6
V
CC
e
e
V
V
0.4V
4.6V
mA
mA
OL
High Level Output Current
OH
DC Supply Current Per Comparator
(When Enabled)
250
mA
ms
Response Time
TBD mV Step, TBD mV
Overdrive, 100 pF Load
1
TL/DD/9765–7
FIGURE 2. MICROWIRE/PLUS Timing
Pin Descriptions
and GND are the power supply pins.
V
CC
TL/DD/9765–8
CKI is the clock input. This can come from an R/C generat-
ed oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.
FIGURE 3. I/O Port Configurations
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
RESET is the master reset input. See Reset Description
section.
The Port L supports Multi-Input Wake Up on all eight pins.
L1 is used for the UART external clock. L2 and L3 are used
for the UART transmit and receive. L4 and L5 are used for
the timer input functions T2A and T2B. L6 and L7 are used
for the timer input functions T3A and T3B.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently con-
figured as an input (Schmitt trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memo-
ry map for the various addresses associated with the I/O
ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
The Port L has the following alternate features:
L0
L1
L2
L3
L4
L5
L6
L7
MIWU
MIWU or CKX
MIWU or TDX
MIWU or RDX
MIWU or T2A
MIWU or T2B
MIWU or T3A
MIWU or T3B
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
G0 and G2–G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscil-
lator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low
to high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-
vidually configured under software control.
CONFIGURATION
Register
DATA
Port Set-Up
Hi-Z Input
Register
0
0
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
0
1
1
1
0
1
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6
Pin Descriptions (Continued)
Functional Description
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose
input (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below. Reading the G6 and
G7 data bits will return zeros.
The architecture of the device is modified Harvard architec-
ture. With the Harvard architecture, the control store pro-
gram memory (ROM) is separated from the data store mem-
ory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The archi-
tecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
Note that the chip will be placed in the HALT mode by writ-
ing a ‘‘1’’ to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (t ) cycle time.
c
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alter-
nate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
Config Reg.
CLKDLY
Data Reg.
HALT
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
G7
G6
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
Alternate SK
IDLE
Port G has the following alternate features:
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 06F with reset.
S is the 8-bit Data Segment Address Register used to ex-
tend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.
G4 SO (MICROWIRETM Serial Data Output)
G5 SK (MICROWIRE Serial Clock)
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions:
PROGRAM MEMORY
G1 WDOUT WATCHDOG and/or Clock Monitor dedicat-
ed output
The program memory consists of 4096 bytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the
JID instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices vector to program
memory location 0FF Hex.
G7 CKO Oscillator dedicated output or general purpose
input
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredicatable values.
DATA MEMORY
PORT I is an eight-bit Hi-Z input port. The 28-pin device
does not have a full complement of Port I pins. The unavail-
able pins are not terminated i.e., they are floating. A read
operation for these unterminated pins will return unpredict-
able values. The user must ensure that the software takes
this into account by either masking or restricting the access-
es to bit operations. The unterminated Port I pins will draw
power only when addressed.
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters asso-
ciated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indi-
rectly by the B, X, SP pointers and S register.
The device has 192 bytes of RAM. Sixteen bytes of RAM
are mapped as ‘‘registers’’ at addresses 0F0 to 0FF Hex.
These registers can be loaded immediately, and also decre-
mented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
B and S are memory mapped into this space at address
locations 0FC to 0FF Hex respectively, with the other regis-
ters being available for general usage.
Port I1–I3 are used for Comparator 1. Port I4–I6 are used
for Comparator 2.
The Port I has the following alternate features.
b
COMP1 IN (Comparator 1 Negative Input)
I1
I2
I3
I4
I5
I6
a
COMP1 IN (Comparator 1 Positive Input)
COMP1OUT (Comparator 1 Output)
b
COMP2 IN (Comparator 2 Negative Input)
The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumu-
lator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
a
COMP2 IN (Comparator 2 Positive Input)
COMP2OUT (Comparator 2 Output)
Port D is an 8-bit output port that is preset high when
RESET goes low. The user can tie two or more D port out-
puts together in order to get a higher drive.
7
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Data Memory Segment RAM Extension
Data memory address 0FF is used as a memory mapped
location for the Data Segment Address Register (S).
(beyond the initial 128 bytes) are memory mapped at ad-
dress locations 0100 to 013F hex.
The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly rela-
tive to the reference of the B, X, or SP pointers (each con-
tains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previ-
ously. With the exception of the RAM register memory from
address locations 00F0 to 00FF, all RAM memory is memo-
ry mapped with the upper bit of the single-byte address be-
ing equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to 00FF) is extended. If this upper bit
equals one (representing address range 0080 to 00FF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
register S is used to extend the base address range (from
0000 to 007F) from XX00 to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data segment 2, etc., up
to FF00 to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment 0.
TL/DD/9765–9
*Reads as all ones.
FIGURE 4. RAM Organization
Figure 4 illustrates how the S register data memory exten-
sion is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data seg-
ments of 128 bytes each with an additional upper base seg-
ment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data seg-
ment (128 bytes) to another. However, the upper base seg-
ment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data seg-
ment extension.
Reset
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is set high. The PC, PSW, ICNTRL,
CNTRL, T2CNTRL and T3CNTRL control registers are
cleared. The UART registers PSR, ENU (except that TBMT
bit is set), ENUR and ENUI are cleared. The Comparator
Select Register is cleared. The S register is initialized to
zero. The Multi-Input Wakeup registers WKEN, WKEDG and
WKPND are cleared. The stack pointer, SP, is initialized to
6F Hex.
The instructions that utilize the stack pointer (SP) always
reference the stack as part of the base segment (Segment
0), regardless of the contents of the S register. The S regis-
ter is not changed by these instructions. Consequently, the
stack (used with subroutine linkage and interrupts) is always
located in the base segment. The stack pointer will be inti-
tialized to point at data memory location 006F as a result of
reset.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in-
hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t clock cycles. The Clock Monitor bit
C
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
116 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at ad-
dresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t –32 t clock cycles following
C
C
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in Figure 5 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 64 bytes of RAM
http://www.national.com
8
e
TABLE A. Crystal Oscillator Configuration, T
25 C
§
A
Reset (Continued)
R1
R2
C1
C2
CKI Freq
(MHz)
Conditions
(kX) (MX) (pF)
(pF)
e
5V
0
0
0
1
1
1
30
30
30–36
30–36
10
4
V
CC
e
V
5.0V
CC
e
200 100–150
0.455
V
5V
CC
e
TABLE B. RC Oscillator Configuration, T
25 C
§
A
TL/DD/9765–10
R
C
CKI Freq
(MHz)
Instr. Cycle
Conditions
l
c
Power Supply Rise Time
RC
5
(kX)
(pF)
(ms)
FIGURE 5. Recommended Reset Circuit
e
e
e
3.3
5.6
6.8
82
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
3.7 to 4.6
7.4 to 9.0
8.8 to 10.8
V
CC
V
CC
V
CC
5V
5V
5V
100
100
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction
s
s
200k
Note: 3k
R
s
s
200 pF
50 pF
C
cycle clock (1/t ).
c
Control Registers
CNTRL Register (Address X 00EE)
Figure 6 shows the Crystal and R/C diagrams.
Ê
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
e
8)
e
e
by (00
2, 01
4, 1x
Table A shows the component values required for various
standard crystal values.
IEDG
MSEL
T1C0
External interrupt edge polarity select
e
Falling edge)
e
(0
Rising edge, 1
R/C OSCILLATOR
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is avail-
able as a general purpose input, and/or HALT restart input.
Timer T1 Start/Stop control in timer
modes 1 and 2
Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
T1C1
T1C2
T1C3
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1
Bit 7
SL0
Bit 0
TL/DD/9765–12
TL/DD/9765–11
FIGURE 6. Crystal and R/C Oscillator Diagrams
9
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Control Registers (Continued)
PSW Register (Address X 00EF)
T2C1
T2C2
T2C3
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 mode control bit
Ê
The PSW register contains the following select bits:
GIE
Global interrupt enable (enables interrupts)
Enable external interrupt
EXEN
BUSY
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
MICROWIRE/PLUS busy shifting flag
EXPND External interrupt pending
Bit 7
Bit 0
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
T3CNTRL Register (Address X 00B6)
Ê
The T3CNTRL register contains the following bits:
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A cap-
ture edge in mode 3)
T3ENB Timer T3 Interrupt Enable for T3B
T3PNDB Timer T3 Interrupt Pending Flag for T3B pin
(T3B capture edge)
C
Carry Flag
T3ENA Timer T3 Interrupt Enable for Timer Underflow
or T3A pin
HC
Half Carry Flag
T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA
in mode 1, T3 Underflow in mode 2, T3a cap-
ture edge in mode 3)
HC
Bit 7
C
T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 0
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the car-
ry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.
T3C0
Timer T3 Start/Stop control in timer modes 1
and 2
Timer T3 Underflow Interrupt Pending Flag in
timer mode 3
T3C1
T3C2
T3C3
Timer T3 mode control bit
Timer T3 mode control bit
Timer T3 mode control bit
ICNTRL Register (Address X 00E8)
Ê
The ICNTRL register contains the following bits:
T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
Bit 7
Bit 0
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
Timers
mWEN Enable MICROWIRE/PLUS interrupt
mWPND MICROWIRE/PLUS interrupt pending
The device contains a very versatile set of timers (T0, T1,
T2, T3). All timers and associated autoreload/capture regis-
ters power up containing random data.
T0EN
T0PND Timer T0 Interrupt pending
LPEN L Port Interrupt Enable (Multi-Input Wakeup/In-
Timer T0 Interrupt Enable (Bit 12 toggle)
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed
terrupt)
Bit 7 could be used as a flag
Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB
rate of the instruction cycle clock, t . The user cannot read
c
or write to the IDLE Timer T0, which is a count down timer.
Bit 7
Bit 0
The Timer T0 supports the following functions:
T2CNTRL Register (Address X 00C6)
Ê
The T2CNTRL register contains the following bits:
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
T2ENB Timer T2 Interrupt Enable for T2B Input capture
edge
The IDLE Timer T0 can generate an interrupt when the thir-
teenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4 ms at the maximum
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
e
clock frequency (t
1 ms). A control flag T0EN allows the
c
T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
interrupt from the thirteenth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while reset-
ting it will disable the interrupt.
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A cap-
ture edge in mode 3)
T2C0
Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
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10
Timers (Continued)
TIMER T1, TIMER T2 AND TIMER T3
The device has
a set of three powerful timer/counter
blocks, T1, T2 and T3. The associated features and func-
tioning of a timer block are described by referring to the
timer block Tx. Since the three timer blocks, T1, T2 and T3
are identical, all comments are equally applicable to any of
the three timer blocks.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Inde-
pendent PWM mode, External Event Counter mode, and
Input Capture mode.
TL/DD/9765–14
FIGURE 7. Timer in PWM Mode
Mode 2. External Event Counter Mode
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to gen-
erate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely indepen-
dent of the microcontroller. The user software services the
timer block only when the PWM parameters require updat-
ing.
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
In this mode the timer Tx counts down at a fixed rate of t .
c
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
Figure 8 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Figure 7 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA out-
put pin. The underflows can also be programmed to gener-
ate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control en-
able flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer un-
derflow causes the RxA register to be reloaded into the tim-
er. Setting the timer enable flag TxENB will cause an inter-
rupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
TL/DD/9765–15
FIGURE 8. Timer in External Event Counter Mode
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
Either or both of the timer underflow interrupts may be en-
abled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
In this mode, the timer Tx is constantly running at the fixed
rate. The two registers, RxA and RxB, act as capture
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.
t
c
11
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Timers (Continued)
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be speci-
fied either as a positive or a negative edge. The trigger con-
dition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
TL/DD/9765–16
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
FIGURE 9. Timer in Input Capture Mode
TIMER CONTROL FLAGS
The timers T1, T2 and T3 have indentical control structures.
The control bits and their functions are summarized below.
TxC0
Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
e
e
Stop
Event Counter), where 1
Start, 0
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
Figure 9 shows a block diagram of the timer in Input Capture
mode.
TxENA Timer Interrupt Enable Flag
TxENB Timer Interrupt Enable Flag
e
e
1
0
Timer Interrupt Enabled
Timer Interrupt Disabled
TxC3
TxC2
TxC1
Timer mode control
Timer mode control
Timer mode control
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12
Timers (Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Interrupt A
Source
Interrupt B
Source
Timer
TxC3
TxC2
TxC1
Timer Mode
Counts On
0
0
0
MODE 2 (External
Event Counter)
Timer
Pos. TxB
Edge
TxA
Underflow
Pos. Edge
0
1
1
0
0
0
0
1
1
1
0
0
MODE 2 (External
Event Counter)
Timer
Pos. TxB
Edge
TxA
Underflow
Neg. Edge
MODE 1 (PWM)
TxA Toggle
Autoreload
RA
Autoreload
RB
t
c
MODE 1 (PWM)
No TxA Toggle
Autoreload
RA
Autoreload
RB
t
t
c
MODE 3 (Capture)
Captures:
Pos. TxA
Edge or
Timer
Pos. TxB
Edge
c
TxA Pos. Edge
TxB Pos. Edge
Underflow
1
0
1
1
1
1
0
1
1
MODE 3 (Capture)
Captures:
Pos. TxA
Edge or
Timer
Neg. TxB
Edge
t
c
t
c
t
c
TxA Pos. Edge
TxB Neg. Edge
Underflow
MODE 3 (Capture)
Captures:
Neg. TxB
Edge or
Timer
Pos. TxB
Edge
TxA Neg. Edge
TxB Pos. Edge
Underflow
MODE 3 (Capture)
Captures:
Neg. TxA
Edge or
Timer
Neg. TxB
Edge
TxA Neg. Edge
TxB Neg. Edge
Underflow
Power Save Modes
The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry the WATCHDOG logic, the Clock Monitor and
timer T0 are active but all other microcontroller activities are
stopped. In either mode, all on-board RAM, registers, I/O
states, and timers (with the exception of T0) are unaltered.
figuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
HALT MODE
The device can be placed in the HALT mode by writing a
‘‘1’’ to the HALT flag (G7 data bit). All microcontroller activi-
ties, including the clock and timers, are stopped. The
WATCHDOG logic is disabled during the HALT mode. How-
ever, the clock monitor circuitry if enabled remains active
and will cause the WATCHDOG output pin (WDOUT) to go
low. If the HALT mode is used and the user does not want
to activate the WDOUT pin, the Clock Monitor should be
disabled after the device comes out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register). In the HALT mode, the power requirements of the
256 and is clocked with the t instruction cycle clock. The t
c
c
clock is derived by dividing the oscillator clock down by a
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.
device are minimal and the applied voltage (V ) may be
CC
e
decreased to V (V
r
2.0V) without altering the state of the
r
machine.
If an RC clock option is being used, the fixed delay is intro-
duced optionally. A control bit, CLKDLY, mapped as config-
uration bit G7, controls whether the delay is to be intro-
duced or not. The delay is included if CLKDLY is set, and
excluded if CLKDLY is reset. The CLKDLY bit is cleared on
reset.
The device supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port. The sec-
ond method is with a low to high transition on the CKO (G7)
pin. This method precludes the use of the crystal clock con-
13
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Power Save Modes (Continued)
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode fea-
ture, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the device
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the device cannot be placed
in the HALT mode (writing a ‘‘1’’ to the HALT flag will have
no effect).
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service rou-
tine and then return to the instruction following the ‘‘Enter
Idle Mode’’ instruction.
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device
will resume normal operation with the instruction immediate-
ly following the ‘‘Enter IDLE Mode’’ instruction.
IDLE MODE
The device is placed in the IDLE mode by writing a ‘‘1’’ to
the IDLE flag (G6 data bit). In this mode, all activities, except
the associated on-board oscillator circuitry, the WATCH-
DOG logic, the clock monitor and the IDLE Timer T0, are
stopped.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
As with the HALT mode, the device can be returned to nor-
mal operation with a reset, or with a Multi-Input Wakeup
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
Multi-Input Wakeup
The Multi-Input Wakeup feature is ued to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
e
1 MHz, t
1 ms) of the IDLE Timer toggles.
c
Figure 10 shows the Multi-Input Wakeup logic.
TL/DD/9765–17
FIGURE 10. Multi-Input Wake Up Logic
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14
Multi-Input Wakeup (Continued)
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the Reg: WKEN. The Reg:
WKEN is an 8-bit read/write register, which contains a con-
trol bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.
PORT L INTERRUPTS
Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into
the same service subroutine.
The interrupt from Port L shares logic with the wake up cir-
cuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8-
bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable inter-
rupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal oper-
ation.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The pro-
gram would be as follows:
RBIT 5, WKEN
SBIT 5, WKEDG
RBIT 5, WKPND
SBIT 5, WKEN
The Wakeup signal will not start the chip running immediate-
ly since crystal oscillators or ceramic resonators have a fi-
nite start up time. The IDLE Timer (T0) generates a fixed
delay to ensure that the oscillator has indeed stabilized be-
fore allowing the device to execute instructions. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry and the IDLE Timer T0 are enabled. The IDLE Tim-
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safe-
ty procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the as-
sociated WKEN bits are enabled, the associated edge se-
lect bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
er is loaded with a value of 256 and is clocked from the t
c
instruction cycle clock. The t clock is derived by dividing
c
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE tim-
er is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock sig-
nals to be routed to the rest of the chip.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for Multi-In-
put Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempt-
ing to enter the HALT mode.
If the RC clock option is used, the fixed delay is under soft-
ware control. A control flag, CLKDLY, in the G7 configura-
tion bit allows the clock start up delay to be optionally insert-
ed. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during reset, so the clock
start up delay is not present following reset with the RC
clock options.
15
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UART
The COP888CG contains a full-duplex software program-
mable UART. The UART (Figure 11) consists of a transmit
shift register, a receiver shift register and seven address-
able registers, as follows: a transmit buffer register (TBUF),
Other functions of the ENUR register include saving the
ninth bit received in the data frame, enabling or disabling the
UART’s attention mode of operation and providing addition-
al receiver/transmitter status information via RCVG and
XMTG bits. The determination of an internal or external
clock source is done by the ENUI register, as well as select-
ing the number of stop bits and enabling or disabling trans-
mit and receive interrupts. A control flag in this register can
also select the UART mode of operation: asynchronous or
synchronous.
a
receiver buffer register (RBUF), a UART control and
status register (ENU), a UART receive control and status
register (ENUR), a UART interrupt and clock source register
(ENUI), a prescaler select register (PSR) and baud (BAUD)
register. The ENU register contains flags for transmit and
receive functions; this register also determines the length of
the data frame (7, 8 or 9 bits), the value of the ninth bit in
transmission, and parity selection bits. The ENUR register
flags framming, data overrun and parity errors while the
UART is receiving.
TL/DD/9765–18
FIGURE 11. UART Block Diagram
http://www.national.com
16
UART (Continued)
UART CONTROL AND STATUS REGISTERS
e
e
e
e
PSEL1
PSEL1
1, PSEL0
1, PSEL0
0
1
Mark(1) (if Parity enabled)
Space(0) (if Parity enabled)
The operation of the UART is programmed through three
registers: ENU, ENUR and ENUI. The function of the individ-
ual bits in these registers is as follows:
PEN: This bit enables/disables Parity (7- and 8-bit modes
only).
e
e
PEN
PEN
0
1
Parity disabled.
Parity enabled.
ENU-UART Control and Status Register (Address at 0BA)
PEN
PSEL1 XBIT9/ CHL1 CHL0 ERR
PSEL0
RBFL TBMT
0R 1R
Bit 0
ENURÐUART RECEIVE CONTROL AND
STATUS REGISTER
0RW 0RW 0RW 0RW 0RW 0R
RCVG: This bit is set high whenever a framing error occurs
and goes low when RDX goes high.
Bit 7
ENUR-UART Receive Control and Status Register
(Address at 0BB)
XMTG: This bit is set to indicate that the UART is transmit-
ting. It gets reset at the end of the last frame (end of last
Stop bit).
DOE FE
PE
SPARE RBIT9 ATTN XMTG RCVG
ATTN: ATTENTION Mode is enabled while this bit is set.
This bit is cleared automatically on receiving a character
with data bit nine set.
0RD
0RD
0RD
0RW* 0R
0RW 0R
0R
Bit7
Bit0
RBIT9: Contains the ninth data bit received when the UART
is operating with nine data bits per frame.
ENUI-UART Interrupt and Clock Source Register
(Address at 0BC)
SPARE: Reserved for future use.
STP2 STP78 ETDX SSEL XRCLK XTCLK ERI
ETI
PE: Flags a Parity Error.
0RW 0RW 0RW 0RW 0RW 0RW 0RW 0RW
e
e
PE
PE
0
1
Indicates no Parity Error has been detected since
the last time the ENUR register was read.
Indicates the occurrence of a Parity Error.
Bit7
Bit0
*Bit is not used.
0
1
R
Bit is cleared on reset.
FE: Flags a Framing Error.
e
Bit is set to one on reset.
FE
0
Indicates no Framing Error has been detected
since the last time the ENUR register was read.
Indicates the occurrence of a Framing Error.
Bit is read-only; it cannot be written by software.
e
FE
1
RW Bit is read/write.
D
Bit is cleared on read; when read by software as a one, it is cleared
automatically. Writing to the bit does not affect its state.
DOE: Flags a Data Overrun Error.
e
DOE
0
Indicates no Data Overrun Error has been de-
tected since the last time the ENUR register
was read.
DESCRIPTION OF UART REGISTER BITS
ENUÐUART CONTROL AND STATUS REGISTER
e
DOE
1
Indicates the occurrence of a Data Overrun Er-
ror.
TBMT: This bit is set when the UART transfers a byte of
data from the TBUF register into the TSFT register for trans-
mission. It is automatically reset when software writes into
the TBUF register.
ENUIÐUART INTERRUPT AND
CLOCK SOURCE REGISTER
ETI: This bit enables/disables interrupt from the transmitter
section.
RBFL: This bit is set when the UART has received a com-
plete character and has copied it into the RBUF register. It
is automatically reset when software reads the character
from RBUF.
e
e
ETI
ETI
0
1
Interrupt from the transmitter is disabled.
Interrupt from the transmitter is enabled.
ERI: This bit enables/disables interrupt from the receiver
section.
ERR: This bit is a global UART error flag which gets set if
any or a combination of the errors (DOE, FE, PE) occur.
e
e
ERI
ERI
0
1
Interrupt from the receiver is disabled.
Interrupt from the receiver is enabled.
CHL1, CHL0: These bits select the character frame format.
Parity is not included and is generated/verified by hardware.
XTCLK: This bit selects the clock source for the transmitter-
section.
e
e
e
e
CHL1
CHL1
0, CHL0
0, CHL0
0
1
The frame contains eight data bits.
The frame contains seven data
bits.
e
XTCLK
0
1
The clock source is selected through the
PSR and BAUD registers.
Signal on CKX (L1) pin is used as the clock.
e
e
e
e
CHL1
CHL1
1, CHL0
1, CHL0
0
1
The frame contains nine data bits.
Loopback Mode selected. Trans-
mitter output internally looped
back to receiver input. Nine bit
framing format is used.
e
XTCLK
XRCLK: This bit selects the clock source for the receiver
section.
e
e
XRCLK
0
The clock source is selected through the
PSR and BAUD registers.
Signal on CKX (L1) pin is used as the clock.
XBIT9/PSEL0: Programs the ninth bit for transmission
when the UART is operating with nine data bits per frame.
For seven or eight data bits per frame, this bit in conjunction
with PSEL1 selects parity.
XRCLK
1
SSEL: UART mode select.
e
e
SSEL
SSEL
0
1
Asynchronous Mode.
Synchronous Mode.
PSEL1, PSEL0: Parity select bits.
e
e
e
e
PSEL1
PSEL1
0, PSEL0
0, PSEL0
0
1
Odd Parity (if Parity enabled)
Even Parity (if Parity enabled)
17
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when a framing error occurs and goes low once RDX goes
high. TBMT, XMTG, RBFL and RCVG are read only bits.
UART (Continued)
ETDX: TDX (UART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
To simulate line break generation, software should reset
ETDX bit and output logic zero to TDX pin through Port L
data and configuration registers.
SYNCHRONOUS MODE
In this mode data is transferred synchronously with the
clock. Data is transmitted on the rising edge and received
on the falling edge of the synchronous clock.
STP78: This bit is set to program the last Stop bit to be
7/8th of a bit in length.
This mode is selected by setting SSEL bit in the ENUI regis-
ter. The input frequency to the UART is the same as the
baud rate.
STP2: This bit programs the number of Stop bits to be trans-
mitted.
When an external clock input is selected at the CKX pin,
data transmit and receive are performed synchronously with
this clock through TDX/RDX pins.
e
e
STP2
STP2
0
1
One Stop bit transmitted.
Two Stop bits transmitted.
If data transmit and receive are selected with the CKX pin
as clock output, the device generates the synchronous
clock output at the CKX pin. The internal baud rate genera-
tor is used to produce the synchronous clock. Data transmit
and receive are performed synchronously with this clock.
Associated I/O Pins
Data is transmitted on the TDX pin and received on the RDX
pin. TDX is the alternate function assigned to Port L pin L2;
it is selected by setting ETDX (in the ENUI register) to one.
RDX is an inherent function of Port L pin L3, requiring no
setup.
FRAMING FORMATS
The UART supports several serial framing formats (Figure
12). The format is selected using control bits in the ENU,
ENUR and ENUI registers.
The baud rate clock for the UART can be generated on-
chip, or can be taken from an external source. Port L pin L1
(CKX) is the external clock I/O pin. The CKX pin can be
either an input or an output, as determined by Port L Config-
uration and Data registers (Bit 1). As an input, it accepts a
clock signal which may be selected to drive the transmitter
and/or receiver. As an output, it presents the internal Baud
Rate Generator output.
The first format (1, 1a, 1b, 1c) for data transmission (CHL0
e
0) consists of Start bit, seven Data bits (ex-
e
1, CHL1
cluding parity) and 7/8, one or two Stop bits. In applications
using parity, the parity bit is generated and verified by hard-
ware.
e
e
0) consists of one
The second format (CHL0
0, CHL1
Start bit, eight Data bits (excluding parity) and 7/8, one or
two Stop bits. Parity bit is generated and verified by hard-
ware.
UART Operation
The UART has two modes of operation: asynchronous
mode and synchronous mode.
e
e
1)
The third format for transmission (CHL0
0, CHL1
ASYNCHRONOUS MODE
consists of one Start bit, nine Data bits and 7/8, one or two
Stop bits. This format also supports the UART ‘‘ATTEN-
TION’’ feature. When operating in this format, all eight bits
of TBUF and RBUF are used for data. The ninth data bit is
transmitted and received using two bits in the ENU and
ENUR registers, called XBIT9 and RBIT9. RBIT9 is a read
only bit. Parity is not generated or verified in this mode.
This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero. The input frequency to the UART is 16
times the baud rate.
The TSFT and TBUF registers double-buffer data for trans-
mission. While TSFT is shifting out the current character on
the TDX pin, the TBUF register may be loaded by software
with the next byte to be transmitted. When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register. There is also the
XMTG bit which is set to indicate that the UART is transmit-
ting. This bit gets reset at the end of the last frame (end of
last Stop bit). TBUF is a read/write register.
For any of the above framing formats, the last Stop bit can
be programmed to be 7/8th of a bit in length. If two Stop
bits are selected and the 7/8th bit is set (selected), the
second Stop bit will be 7/8th of a bit in length.
The parity is enabled/disabled by PEN bit located in the
ENU register. Parity is selected for 7- and 8-bit modes only.
e
If parity is enabled (PEN
1), the parity selection is then
performed by PSEL0 and PSEL1 bits located in the ENU
register.
The RSFT and RBUF registers double-buffer data being re-
ceived. The UART receiver continually monitors the signal
on the RDX pin for a low level to detect the beginning of a
Start bit. Upon sensing this low level, it waits for half a bit
time and samples again. If the RDX pin is still low, the re-
ceiver considers this to be a valid Start bit, and the remain-
ing bits in the character frame are each sampled a single
time, at the mid-bit position. Serial data input on the RDX pin
is shifted into the RSFT register. Upon receiving the com-
plete character, the contents of the RSFT register are cop-
ied into the RBUF register and the Received Buffer Full Flag
(RBFL) is set. RBFL is automatically reset when software
reads the character from the RBUF register. RBUF is a read
only register. There is also the RCVG bit which is set high
Note that the XBIT9/PSEL0 bit located in the ENU register
serves two mutually exclusive functions. This bit programs
the ninth bit for transmission when the UART is operating
with nine data bits per frame. There is no parity selection in
this framing format. For other framing formats XBIT9 is not
needed and the bit is PSEL0 used in conjunction with
PSEL1 to select parity.
The frame formats for the receiver differ from the transmit-
ter in the number of Stop bits required. The receiver only
requires one Stop bit in a frame, regardless of the setting of
the Stop bit selection bits in the control register. Note that
an implicit assumption is made for full duplex UART opera-
tion that the framing formats are the same for the transmit-
ter and receiver.
http://www.national.com
18
UART Operation (Continued)
TL/DD/9765–19
FIGURE 12. Framing Formats
UART INTERRUPTS
source selected in the PSR and BAUD registers. Internally,
the basic baud clock is created from the oscillator frequency
through a two-stage divider chain consisting of a 1–16 (in-
crements of 0.5) prescaler and an 11-bit binary counter.
(Figure 13) The divide factors are specified through two
read/write registers shown in Figure 14. Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Reg-
ister (PSR). PSR is cleared upon reset.
The UART is capable of generating interrupts. Interrupts are
generated on Receive Buffer Full and Transmit Buffer Emp-
ty. Both interrupts have individual interrupt vectors. Two
bytes of program memory space are reserved for each inter-
rupt vector. The two vectors are located at addresses 0xEC
to 0xEF Hex in the program memory space. The interrupts
can be individually enabled or disabled using Enable Trans-
mit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in
the ENUI register.
As shown in Table I, a Prescaler Factor of 0 corresponds to
NO CLOCK. NO CLOCK condition is the UART power down
mode where the UART clock is turned off for power saving
purpose. The user must also turn the UART clock off when
a different baud rate is chosen.
The interrupt from the Transmitter is set pending, and re-
mains pending, as long as both the TBMT and ETI bits are
set. To remove this interrupt, software must either clear the
ETI bit or write to the TBUF register (thus clearing the TBMT
bit).
The correspondences between the 5-bit Prescaler Select
and Prescaler factors are shown in Table I. Therer are many
ways to calculate the two divisor factors, but one particularly
effective method would be to achieve a 1.8432 MHz fre-
quency coming out of the first stage. The 1.8432 MHz pre-
scaler output is then used to drive the software programma-
ble baud rate counter to create a x16 clock for the following
baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400,
3600, 4800, 7200, 9600, 19200 and 38400 (Table II). Other
baud rates may be created by using appropriate divisors.
The x16 clock is then divided by 16 to provide the rate for
the serial shift registers of the transmitter and receiver.
The interrupt from the receiver is set pending, and remains
pending, as long as both the RBFL and ERI bits are set. To
remove this interrupt, software must either clear the ERI bit
or read from the RBUF register (thus clearing the RBFL bit).
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of
the UART can be individually selected to come either from
an external source at the CKX pin (port L, pin L1) or from a
19
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Baud Clock Generation (Continued)
TL/DD/9765–20
FIGURE 13. UART BAUD Clock Generation
TL/DD/9765–21
FIGURE 14. UART BAUD Clock Divisor Registers
TABLE I. Prescaler Factors
TABLE II. Baud Rate Divisors
(1.8432 MHz Prescaler Output)
Prescaler
Select
Prescaler
Factor
Baud
Rate
Baud Rate
b
Divisor 1 (N-1)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
NO CLOCK
1
110 (110.03)
134.5 (134.58)
150
1046
855
767
383
191
95
1.5
2
300
2.5
3
600
1200
3.5
4
1800
63
2400
47
4.5
5
3600
31
4800
23
5.5
6
7200
15
9600
11
6.5
7
19200
38400
5
2
7.5
8
The entries in Table II assume a prescaler output
of 1.8432 MHz. In the asynchronous mode the
baud rate could be as high as 625k.
8.5
9
As an example, considering the Asynchronous Mode and a
CKI clock of 4.608 MHz, the prescaler factor selected is:
9.5
10
e
4.608/1.8432
2.5
10.5
11
The 2.5 entry is available in Table I. The 1.8432 MHz pre-
scaler output is then used with proper Baud Rate Divisor
(Table II) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table II is 5.
11.5
12
12.5
13
b
e
e
b
5 (N 1 is the value from Table II)
N
1
N
6 (N is the Baud Rate Divisor)
13.5
14
e
c
e
1.8432 MHz/(16 6) 19200
Baud Rate
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the UART is 16 times the baud
rate. The equation to calculate baud rates is given below.
14.5
15
15.5
16
The actual Baud Rate may be found from:
e
c
c
N P)
BR
Fc/(16
http://www.national.com
20
Note that the framing format for this mode is the nine bit
format; one Start bit, nine data bits, and 7/8, one or two
Stop bits. Parity is not generated or verified in this mode.
Baud Clock Generation (Continued)
Where:
BR is the Baud Rate
Fc is the CKI frequency
Attention Mode
N is the Baud Rate Divisor (Table II).
The UART Receiver section supports an alternate mode of
operation, referred to as ATTENTION Mode. This mode of
operation is selected by the ATTN bit in the ENUR register.
The data format for transmission must also be selected as
having nine Data bits and either 7/8, one or two Stop bits.
P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table I)
Note: In the Synchronous Mode, the divisor 16 is replaced by two.
Example:
The ATTENTION mode of operation is intended for use in
networking the device with other processors. Typically in
such environments the messages consists of device ad-
dresses, indicating which of several destinations should re-
ceive them, and the actual data. This Mode supports a
scheme in which addresses are flagged by having the ninth
bit of the data field set to a 1. If the ninth bit is reset to a
zero the byte is a Data byte.
Asynchronous Mode:
e
e
Crystal Frequency
Desired baud rate
5 MHz
9600
c
Using the above equation N
6
P can be calculated first.
c
e
c c
(5 10 )/(16 9600) 32.552
e
N
P
Now 32.552 is divided by each Prescaler Factor (Table II) to
obtain a value closest to an integer. This factor happens to
While in ATTENTION mode, the UART monitors the com-
munication flow, but ignores all characters until an address
character is received. Upon receiving an address character,
the UART signals that the character is ready by setting the
RBFL flag, which in turn interrupts the processor if UART
Receiver interrupts are enabled. The ATTN bit is also
cleared automatically at this point, so that data characters
as well as address characters are recognized. Software ex-
amines the contents of the RBUF and responds by deciding
either to accept the subsequent data stream (by leaving the
ATTN bit reset) or to wait until the next address character is
seen (by setting the ATTN bit again).
e
be 6.5 (P
6.5).
e
e
e
5.008 (N 5)
N
32.552/6.5
b
The programmed value (from Table II) should be 4 (N
1).
Using the above values calculated for N and P:
6
e
c
(5 10 )/(16
c
c
e
6.5) 9615.384
BR
5
e
b
e
(9615.385 9600)/9600 0.16
% error
Effect of HALT/IDLE
The UART logic is reinitialized when either the HALT or
IDLE modes are entered. This reinitialization sets the TBMT
flag and resets all read only bits in the UART control and
status registers. Read/Write bits remain unchanged. The
Transmit Buffer (TBUF) is not affected, but the Transmit
Shift register (TSFT) bits are set to one. The receiver regis-
ters RBUF and RSFT are not affected.
Operation of the UART Transmitter is not affected by selec-
tion of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
the ninth bit received is obtained by reading RBIT9. Since
this bit is located in ENUR register where the error flags
reside, a bit operation on it will reset the error flags.
The device will exit from the HALT/IDLE modes when the
Start bit of a character is detected at the RDX (L3) pin. This
feature is obtained by using the Multi-Input Wakeup scheme
provided on the device.
Comparators
The device contains two differential comparators, each with
a pair of inputs (positive and negative) and an output. Ports
I1–I3 and I4–I6 are used for the comparators. The following
is the Port I assignment:
Before entering the HALT or IDLE modes the user program
must select the Wakeup source to be on the RDX pin. This
selection is done by setting bit 3 of WKEN (Wakeup Enable)
register. The Wakeup trigger condition is then selected to
be high to low transition. This is done via the WKEDG regis-
ter (Bit 3 is one.)
I1 Comparator1 negative input
I2 Comparator1 positive input
I3 Comparator1 output
If the device is halted and crystal oscillator is used, the
Wakeup signal will not start the chip running immediately
because of the finite start up time requirement of the crystal
I4 Comparator2 negative input
I5 Comparator2 positive input
I6 Comparator2 output
oscillator. The idle timer (T0) generates a fixed (256 t ) de-
c
A Comparator Select Register (CMPSL) is used to enable
the comparators, read the outputs of the comparators inter-
nally, and enable the outputs of the comparators to the pins.
Two control bits (enable and output enable) and one result
bit are associated with each comparator. The comparator
result bits (CMP1RD and CMP2RD) are read only bits which
will read as zero if the associated comparator is not en-
abled. The Comparator Select Register is cleared with
reset, resulting in the comparators being disabled. The com-
parators should also be disabled before entering either the
HALT or IDLE modes in order to save power. The configura-
tion of the CMPSL register is as follows:
lay to ensure that the oscillator has indeed stabilized before
allowing the device to execute code. The user has to con-
sider this delay when data transfer is expected immediately
after exiting the HALT mode.
Diagnostic
Bits CHARL0 and CHARL1 in the ENU register provide a
loopback feature for diagnostic testing of the UART. When
these bits are set to one, the following occur: The receiver
input pin (RDX) is internally connected to the transmitter
output pin (TDX); the output of the Transmitter Shift Regis-
ter is ‘‘looped back’’ into the Receive Shift Register input. In
this mode, data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and
receive data paths of the UART.
21
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Comparators (Continued)
Interrupts
The device supports a vectored interrupt scheme. It sup-
ports a total of fourteen interrupt sources. The following ta-
ble lists all the possible device interrupt sources, their arbi-
tration ranking and the memory locations reserved for the
interrupt vector for each source.
CMPSL REGISTER (ADDRESS X’00B7)
The CMPSL register contains the following bits:
CMP1EN Enable comparator 1
CMP1RD Comparator 1 result (this is a read only bit,
which will read as 0 if the comparator is not
enabled)
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
CMP10E
Selects pin I3 as comparator 1 output provided
that CMPIEN is set to enable the comparator
CMP2EN
CMP2RD
Enable comparator 2
e
GIE
1 and an interrupt is active, then the processor will
Comparator 2 result (this is a read only bit,
which will read as 0 if the comparator is not
enabled)
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.
CMP20E
Selects pin I6 as comparator 2 output provided
that CMP2EN is set to enable the comparator
The interruption process is accomplished with the INTR in-
struction (opcode 00), which is jammed inside the Instruc-
tion Register and replaces the opcode about to be execut-
ed. The following steps are performed for every interrupt:
Unused CMP20E CMP2RD CMP2EN CMP10E CMP1RD CMP1EN Unused
Bit 7 Bit 0
Note that the two unused bits of CMPSL may be used as
software flags.
1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
Comparator outputs have the same spec as Ports L and G
except that the rise and fall times are symmetrical.
3. The PC (Program Counter) branches to address 00FF.
This procedure takes 7 t cycles to execute.
c
TL/DD/9765–22
FIGURE 15. Interrupt Block Diagram
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22
Interrupts (Continued)
Vector
Address
Arbitration
Source
Description
Ranking
Hi-Low Byte
(1) Highest
Software
INTR Instruction
for Future Use
Pin G0 Edge
Underflow
0yFE–0yFF
0yFC–0yFD
0yFA–0yFB
0yF8–0yF9
0yF6–0yF7
0yF4–0yF5
0yF2–0yF3
0yF0–0yF1
0yEE–0yEF
0yEC–0yED
0yEA–0yEB
0yE8–0yE9
0yE6–0yE7
0yE4–0yE5
0yE2–0yE3
0yE0–0yE1
Reserved
External
(2)
(3)
(4)
(5)
(6)
Timer T0
Timer T1
Timer T1
MICROWIRE/PLUS
Reserved
UART
T1A/Underflow
T1B
BUSY Goes Low
for Future Use
Receive
(7)
(8)
UART
Transmit
(9)
Timer T2
Timer T2
Timer T3
Timer T3
Port L/Wakeup
Default
T2A/Underflow
T2B
(10)
(11)
T3A/Underflow
T3B
(12)
(13)
Port L Edge
(14) Lowest
VIS Instr. Execution
without Any Interrupts
i
y is VIS page, y
0.
e
At this time, since GIE
0, other maskable interrupts are
a table starting at 01E0 (assuming that VIS is located be-
tween 00FF and 01DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then pro-
gram a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location 00FF Hex prior to the context
switching.
VIS and the vector table must be located in the same 256-
byte block (0y00 to 0yFF) except if VIS is located at the last
address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
i
256-byte block (y
0).
The vector of the maskable interrupt with the lowest rank is
located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at 0yFA
(Hi-Order byte) and 0yFB (Lo-Order byte).
Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt im-
mediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serv-
iced. This lower priority interrupt will occur immediately fol-
lowing the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.
The Software Trap has the highest rank and its vector is
located at 0yFE and 0yFF.
If, by accident, a VIS gets executed and no interrupt is ac-
tive, then the PC (Program Counter) will branch to a vector
located at 0yE0–0yE1.
WARNING; A Default VIS interrupt handler routine must be
present. As a minimum, this handler should confirm that the
GIE bit is cleared (this indicates that the interrupt sequence
has been taken), take care of any required housekeeping,
restore context and return. Some sort of Warm Restart pro-
cedure should be implemented. These events can occur
without any error on the part of the system designer or pro-
grammer.
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service rou-
tine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again if another interrupt is
active and pending.
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset
but an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid
this scenario, the user should always use a two, three, or four cycle
instruction to reset interrupt enable bits.
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
Figure 15 shows the Interrupt block diagram.
23
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TABLE IV. WATCHDOG Service Window Select
Interrupts (Continued)
WDSVR
Bit 7
WDSVR
Bit 6
Service Window
SOFTWARE TRAP
(Lower-Upper Limits)
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.
0
0
1
1
0
1
0
1
2k–8k t Cycles
c
2k–16k t Cycles
c
2k–32k t Cycles
c
2k–64k t Cycles
c
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset, but
not necessarily containing all of the same initialization pro-
cedures) before restarting.
Clock Monitor
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/t ) is greater or equal to 10 kHz. This equates to a
c
clock input rate on CKI of greater or equal to 100 kHz.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This pending bit is also
cleared on reset.
WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, in-
cluding the case where the oscillator fails to start.
The ST has the highest rank among all interrupts.
Nothing (except another ST) can interrupt an ST being
serviced.
WATCHDOG
The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
‘‘runaway’’ programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a speci-
fied rate on the CKI pin.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCH-
DOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table V shows the se-
quence of events that can occur.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific val-
ue to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table III shows the WDSVR register.
The user must service the WATCHDOG at least once be-
fore the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
The lower limit of the service window is fixed at 2048 in-
struction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.
Table IV shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexi-
bility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-
bit Key Data field. The key data is fixed at 01100. Bit 0 of the
WDSVR Register is the Clock Monitor Select bit.
will pull the WDOUT (G1) pin low for an additional 16 t –
c
32 t cycles after the signal level on WDOUT pin goes be-
c
TABLE III. WATCHDOG Service Register (WDSVR)
low the lower Schmitt trigger threshold. After this delay, the
device will stop forcing the WDOUT output low.
Window
Select
Clock
Key Data
Monitor
X
X
6
0
5
1
4
1
3
0
2
0
1
Y
0
7
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24
The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
#
WATCHDOG Operation (Continued)
The WATCHDOG service window will restart when the
WDOUT pin goes high. It is recommended that the user tie
through a resistor in order to
the WDOUT pin back to V
pull WDOUT high.
CC
The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
#
#
A WATCHDOG service while the WDOUT signal is active
will be ignored. The state of the WDOUT pin is not guaran-
teed on reset, but if it powers up low then the WATCHDOG
will time out and WDOUT will enter high impedance state.
The CLOCK MONITOR detector circuit is active during
both the HALT and IDLE modes. Consequently, the de-
vice inadvertently entering the HALT mode will be detect-
ed as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program).
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum speci-
fied value, after which the G1 output will enter the high im-
With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service win-
dow will resume following HALT mode from where it left
off before entering the HALT mode.
#
#
pedance TRI-STATE mode following 16 t –32 t clock cy-
c
c
cles. The Clock Monitor generates a continual Clock Moni-
tor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:
With the crystal oscillator mask option selected, or with
the single-pin R/C oscillator mask option selected and
the CLKDLY bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.
l
k
1/t
10 kHzÐNo clock rejection.
c
c
1/t
10 HzÐGuaranteed clock rejection.
Watchdog and Clock Monitor
Summary
The following salient points regarding the WATCHDOG and
The IDLE timer T0 is not initialized with RESET.
#
#
The user can sync in to the IDLE counter cycle with an
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the T0PND flag.
CLOCK MONITOR should be noted:
Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET.
#
Following RESET, the WATCHDOG and CLOCK MONI-
TOR are both enabled, with the WATCHDOG having he
maximum service window selected.
#
A hardware WATCHDOG service occurs just as the de-
vice exits the IDLE mode. Consequently, the WATCH-
DOG should not be serviced for at least 2048 instruction
cycles following IDLE, but must be serviced within the
selected window to avoid a WATCHDOG error.
#
#
The WATCHDOG service window and CLOCK MONI-
TOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
#
The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in or-
der to avoid a WATCHDOG error.
#
Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed any-
where within the maximum service window (65,536 in-
struction cycles) initialized by RESET. Note that this ini-
tial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a WATCH-
DOG error.
Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG er-
rors.
#
25
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Detection of Illegal Conditions
MICROWIRE/PLUS
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
MICROWIRE/PLUS is a serial synchronous communica-
tions interface. The MICROWIRE/PLUS capability enables
the device to interface with any of National Semiconductor’s
MICROWIRE peripherals (i.e. A/D converters, display driv-
Reading of undefined ROM gets zeros. The opcode for soft-
ware interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
2
ers, E PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 12
shows a block diagram of the MICROWIRE/PLUS logic.
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each re-
turn or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more re-
turns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F (Segment 0), 140 to 17F
(Segment 1), and all other segments (i.e., Segments 3 . . .
etc.) is read as all 1’s, which in turn will cause the program
to return to address 7FFF Hex. This is an undefined ROM
location and the instruction fetched (all 0’s) from this loca-
tion will generate a software interrupt signaling an illegal
condition.
Thus, the chip can detect the following illegal conditions:
a. Executing from undefined ROM
TL/DD/9765–23
b. Over ‘‘POP’’ing the stack by having more returns than
calls.
FIGURE 16. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift
clock is called the Slave mode of operation.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before re-
starting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures). The recovery program should re-
set the software interrupt pending bit using the RPND in-
struction.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table VI details the
different clock rates that may be selected.
TABLE V. WATCHDOG Service Actions
Key
Window
Data
Clock
Action
Data
Monitor
Match
Match
Match
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Don’t Care
Mismatch
Don’t Care
Mismatch
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Mismatch
TABLE VI. MICROWIRE/PLUS
Master Mode Clock Select
SL1
SL0
SK
Where t is the
c
instruction cycle clock
c
c
c
0
0
1
0
1
x
2
4
8
t
c
t
c
t
c
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26
MICROWIRE/PLUS (Continued)
MICROWIRE/PLUS OPERATION
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.
Setting the BUSY bit in the PSW register causes the MI-
CROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 13 shows
how two devices, microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS ar-
rangements.
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shift-
ed in on the falling edge of the SK clock and shifted out on
the rising edge of the SK clock.
Warning:
The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register. SK clock is
normally low when not shifting.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configura-
tion bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
MICROWIRE/PLUS Master Mode Operation
TABLE VII
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table VII summarizes the bit settings
required for Master mode of operation.
This table assumes that the control flag MSEL is set.
G4 (SO)
G5 (SK)
G4
G5
Operation
Config. Bit Config. Bit Fun. Fun.
1
0
1
0
1
1
0
0
SO
Int. MICROWIRE/PLUS
SK Master
TRI- Int. MICROWIRE/PLUS
STATE SK Master
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration reg-
ister. Table VII summarizes the settings required to enter
the Slave mode of operation.
SO
Ext. MICROWIRE/PLUS
SK Slave
TRI- Ext. MICROWIRE/PLUS
STATE SK Slave
TL/DD/9765–24
FIGURE 17. MICROWIRE/PLUS Application
27
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Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
Address
Address
Contents
Contents
Port L Data Register
S/ADD REG
S/ADD REG
0000 to 006F
0070 to 007F
On-Chip RAM bytes (112 bytes)
xxD0
xxD1
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Unused RAM Address Space (Reads
As All Ones)
xxD2
xxD3
xx80 to xxAF
Unused RAM Address Space (Reads
Undefined Data)
xxD4
Port G Data Register
xxD5
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
xxB0
XXB1
xxB2
Timer T3 Lower Byte
xxD6
Timer T3 Upper Byte
xxD7
Timer T3 Autoload Register T3RA
Lower Byte
xxD8
xxD9
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
xxB3
xxB4
xxB5
Timer T3 Autoload Register T3RA
Upper Byte
xxDA
xxDB
xxDC
xxDD to DF
Timer T3 Autoload Register T3RB
Lower Byte
Port D
Reserved for Port D
Timer T3 Autoload Register T3RB
Upper Byte
xxE0 to xxE5
xxE6
Reserved for EE Control Registers
Timer T1 Autoload Register T1RB
Lower Byte
xxB6
xxB7
xxB8
xxB9
xxBA
Timer T3 Control Register
Comparator Select Register (CMPSL)
UART Transmit Buffer (TBUF)
UART Receive Buffer (RBUF)
UART Control and Status Register
(ENU)
xxE7
Timer T1 Autoload Register T1RB
Upper Byte
xxE8
xxE9
xxEA
xxEB
xxEC
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
xxBB
xxBC
UART Receive Control and Status
Register (ENUR)
Timer T1 Upper Byte
UART Interrupt and Clock Source
Register (ENUI)
Timer T1 Autoload Register T1RA
Lower Byte
xxBD
xxBE
xxBF
UART Baud Register (BAUD)
UART Prescale Select Register (PSR)
Reserved for UART
xxED
Timer T1 Autoload Register T1RA
Upper Byte
xxEE
xxEF
CNTRL Control Register
PSW Register
xxC0
xxC1
xxC2
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA
Lower Byte
xxF0 to FB
xxFC
On-Chip RAM Mapped as Registers
X Register
xxFD
SP Register
xxC3
xxC4
xxC5
Timer T2 Autoload Register T2RA
Upper Byte
xxFE
B Register
xxFF
S Register
Timer T2 Autoload Register T2RB
Lower Byte
0100–013F
On-Chip 64 RAM Bytes
Timer T2 Autoload Register T2RB
Upper Byte
Reading memory locations 0070H–007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H–00AFH (Segment 0) will return
undefined data. Reading unused memory locations 0140–017F (Segment 1)
will return all ones. Reading memory locations from other Segments (i.e.,
Segment 2, Segment 3, ... etc.) will return all ones.
xxC6
xxC7
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
xxC8
MIWU Edge Select Register
(Reg:WKEDG)
xxC9
xxCA
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register
(Reg:WKPND)
xxCB
Reserved
xxCC
Reserved
xxCD to xxCF
Reserved
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28
Addressing Modes
There are ten addressing modes, six for operand address-
ing and four for transfer of control.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.
OPERAND ADDRESSING MODES
Register Indirect
This is the ‘‘normal’’ addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or
decrement of pointer)
Note: The VIS is a special case of the Indirect Transfer of Control address-
ing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X reg-
ister after executing the instruction.
Instruction Set
Register and Symbol Definition
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Registers
A
8-Bit Accumulator Register
8-Bit Address Register
Immediate
B
The instruction contains an 8-bit immediate field as the op-
erand.
X
8-Bit Address Register
SP
PC
PU
PL
C
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Lower 8 Bits of PC
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
1 Bit of PSW Register for Global
Interrupt Enable
Indirect
HC
GIE
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
VU
VL
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
TRANSFER OF CONTROL ADDRESSING MODES
Relative
Symbols
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
[
[
]
B
Memory Indirectly Addressed by B
Register
b
a
program location. JP has a range from 31 to 32 to allow
1 is implemented by a NOP
a
a 1-byte relative jump (JP
]
X
Memory Indirectly Addressed by X
Register
instruction). There are no ‘‘pages’’ when using JP, since all
15 bits of PC are used.
MD
Direct Addressed Memory
[
[
]
]
Mem
Meml
Direct Addressed Memory or
Direct Addressed Memory or
Immediate Data
B
Absolute
B
or
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.
Imm
Reg
8-Bit Immediate Data
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Absolute Long
Bit
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.
w
Ý
Loaded with
Exchanged with
29
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Instruction Set (Continued)
INSTRUCTION SET
a
a
ADD
ADC
A,Meml
A,Meml
ADD
ADD with Carry
w
Meml
Meml
AwA
w
A
C, C
C, C
w
w
Carry
Carry
a
A
HC
Half Carry
b
a
SUBC
A,Meml
Subtract with Carry
A
w
A
MemI
Half Carry
A and Meml
HC
A
w
AND
A,Meml
A,Imm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
Ý
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
w
e
0
ANDSZ
OR
XOR
Skip next if (A and Imm)
AwAA xoor rMMeemml l
w
A
Compare MD and Imm, Do next if MD
e
Imm
Meml
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
e
Compare A and Meml, Do next if A
i
Compare A and Meml, Do next if A Meml
l
Compare A and Meml, Do next if A Meml
i
Do next if lower 4 bits of B Imm
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IF BIT
Reset PeNDing Flag
b
e
0
0 to 7 immediate)
Reg
Reg
w
Reg 1, Skip if Reg
1 to bit, Mem (bit
0 to bit, Mem
e
Ý
Ý
Ý
,Mem
,Mem
,Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
X
X
A,Mem
EXchange A with Memory
EXchange A with Memory
LoaD A with Memory
A
Ý
Ý
Mem
[ ]
X
[
A, X
A,Meml
]
[
]
X
LD
LD
LD
LD
LD
A
AwMeml
[
A, X
B,Imm
]
[
]
[ ]
LoaD A with Memory
LoaD B with Immed.
X
w
B
AwImXm
Mem,Imm
Reg,Imm
LoaD Memory Immed
LoaD Register Memory Immed.
Mem
w
RegwImImmm
[
[
[
[
]
]
]
[
[
]
]
[
[
]
g
g
g
g
g
1)
g
1)
X
X
LD
LD
LD
A,
A,
A,
A,
B
X
B
X
EXchange A with Memory
EXchange A with Memory
B
X
A
A
A
A
[
Ý
Ý
B , (B
w
B
g
1)
]
X , (X
w
[
[
]
]
[
[
]
]
LoaD A with Memory
LoaD A with Memory
B
X
w
w
g
X
XB ,, ((XBwB
]
w
B
,Imm
LoaD Memory
B
Immed.
B
w
Imm, (Bw 1)
B
[
]
[
]
]
g
g
1)
CLR
INC
A
A
A
CLeaR A
INCrement A
DECrementA
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
w
Aw0
AwA
AwA
1
1
a
b
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
A
A
A
A
AwROM (PU,A)
AxBCD correction of A (follows ADC, SUBC)
C
CwA7w .. .. .. wAA00wC
x x x
C
A7 . . .AA74Ý
w
wA3 . . . A0
0
IF C is true, do next instruction
RC
IFC
Reset C
IF C
C
Cw01,, HHCCw1
IFNC
POP
PUSH
IF Not C
POP the stack into A
PUSH A onto the stack
a
[ ]
SP
A
A
ISfPCwis not true, do next instruction
w
SP
w
A, SP1w, A SP
b
1
[
]
SP
[
]
[
]
VL
VIS
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
w
e
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Addr.
Addr.
Disp.
Addr.
Addr
PPUCw VU , PL
w
ii (ii
PC9 . . . 0wi1(5i bits, 0 to 32k)
12 bits)
b
e
r (r is 31 to 32, except 1)
a
a
PU,SP 2, PC
PC
[
[
w
PC
wPL, SP
b
b
b
b
]
[
]
]
SP
SP
1
1
w
w
wii
PU,SP 2, PC9 . . . 0
]
[
w
PL, SP
w
i
PL
SP
SP
SP
[
w
ROM (PU,A)
[
a
b
]
1
]
]
]
]
[
[
[
2, PL
2, PL
2, PL
w
w
SP , PU
w
w
SP
a
a
]
b
]
1
[
[
b
SP ,PU
SP ,PU
SP
b
]
w
w
SP 1 ,GIE
w
1
0FF
b
PU, SP 2, PC
[
SP
w
PL, SP
1
1
w
w
a
PC
w
PC
http://www.national.com
30
Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction
opcode.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
Instructions Using A & C
Transfer of Control
Instructions
[
]
B
Direct
Immed.
CLRA
INCA
DECA
LAID
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
JMPL
JMP
JP
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
ADD
ADC
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
SUBC
AND
OR
JSRL
JSR
DCOR
RRCA
RLCA
SWAPA
SC
JID
XOR
IFEQ
IFNE
IFGT
IFBNE
DRSZ
VIS
RET
RETSK
RETI
INTR
NOP
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
1/3
SBIT
RBIT
IFBIT
1/1
1/1
1/1
3/4
3/4
3/4
RPND
1/1
Memory Transfer Instructions
Register
Indirect
Register Indirect
Auto Incr. & Decr.
Direct Immed.
a
b
a
b
]
, X
[
]
[
]
[
]
[
B
X
B
, B
X
X A,*
LD A,*
LD B, Imm
LD B, Imm
LD Mem, Imm
LD Reg, Imm
IFEQ MD, Imm
1/1
1/1
1/3
1/3
2/3
1/2
1/2
1/3
1/3
2/3
2/2
1/1
2/2
k
(IF B 16)
l
(IF B 15)
2/2
3/3
2/3
3/3
2/2
l
e
*
Memory location addressed by B or X or directly.
31
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Opcode Table
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
F
E
D
C
B
RRCA
*
A
9
8
b
JP 15
b
JP 31
Ý
Ý
Ý
Ý
Ý
Ý
Ý
Ý
Ý
Ý
Ý
[ ]
ADC A, B
LD 0F0,
LD 0F1,
LD 0F2,
LD 0F3,
LD 0F4,
LD 0F5,
LD 0F6,
LD 0F7,
LD 0F8,
LD 0F9,
i
i
i
i
i
i
i
i
i
i
DRSZ 0F0
DRSZ 0F1
DRSZ 0F2
DRSZ 0F3
DRSZ 0F4
DRSZ 0F5
DRSZ 0F6
DRSZ 0F7
DRSZ 0F8
DRSZ 0F9
RC
SC
ADC A,
i
0
1
2
3
4
5
6
7
8
9
b
JP 14
b
JP 30
Ý
[ ]
SUB A, B
SUBC A,
IFEQ A,
i
b
JP 13
b
JP 29
a
b
a
b
[
[
]
]
[
X A, B
]
]
Ý
[ ]
IFEQ A, B
X A,
X A,
VIS
X
X
i
b
JP 12
b
JP 28
[
X A, B
Ý
[ ]
IFGT A, B
IFGT A,
i
b
JP 11
b
JP 27
Ý
[ ]
ADD A, B
LAID
JID
ADD A,
AND A,
XOR A,
i
b
JP 10
b
JP 26
Ý
Ý
i
[ ]
AND A, B
RPND
i
b
b
JP 25
[
X A, X
]
[
X A, B
]
[ ]
XOR A, B
JP
JP
JP
JP
9
8
7
6
i
b
b
b
b
JP 24
Ý
[
OR A, B
]
*
*
OR A,
b
JP 23
Ý
NOP
RLCA
LD A,
IFNE
i
IFC
b
JP 22
IFNE
IFEQ
IFNC
[
A, B
]
Ý
Ý
A, i
Md,
i
b
b
b
b
b
b
b
JP 21
a
b
a
b
a
b
Ý
Ý
Ý
Ý
Ý
Ý
[
LD A, X
]
[
LD A, B
]
[
] Ý
, i
JP
JP
JP
JP
JP
JP
5
4
3
2
1
0
LD 0FA,
LD 0FB,
LD 0FC,
LD 0FD,
LD 0FE,
LD 0FF,
i
DRSZ 0FA
DRSZ 0FB
DRSZ 0FC
DRSZ 0FD
DRSZ 0FE
DRSZ 0FF
LD
LD
B
B
INCA
DECA
POPA
RETSK
RET
A
B
C
D
E
F
b
JP 20
[
LD A, X
]
[
LD A, B
]
[
] Ý
, i
i
i
i
i
i
b
JP 19
Ý
LD Md,
DIR
i
JMPL
JSRL
X A,Md
LD A,Md
b
JP 18
b
JP 17
[
LD A, X
]
[
LD A, B
]
[ ] Ý
LD B , i
b
JP 16
Ý
*
*
LD B,
i
RETI
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32
Opcode Table (Continued)
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
7
6
5
4
3
2
1
0
a
JP 17
Ý
LD B, 0F
IFBIT
]
ANDSZ
Ý
A, i
IFBNE 0
JSR
x000–x0FF
JMP
x000–x0FF
INTR
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
[
0, B
a
JP 18
a
Ý
LD B, 0E
IFBIT
]
*
IFBNE 1
IFBNE 2
IFBNE 3
IFBNE 4
IFBNE 5
IFBNE 6
IFBNE 7
IFBNE 8
IFBNE 9
IFBNE 0A
IFBNE 0B
IFBNE 0C
IFBNE 0D
IFBNE 0E
IFBNE 0F
JSR
x100–x1FF
JMP
x100–x1FF
JP
2
[
1, B
a
JP 19
a
Ý
LD B, 0D
IFBIT
]
*
*
JSR
x200–x2FF
JMP
x200–x2FF
JP
3
[
2, B
a
JP 20
a
Ý
LD B, 0C
IFBIT
]
JSR
x300–x3FF
JMP
x300–x3FF
JP
4
[
3, B
a
JP 21
a
Ý
LD B, 0B
IFBIT
]
CLRA
JSR
x400–x4FF
JMP
x400–x4FF
JP
5
[
4, B
a
JP 22
a
Ý
LD B, 0A
IFBIT
]
SWAPA
DCORA
PUSHA
RBIT
JSR
x500–x5FF
JMP
x500–x5FF
JP
6
[
5, B
a
JP 23
a
Ý
LD B, 09
IFBIT
]
JSR
x600–x6FF
JMP
x600–x6FF
JP
7
[
6, B
a
JP 24
a
Ý
LD B, 08
IFBIT
]
JSR
x700–x7FF
JMP
x700–x7FF
JP
8
[
7, B
a
JP 25
a
Ý
LD B, 07
SBIT
]
JSR
x800–x8FF
JMP
x800–x8FF
JP
9
[
0, B
[
0, B
]
a
JP 26
a
Ý
LD B, 06
SBIT
]
RBIT
]
JSR
x900–x9FF
JMP
x900–x9FF
JP
10
11
12
13
14
15
16
[
1, B
[
1, B
a
JP 27
a
Ý
LD B, 05
SBIT
]
RBIT
]
JSR
xA00–xAFF
JMP
xA00–xAFF
JP
[
2, B
[
2, B
a
JP 28
a
Ý
LD B, 04
SBIT
]
RBIT
]
JSR
xB00–xBFF
JMP
xB00–xBFF
JP
[
3, B
[
3, B
a
JP 29
a
Ý
LD B, 03
SBIT
]
RBIT
]
JSR
xC00–xCFF
JMP
xC00–xCFF
JP
[
4, B
[
4, B
a
JP 30
a
Ý
LD B, 02
SBIT
]
RBIT
]
JSR
xD00–xDFF
JMP
xD00–xDFF
JP
[
5, B
[
5, B
a
JP 31
a
Ý
LD B, 01
SBIT
]
RBIT
]
JSR
xE00–xEFF
JMP
xE00–xEFF
JP
[
6, B
[
6, B
a
JP 32
a
Ý
LD B, 00
SBIT
]
RBIT
[ ]
7, B
JSR
xF00–xFFF
JMP
xF00–xFFF
JP
[
7, B
Where,
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
Ý
Note: The opcode 60 Hex is also the opcode for IFBIT i,A
Mask Options
The mask programmable options are shown below. The op-
tions are programmed at the same time as the ROM pattern
submission.
OPTION 2: HALT
4 1
4 2
Enable HALT mode
Disable HALT mode
OPTION 1: CLOCK CONFIGURATION
OPTION 3: BONDING OPTIONS
4 1
Crystal Oscillator (CKI/10)
4 1
4 2
4 3
4 4
4 5
44-Pin PLCC
40-Pin DIP
N/A
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
28-Pin DIP
28-Pin SO
4 2
Single-pin RC controlled
oscillator (CKI/10)
G7 is available as a HALT
restart and/or general purpose
input
33
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Development Support
SUMMARY
A full 64k hardware configurable break, trace on, trace
off control, and pass count increment events.
#
#
iceMASTERTM: IM-COP8/400ÐFull feature in-circuit em-
#
Tool set integrated interactive symbolic debuggerÐsup-
ports both assembler (COFF) and C Compiler (.COD)
linked object formats.
ulation for all COP8 products. A full set of COP8 Basic
and Feature Family device and package specific probes
are available.
Real time performance profiling analysis; selectable
bucket defintion.
#
#
#
#
COP8 Debug Module: Moderate cost in-circuit emulation
and development programming unit.
#
Watch windows, content updated automatically at each
execution break.
COP8 Evaluation and Programming Unit: EPU-
COP888GGÐlow cost in-circuit simulation and develop-
ment programming unit.
#
Instruction by instruction memory/register changes dis-
played on source window when in single step operation.
Assembler: COP8-DEV-IBMA. A DOS installable cross
development Assembler, Linker, Librarian and Utility
Software Development Tool Kit.
#
Single base unit and debugger software reconfigurable to
support the entire COP8 family; only the probe personali-
ty needs to change. Debugger software is processor cus-
tomized, and reconfigured from a master model file.
C Compiler: COP8C. A DOS installable cross develop-
ment Software Tool Kit.
#
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
#
OTP/EPROM Programmer Support: Covering needs
from engineering prototype, pilot production to full pro-
duction environments.
#
Halt/Idle mode notification.
#
#
On-Line HELP customized to specific processor using
master model file.
IceMASTER (IM) IN-CIRCUIT EMULATION
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool development and marketed by
MetaLink Corporation to support the whole COP8 family of
products. National is a resale vendor for these products.
Includes a copy of COP8-DEV-IBMA assembler and link-
er SDK.
#
IM Order Information
See Figure 18 for configuration.
Base Unit
The iceMASTER IM-COP8/400 with its device specific
COP8 Probe provides a rich feature set for developing, test-
ing and maintaining product:
IM-COP8/400-1
iceMASTER Base Unit,
110V Power Supply
Real-time in-circuit emulation; full 2.4V–5.5V operation
range, full DC-10 MHz clock. Chip options are program-
mable or jumper selectable.
#
IM-COP8/400-2
iceMASTER Base Unit,
220V Power Supply
iceMASTER Probe
Direct connection to application board by package com-
patible socket or surface assembly.
#
MHW-884EG28DWPC
MHW-888EG40DWPC
MHW-888EG44PWPC
28 DIP
40 DIP
Full 32 kbyte of loadable programming space that over-
#
44 PLCC
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on
the probe as necessary.
Adapter for SO Package
MHW-SOIC28
28 SO
Full 4k frame synchronous trace memory. Address, in-
#
struction, and 8 unspecified, circuit connectable trace
lines. Display can be HLL source (e.g., C source), assem-
bly or mixed.
TL/DD/9765–26
FIGURE 18. COP8 iceMASTER Environment
http://www.national.com
34
Development Support (Continued)
Debugger software is processor customized, and recon-
figured from a master model file.
#
#
iceMASTER DEBUG MODULE (DM)
The iceMASTER Debug Module is a PC based, combination
in-circuit emulation tool and COP8 based OTP/EPROM pro-
gramming tool developed and marketed by MetaLink Corpo-
ration to support the whole COP8 family of products. Nation-
al is a resale vendor for these products.
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
Halt/Idle mode notification.
#
#
Programming menu supports full product line of program-
mable OTP and EPROM COP8 products. Program data
is taken directly from the overlay RAM.
See Figure 19 for configuration.
The iceMASTER Debug Module is a moderate cost devel-
opment tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product fami-
lies. Summary of features is as follows:
Programming of 44 PLCC and 68 PLCC parts requires
external programming adapters.
#
Includes wallmount power supply.
#
#
On-board V generator from 5V input or connection to
PP
Real-time in-circuit emulation; full operating voltage
range operation, full DC-10 MHz clock.
#
external supply supported. Requires V
PP
level adjust-
ment per the family programming specification (correct
level is provided on an on-screen pop-down display).
All processor I/O pins can be cabled to an application
development board with package compatible cable to
socket and surface mount assembly.
#
On-line HELP customized to specific processor using
master model file.
#
#
Full 32 kbyte of loadable programming space that over-
#
Includes a copy of COP8-DEV-IBMA assembler and link-
er SDK.
DM Order Information
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
Debug Module Unit
100 frames of synchronous trace memory. The display
#
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the
trace memory.
COP8-DM/888GG
Cable Adapters, Kits for COP888
Configured break points; uses INTR instruction which is
modestly intrusive.
#
DM-COP8/28D
28 DIP
DM-COP8/40D
40 DIP
Software-only supported features are selectable.
#
#
DM-COP8/44P
44 PLCC
Tool set integrated interactive symbolic debuggerÐsup-
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
Adapter for SO Package
MHW-SOIC28
28 SO
Instruction by instruction memory/register changes dis-
played when in single step operation.
#
TL/DD/9765–27
FIGURE 19. COP8-DM Environment
35
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Development Support (Continued)
Tool set integrated interactive symbolic debuggerÐsup-
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
#
iceMASTER EVALUATION PROGRAMMING UNIT (EPU)
The iceMASTER EPU-COP888GG is a PC based, in-circuit
simulation tool to support the feature family COP8 products.
Instruction by instruction memory/register changes dis-
played when in single step operation.
#
#
#
#
See Figure 20 for configuration.
The simulation capability is a very low cost means of evalu-
ating the general COP8 architecture. In addition, the EPU
has programming capability, with added adapters, for pro-
gramming the whole COP8 product family of OTP and EP-
ROM products. The product includes the following features:
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
Halt/Idle mode notification. Restart requires special han-
dling.
Programming menu supports full product line of program-
mable OTP and EPROM COP8 products. Only a 40 ZIF
socket is available on the EPU unit. Adapters are avail-
able for other part package configurations.
Non-real-time in-circuit simulation. Program overlay
#
memory is PC resident; instructions are downloaded over
RS-232 as executed. Approximate performance is
20 kHz.
Integral wall mount power supply provides 5V and devel-
ops the required V to program parts.
PP
#
#
Includes a 40-pin DIP cable adapter. Other target pack-
ages are not supported. All processor I/O pins are ca-
bled to the application development environment.
#
Includes a copy of COP8-DEV-IBMA assembler, linker
SDK.
EPU Order Information
Full 32 kbyte of loadable programming space that over-
#
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
Evaluation Programming Unit
EPU-COP888GG
Evaluation Programming Unit
with debugger and
On-chip timer and watch-dog execution are not well syn-
chronized to the instruction simulation.
#
programmer control software
with 40 ZIF programming
socket.
100 frames of synchronous trace memory. The display
#
can be HLL source (e.g., C source), assembly or mixed.
The most recent history prior to a break is available in the
trace memory.
General Programming Adapters
Up to eight software configured break points; uses INTR
instruction which is modestly intrusive.
#
COP8-PGMA-DS
28 and 20 DIP and SOIC
adapter.
Common look-feel debugger software across all Meta-
Link productsÐonly supported features are selectable.
#
COP8-PGMA-DS44P
28 and 20 DIP and SOIC plus
44 PLCC adapter.
TL/DD/9765–28
FIGURE 20. EPU-COP8 Tool Environment
http://www.national.com
36
Development Support (Continued)
COP8 ASSEMBLER/LINKER SOFTWARE DEVELOP-
MENT TOOL KIT
COP8 C COMPILER
A C Compiler is developed and marketed by Byte Craft Lim-
ited. The COP8C compiler is a fully integrated development
tool specifically designed to support the compact embed-
ded configuration of the COP8 family of products.
National Semiconductor offers a relocatable COP8 macro
cross assembler, linker, librarian and utility software devel-
opment tool kit. Features are summarized as follows:
Basic and Feature Family instruction set by ‘‘device’’
type.
Features are summarized as follows:
#
ANSI C with some restrictions and extensions that opti-
mize development for the COP8 embedded application.
#
Nested macro capability.
#
Ý
BITS data type extension. Register declaration pragma
with direct bit level definitions.
Extensive set of assembler directives.
#
#
#
#
#
#
#
Supported on PC/DOS platform.
C language support for interrupt routines.
#
#
Generates National standard COFF output files.
Expert system, rule based code generation and optimiza-
tion.
Integrated Linker and Librarian.
Integrated utilities to generate ROM code file outputs.
Performs consistency checks against the architectural
definitions of the target COP8 device.
#
DUMPCOFF utility.
This product is integrated as a part of MetaLink tools as a
development kit, fully supported by the MetaLink debugger.
It may be ordered separately or it is bundled with the Meta-
Link products at no additional cost.
Generates program memory code.
#
#
Supports linking of compiled object or COP8 assembled
object formats.
Order Information
Global optimization of linked code.
#
#
Symbolic debug load format fully source level supported
by the MetaLink debugger.
Assembler SDK
COP8-DEV-IBMA
Assembler SDK on installable
3.5 PC/DOS Floppy Disk Drive
format. Periodic upgrades and
most recent version is available
on National’s BBS and Internet.
SINGLE CHIP OTP/EMULATOR SUPPORT
×
The COP8 family is supported by single chip OTP emula-
tors. For detailed information refer to the emulator specific
datasheet and the emulator selection table below:
Approved List
Europe
North
Manufacturer
Asia
America
a
a
a
a
BP
Microsystems
(800) 225-2102
49-8152-4183
852-234-16611
852-2710-8121
(713) 688-4600
49-8856-932616
Fax: (713) 688-0920
a
Data I/O
HI–LO
(800) 426-1045
44-0734-440011
Call
(206) 881-6444
North America
Fax: (206) 882-1043
a
886-2-764-0215
(510) 623-8860
Call Asia
a
Fax: 886-2-756-6403
a
Fax: 0-1226-370-434
ICE
(800) 624-8949
(919) 430-7915
44-1226-767404
Technology
a
a
a
MetaLink
(800) 638-2423
49-80 9156 96-0
852-737-1800
a
Fax: 49-80 9123 86
(602) 926-0797
Fax: (602) 693-0681
a
Systems
General
(408) 263-6667
41-1-9450300
886-2-917-3005
a
Fax: 886-2-911-1283
Needhams
(916) 924-8037
Fax: (916) 924-8065
37
http://www.national.com
Development Support (Continued)
OTP Emulator Ordering Information
DIAL-A-HELPER via FTP
ftp nscmicro.nsc.com
Clock
Device Number
Package
Emulates
user:
anonymous
Option
@
password: username yourhost.site.domain
COP87L84EGN-XE Crystal
COP87L84EGM-XE Crystal
COP87L88EGN-XE Crystal
28 DIP
28 SO
40 DIP
COP884CG
COP884CG
COP888CG
DIAL-A-HELPER via a WorldWide Web Browser
ftp://nscmicro.nsc.com
National Semiconductor on the WorldWide Web
COP87L88EGV-XE
Crystal
44 PLCC COP888CG
See us on the WorldWide Web at: http://www.national.com
CUSTOMER RESPONSE CENTER
INDUSTRY WIDE OTP/EPROM PROGRAMMING
SUPPORT
Complete product information and technical support is avail-
able from National’s customer response centers.
Programming support, in addition to the MetaLink develop-
ment tools, is provided by a full range of independent ap-
proved vendors to meet the needs from the engineering
laboratory to full production.
CANADA/U.S.: Tel:
email:
(800) 272-9959
@
support tevm2.nsc.com
AVAILABLE LITERATURE
@
europe.support nsc.com
EUROPE:
email:
For more information, please see the COP8 Basic Family
User’s Manual, Literature Number 620895, COP8 Feature
Family User’s Manual, Literature Number 620897 and Na-
tional’s Family of 8-bit Microcontrollers COP8 Selection
Guide, Literature Number 630009.
a
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
Tel:
49 (0) 180-530 85 85
49 (0) 180-532 78 32
49 (0) 180-532 93 58
49 (0) 180-534 16 80
81-043-299-2309
DIAL-A-HELPER SERVICE
JAPAN:
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Infor-
mation System that may be accessed as a Bulletin Board
System (BBS) via data modem, as an FTP site on the Inter-
net via standard FTP client application or as an FTP site on
the Internet using a standard Internet browser such as Net-
scape or Mosaic.
a
S.E. ASIA:
Beijing Tel:
Shanghai Tel:
(
(
86) 10-6856-8601
a
86) 21
a
Hong Kong Tel: ( 852) 2737-1600
a
a
a
Korea Tel:
Malaysia Tel:
Singapore Tel:
Taiwan Tel:
Tel:
(
(
(
82) 2-3771-6909
60-4) 644-9061
65) 255-2226
The Dial-A-Helper system provides access to an automated
information storage and retrieval system. The system capa-
bilities include a MESSAGE SECTION (electronic mail,
when accessed as a BBS) for communication to and from
the Microcontroller Applications Group and a FILE SEC-
TION which consists of several file areas where valuable
application software and utilities could be found.
a
886-2-521-3288
a
AUSTRALIA:
INDIA:
(
61) 3-9558-9999
91) 80-559-9467
a
(
Tel:
DIAL-A-HELPER BBS via a Standard Modem
Modem: CANADA/U.S.: (800) NSC-MICRO
(800) 672-6427
a
49) 0-8141-351332
EUROPE:
Baud:
(
14.4k
Set-up:
Length: 8-Bit
Parity:
None
Stop Bit: 1
Operation:
24 Hours, 7 Days
http://www.national.com
38
39
http://www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number COP884CG-XXX/WM
NS Package Number M28B
http://www.national.com
40
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number COP884CG-XXX/N
NS Package Number N28B
Molded Dual-In-Line Package (N)
Order Number COP888CG-XXX/N
NS Package Number N40A
41
http://www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Leaded Chip Carrier (V)
Order Number COP888CG-XXX/V
NS Package Number V44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax: 49 (0) 180-530 85 86
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2308
Fax: 81-043-299-2408
@
Email: europe.support nsc.com
a
Deutsch Tel: 49 (0) 180-530 85 85
a
English Tel: 49 (0) 180-532 78 32
a
Fran3ais Tel: 49 (0) 180-532 93 58
a
Italiano Tel: 49 (0) 180-534 16 80
http://www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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