COP8SAA5SLB8XXX/NOPB [NSC]
IC 8-BIT, MROM, 10 MHz, MICROCONTROLLER, QCC28, CSP-28, Microcontroller;
| 型号： | COP8SAA5SLB8XXX/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC 8-BIT, MROM, 10 MHz, MICROCONTROLLER, QCC28, CSP-28, Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总75页 (文件大小：995K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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information and details on our current products and services.
PRELIMINARY
November 2000
COP8SA Family
8-Bit CMOS ROM Based and One-Time Programmable
(OTP) Microcontroller with 1k to 4k Memory, Power On
Reset, and Very Small Packaging
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1 µs instruction cycle, one multi-
function 16-bit timer/counter with PWM output,
General Description
Note: COP8SAx devices are instruction set and pin com-
patible supersets of the COP800 Family devices, and are
replacements for these in new designs when possible.
™
MICROWIRE/PLUS serial I/O, two power saving HALT/
IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12
high current outputs, user selectable options (WATCH-
The COPSAx Rom based and OTP microcontrollers are
™
™
highly integrated COP8 feature core devices, with 1k to 4k
DOG , 4 clock/oscillator modes, power-on-reset), low EMI
memory and advanced features including low EMI. These
single-chip CMOS devices are suited for low cost applica-
tions requiring a full featured controller, low EMI, and POR.
100% form-fit-function compatible OTP versions are avail-
able with 1k, 2k, and 4k memory, and in a variety of pack-
ages including 28-pin CSP. Erasable windowed versions are
available for use with a range of COP8 software and hard-
ware development tools.
2.7V to 5.5V operation, and 16/20/28/40/44 pin packages.
Devices included in this datasheet are:
Memory
(bytes)
RAM
(bytes)
64
I/O Pins
12/16/24
16/24
Device
Packages
Temperature
COP8SAA5
1k ROM
16/20/28 DIP/SOIC, 28 CSP 0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
COP8SAB5
COP8SAC5
COP8SAA7
COP8SAB7
COP8SAC7
2k ROM
128
128
64
20/28 DIP/SOIC, 28 CSP
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
4k ROM
16/24/36/40 20/28 DIP/SOIC, 28 CSP,
40 DIP, 44 PLCC/QFP
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
1k OTP EPROM
2k OTP EPROM
4k OTP EPROM
12/16/24
16/20/28 DIP/SOIC, 28 CSP 0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
128
128
16/24
20/28 DIP/SOIC, 28 CSP
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
16/24
20/28 DIP/SOIC, 28 CSP,
40 DIP, 44 PLCC/QFP
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
COP8SAC7-Q3
COP8SAC7-J3
4k EPROM
4k EPROM
128
128
16/24/36
40
20/28/40 DIP
44 PLCC
Room Temp. Only
Room Temp. Only
n User selectable clock options
— Crystal/Resonator options
— Crystal/Resonator option with on-chip bias resistor
— External oscillator
— Internal R/C oscillator
Key Features
n Low cost 8-bit OTP microcontroller
n OTP program space with read/write protection (fully
secured)
n Quiet Design (low radiated emissions)
n Multi-Input Wakeup pins with optional interrupts
(4 to 8 pins)
n Internal Power-On Reset—user selectable
n WATCHDOG and Clock Monitor Logic—user selectable
n Up to 12 high current outputs
n 8 bytes of user storage space in EPROM
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
™
™
MICROWIRE/PLUS , COP8 , MICROWIRE and WATCHDOG are trademarks of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation
DS012838
www.national.com
CPU Features
I/O Features
n Versatile easy to use instruction set
n 1 µs instruction cycle time
n Eight multi-source vectored interrupts servicing
— External interrupt
n Software selectable I/O options
— TRI-STATE® Output
— Push-Pull Output
— Weak Pull Up Input
— High Impedance Input
— Idle Timer T0
n Schmitt trigger inputs on ports G and L
n Up to 12 high current outputs
n Pin efficient (i.e., 40 pins in 44-pin package are devoted
to useful I/O)
— One Timer (with 2 interrupts)
— MICROWIRE/PLUS Serial Interface
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)
n 8-bit Stack Pointer SP (stack in RAM)
n Two 8-bit Register Indirect Data Memory Pointers
n True bit manipulation
n Memory mapped I/O
n BCD arithmetic instructions
Fully Static CMOS Design
<
n Low current drain (typically 4 µA)
n Single supply operation: 2.7V to 5.5V
n Two power saving modes: HALT and IDLE
Temperature Ranges
0˚C to +70˚C, −40˚C to +85˚C, and −40˚C to +125˚C
Peripheral Features
n Multi-Input Wakeup Logic
n One 16-bit timer with two 16-bit registers supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
Development Support
n Windowed packages for DIP and PLCC
n Real time emulation and full program debug offered by
MetaLink Development System
n Idle Timer
n MICROWIRE/PLUS Serial Interface (SPI Compatible)
Block Diagram
DS012838-1
FIGURE 1. COP8SAx Block Diagram
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2
Single Byte/Single Cycle Code Execution
General Description (Continued)
The efficiency is due to the fact that the majority of instruc-
tions are of the single byte variety, resulting in minimum
program space. Because compact code does not occupy a
substantial amount of program memory space, designers
can integrate additional features and functionality into the
microcontroller program memory space. Also, the majority
instructions executed by the device are single cycle, result-
ing in minimum program execution time. In fact, 77% of the
instructions are single byte single cycle, providing greater
code and I/O efficiency, and faster code execution.
Key features include an 8-bit memory mapped architecture,
a 16-bit timer/counter with two associated 16-bit registers
supporting three modes (Processor Independent PWM gen-
eration, External Event counter, and Input Capture capabili-
ties), two power saving HALT/IDLE modes with
a
multi-sourced wakeup/interrupt capability, on-chip R/C oscil-
lator, high current outputs, user selectable options such as
WATCHDOG, Oscillator configuration, and power-on-reset.
1.1 EMI REDUCTION
The COP8SAx family of devices incorporates circuitry that
guards against electromagnetic interference—an increasing
problem in today’s microcontroller board designs. National’s
patented EMI reduction technology offers low EMI clock
circuitry, gradual turn-on output drivers (GTOs) and internal
ICC smoothing filters, to help circumvent many of the EMI
issues influencing embedded control designs. National has
achieved 15 dB–20 dB reduction in EMI transmissions when
designs have incorporated its patented EMI reducing cir-
cuitry.
1.3.2 Many Single-Byte, Multifunction Instructions
The COP8SAx instruction set utilizes many single-byte, mul-
tifunction instructions. This enables a single instruction to
accomplish multiple functions, such as DRSZ, DCOR, JID,
and LOAD/EXCHANGE instructions with post-incrementing
and post-decrementing, to name just a few examples. In
many cases, the instruction set can simultaneously execute
as many as three functions with the same single-byte in-
struction.
JID: (Jump Indirect); Single byte instruction; decodes exter-
nal events and jumps to corresponding service routines
(analogous to “DO CASE” statements in higher level lan-
guages).
1.2 ARCHITECTURE
The COP8SAx family is based on a modified Harvard archi-
tecture, which allows data tables to be accessed directly
from program memory. This is very important with modern
microcontroller-based applications, since program memory
is usually ROM or EPROM, while data memory is usually
RAM. Consequently data tables usually need to be con-
tained in ROM or EPROM, so they are not lost when the
microcontroller is powered down. In a modified Harvard ar-
chitecture, instruction fetch and memory data transfers can
be overlapped with a two stage pipeline, which allows the
next instruction to be fetched from program memory while
the current instruction is being executed using data memory.
This is not possible with a Von Neumann single-address bus
architecture.
LAID: (Load Accumulator-Indirect); Single byte look up table
instruction provides efficient data path from the program
memory to the CPU. This instruction can be used for table
lookup and to read the entire program memory for checksum
calculations.
RETSK: (Return Skip); Single byte instruction allows return
from subroutine and skips next instruction. Decision to
branch can be made in the subroutine itself, saving code.
AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These
instructions use the two memory pointers B and X to effi-
ciently process a block of data (analogous to “FOR NEXT” in
higher level languages).
The COP8SAx family supports a software stack scheme that
allows the user to incorporate many subroutine calls. This
capability is important when using High Level Languages.
With a hardware stack, the user is limited to a small fixed
number of stack levels.
1.3.3 Bit-Level Control
Bit-level control over many of the microcontroller’s I/O ports
provides a flexible means to ease layout concerns and save
board space. All members of the COP8 family provide the
ability to set, reset and test any individual bit in the data
memory address space, including memory-mapped I/O ports
and associated registers. Three memory-mapped pointers
handle register indirect addressing and software stack
pointer functions. The memory data pointers allow the option
of post-incrementing or post-decrementing with the data
movement instructions (LOAD/EXCHANGE). And 15
memory-maped registers allow designers to optimize the
precise implementation of certain specific instructions.
1.3 INSTRUCTION SET
In today’s 8-bit microcontroller application arena cost/
performance, flexibility and time to market are several of the
key issues that system designers face in attempting to build
well-engineered products that compete in the marketplace.
Many of these issues can be addressed through the manner
in which a microcontroller’s instruction set handles process-
ing tasks. And that’s why COP8 family offers a unique and
code-efficient instruction set—one that provides the flexibil-
ity, functionality, reduced costs and faster time to market that
today’s microcontroller based products require.
1.4 PACKAGING/PIN EFFICIENCY
Real estate and board configuration considerations demand
maximum space and pin efficiency, particularly given today’s
high integration and small product form factors. Microcon-
troller users try to avoid using large packages to get the I/O
needed. Large packages take valuable board space and
increases device cost, two trade-offs that microcontroller
designs can ill afford.
Code efficiency is important because it enables designers to
pack more on-chip functionality into less program memory
space (ROM/OTP). Selecting a microcontroller with less pro-
gram memory size translates into lower system costs, and
the added security of knowing that more code can be packed
into the available program memory space.
The COP8 family offers a wide range of packages and do not
waste pins: up to 90.9% (or 40 pins in the 44-pin package)
are devoted to useful I/O.
1.3.1 Key Instruction Set Features
The COP8SAx family incorporates a unique combination of
instruction set features, which provide designers with opti-
mum code efficiency and program memory utilization.
3
www.national.com
Connection Diagrams
DS012838-2
Top View
DS012838-3
Top View
DS012838-4
Top View
DS012838-39
Top View
DS012838-6
Top View
DS012838-5
Top View
FIGURE 2. Connection Diagrams
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4
Ordering Information
DS012838-8
FIGURE 3. Part Numbering Scheme
1k EPROM
2k EPROM
4k EPROM
4k EPROM
Windowed
Device
Temperature
Order Number
COP8SAA716M9
COP8SAA720M9
COP8SAA728M9
COP8SAA716N9
COP8SAA720N9
COP8SAA728N9
Package
16M
Order Number
Package
Order Number
Package
Order Number
Package
0˚C to +70˚C
20M
COP8SAB720M9
COP8SAB728M9
20M
28M
COP8SAC720M9
COP8SAC728M9
20M
28M
28M
16N
20N
COP8SAB720N9
COP8SAB728N9
20N
28N
COP8SAC720N9
COP8SAC728N9
COP8SAC740N9
COP8SAC744V9
20N
28N
40N
44V
COP8SAC720Q3
COP8SAC728Q3
COP8SAC740Q3
COP8SAC744J3
20Q
28Q
40Q
44J
28N
−40˚C to +85˚C
COP8SAA716M8
COP8SAA720M8
COP8SAA728M8
COP8SAA716N8
COP8SAA720N8
COP8SAA728N8
16M
20M
28M
16N
20N
28N
COP8SAB720M8
COP8SAB728M8
20M
28M
COP8SAC720M8
COP8SAC728M8
20M
28M
COP8SAB720N8
COP8SAB728N8
20N
28N
COP8SAC720N8
COP8SAC728N8
COP8SAC740N8
COP8SAC744V8
COP8SAC7SLB8
COP8SAC720M7
COP8SAC728M7
COP8SAC720N7
COP8SAC728N7
COP8SAC740N7
COP8SAC744V7
20N
28N
40N
44V
SLB
20M
28M
20N
28N
40N
44V
COP8SAA7SLB8
SLB
COP8SAB7SLB8
SLB
−40˚C to
+125˚C
5
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4.0 Electrical Characteristics
ESD Protection Level
2 kV
(Human Body Model)
80 mA
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
100 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at Any Pin
)
7V
−0.6V to VCC +0.6V
DC Electrical Characteristics
0˚C ≤ TA ≤ +70˚C unless otherwise specified.
Parameter
Operating Voltage
Conditions
Min
Typ
Max
Units
(Note 8)
2.7
5.5
V
Power Supply Rise Time from 0.0V
(On-Chip Power-On Reset Selected)
VCC Start Voltage to Guarantee POR
Power Supply Ripple (Note 3)
Supply Current (Note 4)
CKI = 10 MHz
10 ns
50 ms
0.25
V
V
Peak-to-Peak
0.1 VCC
VCC = 5.5V, tC = 1 µs
VCC = 4.5V, tC = 2.5 µs
VCC = 5.5V, CKI = 0 MHz
6
2.1
8
mA
mA
µA
CKI = 4 MHz
<
HALT Current (Note 5) —WATCHDOG Disabled
IDLE Current (Note 4)
4
CKI = 10 MHz
VCC = 5.5V, tC = 1 µs
VCC = 4.5V, tC = 2.5 µs
1.5
0.8
mA
mA
CKI = 4 MHz
Input Levels (VIH, VIL)
RESET
Logic High
0.8 VCC
V
V
Logic Low
0.2 VCC
CKI, All Other Inputs
Logic High
0.7 VCC
V
V
Logic Low
0.2 VCC
2.0
Value of the Internal Bias Resistor
for the Crystal/Resonator Oscillator
CKI Resistance to VCC or GND when R/C
Oscillator is Selected
0.5
5
1.0
8
MΩ
VCC = 5.5V
11
kΩ
Hi-Z Input Leakage (same as TRI-STATE output)
Input Pullup Current
VCC = 5.5V
−2
−40
+2
µA
µA
V
VCC = 5.5V, VIN = 0V
−250
G and L Port Input Hysteresis
0.25 VCC
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6
DC Electrical Characteristics (Continued)
0˚C ≤ TA ≤ +70˚C unless otherwise specified.
Parameter
Output Current Levels
Conditions
Min
Typ
Max
Units
D Outputs
Source
VCC = 4.5V, VOH = 3.3V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOL = 1.0V
VCC = 2.7V, VOL = 0.4V
−0.4
−0.2
10
mA
mA
mA
mA
Sink
2
L Port
Source (Weak Pull-Up)
VCC = 4.5V, VOH = 2.7V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOH = 3.3V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOL = 1.0V
VCC = 2.7V, VOL = 0.4V
VCC = 4.5V, VOL = 0.4V
VCC = 2.7V, VOL = 0.4V
−10
−2.5
−0.4
−0.2
10
−110
−33
µA
µA
Source (Push-Pull Mode)
mA
mA
mA
mA
mA
mA
Sink (L0–L3, Push-Pull Mode)
Sink (L4–L7, Push-Pull Mode)
2
1.6
0.7
All Others
Source (Weak Pull-Up Mode)
VCC = 4.5V, VOH = 2.7V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOH = 3.3V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOL = 0.4V
VCC = 2.7V, VOL = 0.4V
−10
−2.5
−0.4
−0.2
1.6
−110
−33
µA
µA
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
mA
mA
mA
mA
0.7
Allowable Sink Current per Pin (Note 8)
D Outputs and L0 to L3
All Others
15
3
mA
mA
mA
±
Maximum Input Current without Latchup
(Note 6)
200
RAM Retention Voltage, Vr
VCC Rise Time from a VCC ≥ 2.0V
Input Capacitance
2.0
12
V
(Note 9)
(Note 8)
(Note 8)
µs
pF
pF
7
Load Capacitance on D2
1000
7
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AC Electrical Characteristics
0˚C ≤ TA ≤ +70˚C unless otherwise specified.
Parameter
Instruction Cycle Time (tC)
Crystal/Resonator, External
Conditions
Min
Typ
Max
Units
4.5V ≤ VCC ≤ 5.5V
1.0
2.0
DC
DC
µs
µs
µs
µs
%
<
2.7V ≤ VCC 4.5V
Internal R/C Oscillator
4.5V ≤ VCC ≤ 5.5V
1.667
TBD
<
2.7V ≤ VCC 4.5V
±
35
R/C Oscillator Frequency Variation
4.5V ≤ VCC ≤ 5.5V
<
(Note 8)
2.7V ≤ VCC 4.5V
TBD
55
12
8
%
External CKI Clock Duty Cycle (Note 8)
fr = Max
45
%
Rise Time (Note 8)
Fall Time (Note 8)
Inputs
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
ns
ns
tSETUP
4.5V ≤ VCC ≤ 5.5V
200
500
60
ns
ns
ns
ns
<
2.7V ≤ VCC 4.5V
tHOLD
4.5V ≤ VCC ≤ 5.5V
<
2.7V ≤ VCC 4.5V
150
Output Propagation Delay (Note 7)
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
4.5V ≤ VCC ≤ 5.5V
0.7
1.75
1.0
µs
µs
µs
µs
ns
ns
ns
<
2.7V ≤ VCC 4.5V
All Others
4.5V ≤ VCC ≤ 5.5V
<
2.7V ≤ VCC 4.5V
2.5
MICROWIRE Setup Time (tUWS) (Note 7)
MICROWIRE Hold Time (tUWH) (Note 7)
MICROWIRE Output Propagation Delay (tUPD
MICROWIRE Maximum Shift Clock
Master Mode
20
56
)
220
500
1
kHz
Slave Mode
MHz
Input Pulse Width (Note 7)
Interrupt Input High Time
1
1
1
1
1
tC
tC
tC
tC
µs
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Reset Pulse Width
Note 2: t = Instruction cycle time (Clock input frequency divided by 10).
C
<
Note 3: Maximum rate of voltage change must be 0.5 V/ms.
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
CC
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of I HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5
DD
programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V ; WATCHDOG and clock monitor disabled.
CC
Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
>
Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
V
and the pins will have sink current to V when
CC CC
>
biased at voltages
V
(the pins do not have source current when biased at a voltage below V ). The effective resistance to V
is 750Ω (typical). These two
CC
CC
CC
<
pins will not latch up. The voltage at the pins must be limited to
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning
excludes ESD transients.
Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 8: Parameter characterized but not tested.
Note 9: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
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8
Absolute Maximum Ratings (Note 10)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 10: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
80 mA
100 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at Any Pin
)
7V
−0.6V to VCC +0.6V
ESD Protection Level
2 kV
(Human Body Model)
DC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified.
Parameter
Operating Voltage
Conditions
Min
Typ
Max
Units
2.7
5.5
V
Power Supply Rise Time from 0.0V
(On-Chip Power-On Reset Selected)
VCC Start Voltage to Guarantee POR
Power Supply Ripple (Note 12)
Supply Current (Note 13)
CKI = 10 MHz
(Note 17)
10 ns
50 ms
0.25
V
V
Peak-to-Peak
0.1 VCC
VCC = 5.5V, tC = 1 µs
6.0
mA
µA
<
HALT Current (Note 14) —WATCHDOG Disabled
IDLE Current (Note 13)
CKI = 10 MHz
VCC = 5.5V, CKI = 0 MHz
4
10.0
VCC = 5.5V, tC = 1 µs
1.5
mA
Input Levels (VIH, VIL)
RESET
Logic High
0.8 VCC
V
V
Logic Low
0.2 VCC
CKI, All Other Inputs
Logic High
0.7 VCC
V
V
Logic Low
0.2 VCC
2.0
Value of the Internal Bias Resistor
for the Crystal/Resonator Oscillator
CKI Resistance to VCC or GND when R/C
Oscillator is Selected
0.5
5
1.0
8
MΩ
VCC = 5.5V
11
kΩ
Hi-Z Input Leakage (same as TRI-STATE output)
Input Pullup Current
VCC = 5.5V
−2
−40
+2
µA
µA
V
VCC = 5.5V, VIN = 0V
−250
G and L Port Input Hysteresis
0.25 VCC
9
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DC Electrical Characteristics (Continued)
−40˚C ≤ TA ≤ +85˚C unless otherwise specified.
Parameter
Output Current Levels
D Outputs
Conditions
Min
Typ
Max
Units
Source
VCC = 4.5V, VOH = 3.3V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOL = 1.0V
VCC = 2.7V, VOL = 0.4V
−0.4
−0.2
10
mA
mA
mA
mA
Sink
2
L Port
Source (Weak Pull-Up)
VCC = 4.5V, VOH = 2.7V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOH = 3.3V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOL = 1.0V
VCC = 2.7V, VOL = 0.4V
VCC = 4.5V, VOL = 0.4V
VCC = 2.7V, VOL = 0.4V
−10.0
−2.5
−0.4
−0.2
10.0
2
−110
−33
µA
µA
Source (Push-Pull Mode)
Sink (L0–L3, Push-Pull Mode)
Sink (L4–L7, Push-Pull Mode)
mA
mA
mA
mA
mA
mA
1.6
0.7
All Others
Source (Weak Pull-Up Mode)
VCC = 4.5V, VOH = 2.7V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOH = 3.3V
VCC = 2.7V, VOH = 1.8V
VCC = 4.5V, VOL = 0.4V
VCC = 2.7V, VOL = 0.4V
−10.0
−2.5
−0.4
−0.2
1.6
−110
−33
µA
µA
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
mA
mA
mA
mA
0.7
Allowable Sink Current per Pin (Note 17)
D Outputs and L0 to L3
15
3
mA
mA
mA
V
All Others
±
Maximum Input Current without Latchup (Note 15)
RAM Retention Voltage, Vr
VCC Rise Time from a VCC ≥ 2.0V
Input Capacitance
200
2.0
12
(Note 18)
(Note 17)
(Note 17)
µs
7
pF
pF
Load Capacitance on D2
1000
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified.
Parameter
Instruction Cycle Time (tC)
Crystal/Resonator, External
Conditions
Min
Typ
Max
Units
4.5V ≤ VCC ≤ 5.5V
1.0
2.0
DC
DC
µs
µs
µs
µs
%
<
2.7V ≤ VCC 4.5V
Internal R/C Oscillator
4.5V ≤ VCC ≤ 5.5V
1.667
TBD
<
2.7V ≤ VCC 4.5V
±
R/C Oscillator Frequency Variation
(Note 17)
4.5V ≤ VCC ≤ 5.5V
35
TBD
55
<
2.7V ≤ VCC 4.5V
%
External CKI Clock Duty Cycle (Note 17)
Rise Time (Note 17)
fr = Max
45
%
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
12
ns
ns
Fall Time (Note 17)
8
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10
AC Electrical Characteristics (Continued)
−40˚C ≤ TA ≤ +85˚C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Inputs
tSETUP
4.5V ≤ VCC ≤ 5.5V
200
500
60
ns
ns
ns
ns
<
2.7V ≤ VCC 4.5V
tHOLD
4.5V ≤ VCC ≤ 5.5V
<
2.7V ≤ VCC 4.5V
150
Output Propagation Delay (Note 16)
PD1, tPD0
RL = 2.2k, CL = 100 pF
t
SO, SK
4.5V ≤ VCC ≤ 5.5V
0.7
1.75
1.0
µs
µs
µs
µs
ns
ns
ns
<
2.7V ≤ VCC 4.5V
All Others
4.5V ≤ VCC ≤ 5.5V
<
2.7V ≤ VCC 4.5V
2.5
MICROWIRE Setup Time (tUWS) (Note 16)
MICROWIRE Hold Time (tUWH) (Note 16)
MICROWIRE Output Propagation Delay (tUPD
MICROWIRE Maximum Shift Clock
Master Mode
20
56
)
220
500
1
kHz
Slave Mode
MHz
Input Pulse Width (Note 17)
Interrupt Input High Time
1
1
1
1
1
tC
tC
tC
tC
µs
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Reset Pulse Width
Note 11: t = Instruction cycle time (Clock input frequency divided by 10).
C
<
Note 12: Maximum rate of voltage change must be 0.5 V/ms.
Note 13: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
CC
and outputs driven low but not connected to a load.
Note 14: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of I HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5
DD
programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V ; clock monitor disabled. Parameter refers
CC
to HALT mode entered via setting bit 7 of the G Port data register.
>
Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
V
and the pins will have sink current to V when
CC CC
>
biased at voltages
V
(the pins do not have source current when biased at a voltage below V ). The effective resistance to V
pins will not latch up. The voltage at the pins must be limited to 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes
ESD transients.
is 750Ω (typical). These two
CC
CC
CC
<
Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 17: Parameter characterized but not tested.
Note 18: Rise times faster than this specification may reset the device if POR is enabled and may affect the value of Idle Timer T0 if POR is not enabled.
DS012838-9
FIGURE 4. MICROWIRE/PLUS Timing
11
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Absolute Maximum Ratings (Note 19)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 19: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
80 mA
100 mA
−65˚C to +140˚C
Supply Voltage (VCC
Voltage at Any Pin
)
7V
−0.6V to VCC +0.6V
ESD Protection Level
2 kV
(Human Body Model)
DC Electrical Characteristics
−40˚C ≤ TA ≤ +125˚C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Operating Voltage
4.5
5.5
V
Power Supply Rise Time from 0.0V
(On-Chip Power-On Reset Selected)
VCC Start Voltage to Guarantee POR
Power Supply Ripple (Note 12)
Supply Current (Note 13)
(Note 17)
10 ns
50 ms
0.25
V
V
Peak-to-Peak
0.1 VCC
CKI = 10 MHz
VCC = 5.5V, tC = 1 µs
6.0
30
mA
µA
<
10
HALT Current (Note 14) —WATCHDOG
Disabled
VCC = 5.5V, CKI = 0 MHz
IDLE Current (Note 13)
CKI = 10 MHz
VCC = 5.5V, tC = 1 µs
1.5
mA
Input Levels (VIH, VIL)
RESET
Logic High
0.8 VCC
V
V
Logic Low
0.2 VCC
CKI, All Other Inputs
Logic High
0.7 VCC
V
V
Logic Low
0.2 VCC
2.0
Value of the Internal Bias Resistor
for the Crystal/Resonator Oscillator
CKI Resistance to VCC or GND when R/C
Oscillator is Selected
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis
Output Current Levels
D Outputs
0.5
5
1.0
8
MΩ
VCC = 5.5V
11
kΩ
VCC = 5.5V
−5
−35
+5
µA
µA
V
VCC = 5.5V, VIN = 0V
−400
0.25 VCC
Source
VCC = 4.5V, VOH = 3.3V
VCC = 4.5V, VOL = 1.0V
−0.4
9
mA
mA
Sink
L Port
Source (Weak Pull-Up)
Source (Push-Pull Mode)
Sink (L0–L3, Push-Pull Mode)
Sink (L4–L7, Push-Pull Mode)
All Others
VCC = 4.5V, VOH = 2.7V
VCC = 4.5V, VOH = 3.3V
VCC = 4.5V, VOL = 1.0V
VCC = 4.5V, VOL = 0.4V
−9
−0.4
9
−140
µA
mA
mA
mA
1.4
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
VCC = 4.5V, VOH = 2.7V
VCC = 4.5V, VOH = 3.3V
VCC = 4.5V, VOL = 0.4V
VCC = 5.5V
−9
−0.4
1.4
−5
−140
+5
µA
mA
mA
µA
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12
DC Electrical Characteristics (Continued)
−40˚C ≤ TA ≤ +125˚C unless otherwise specified.
Parameter
Allowable Sink Current per Pin (Note 17)
D Outputs and L0 to L3
All Others
Conditions
Min
Typ
Max
Units
15
3
mA
mA
mA
±
Maximum Input Current without Latchup
(Note 15)
Room Temp
200
RAM Retention Voltage, Vr
VCC Rise Time from a VCC ≥ 2.0V
Input Capacitance
2.0
12
V
(Note 18)
(Note 17)
(Note 17)
µs
pF
pF
7
Load Capacitance on D2
1000
AC Electrical Characteristics
−40˚C ≤ TA ≤ +125˚C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tC)
Crystal/Resonator, External
Internal R/C Oscillator
R/C Oscillator Frequency Variation
(Note 6)
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.0
DC
DC
µs
µs
%
1.667
TBD
External CKI Clock Duty Cycle (Note 6)
Rise Time (Note 6)
fr = Max
45
55
12
8
%
ns
ns
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
Fall Time (Note 6)
Inputs
tSETUP
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
RL = 2.2k, CL = 100 pF
200
60
ns
ns
tHOLD
Output Propagation Delay (Note 5)
tPD1, tPD0
SO, SK
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
0.7
1.0
µs
µs
ns
ns
ns
All Others
MICROWIRE Setup Time (tUWS) (Note 5)
MICROWIRE Hold Time (tUWH) (Note 5)
MICROWIRE Output Propagation Delay (tUPD
MICROWIRE Maximum Shift Clock
Master Mode
20
56
)
220
500
1
kHz
Slave Mode
MHz
Input Pulse Width (Note 6)
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
1
1
1
1
1
tC
tC
tC
tC
µs
13
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not selected. If WATCHDOG feature is selected, bit 1 of the
Port G configuration and data register does not have any
effect on Pin G1 setup. Pin G7 is either input or output
depending on the oscillator option selected. With the crystal
oscillator option selected, G7 serves as the dedicated output
pin for the CKO clock output. With the internal R/C or the
external oscillator option selected, G7 serves as a general
purpose Hi-Z input pin and is also used to bring the device
out of HALT mode with a low to high transition on G7. There
are two registers associated with Port G, a data register and
a configuration register. Using these registers, each of the 5
I/O pins (G0, G2–G5) can be individually configured under
software control.
5.0 Pin Descriptions
COP8SAx I/O structure minimizes external component
requirements. Software-switchable I/O enables designers
to reconfigure the microcontroller’s I/O functions with a
single instruction. Each individual I/O pin can be indepen-
dently configured as an output pin low, an output high, an
input with high impedance or an input with a weak pull-up
device. A typical example is the use of I/O pins as the
keyboard matrix input lines. The input lines can be pro-
grammed with internal weak pull-ups so that the input
lines read logic high when the keys are all up. With a key
closure, the corresponding input line will read a logic zero
since the weak pull-up can easily be overdriven. When the
key is released, the internal weak pullup will pull the input
line back to logic high. This flexibility eliminates the need
for external pull-up resistors. The High current options are
available for driving LEDs, motors and speakers. This
flexibility helps to ensure a cleaner design, with less ex-
ternal components and lower costs. Below is the general
description of all available pins.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose
input (R/C or external clock option), the associated bits in the
data and configuration registers for G6 and G7 are used for
special purpose functions as outlined below. Reading the G6
and G7 data bits will return zeroes.
The device will be placed in the HALT mode by writing a “1”
to bit 7 of the Port G Data Register. Similarly the device will
be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
VCC and GND are the power supply pins. All VCC and
GND pins must be connected.
CKI is the clock input. This can come from the Internal
R/C oscillator, external, or a crystal oscillator (in conjunc-
tion with CKO). See Oscillator Description section.
Writing a “1” to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alter-
nate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
RESET is the master reset input. See Reset description
section.
The device contains four bidirectional 8-bit I/O ports (C, G,
L and F), where each individual bit may be independently
configured as an input (Schmitt trigger inputs on ports L
and G), output or TRI-STATE under program control.
Three data memory address locations are allocated for
each of these I/O ports. Each I/O port has two associated
8-bit memory mapped registers, the CONFIGURATION
register and the output DATA register. A memory mapped
address is also reserved for the input pins of each I/O
port. (See the memory map for the various addresses
associated with the I/O ports.) Figure 5 shows the I/O port
configurations. The DATA and CONFIGURATION regis-
ters allow for each port bit to be individually configured
under software control as shown below:
Config. Reg.
CLKDLY
Alternate SK
Data Reg.
HALT
IDLE
G7
G6
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
CONFIGURATION
DATA
Register
0
Port Set-Up
Register
G1 WDOUT WATCHDOG and/or CLock Monitor if WATCH-
DOG enabled, otherwise it is a general purpose I/O
0
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation on these unterminated pins
will return unpredictable values. Only the COP8SAC7 device
contains Port C. The 20/28 pin devices do not offer Port C.
On these devices, the associated Port C Data and Configu-
ration registers should not be used.
0
1
1
1
0
1
Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on
the inputs.
Port L supports the Multi-Input Wake Up feature on all eight
pins. The 16-pin device does not have a full complement of
Port L pins. The unavailable pins are not terminated. A read
operation these unterminated pins are not terminated. A read
operation these unterminated pins will return unpredictable
values. To minimize current drain, the unavailable pins must
be programmed as outputs.
Port F is an 8-bit I/O port. The 28-pin device does not have
a full complement of Port F pins. The unavailable pins are
not terminated. A read operation on these unterminated pins
will return unpredictable values.
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O
ports. Pin G6 is always a general purpose Hi-Z input. All pins
have Schmitt Triggers on their inputs. Pin G1 serves as the
dedicated WDOUT WATCHDOG output with weak pullup
if WATCHDOG feature is selected by the ECON register.
The pin is a general purpose I/O if WATCHDOG feature is
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14
5.0 Pin Descriptions (Continued)
6.0 Functional Description
The architecture of the device is a modified Harvard archi-
tecture. With the Harvard architecture, the program memory
EPROM is separated from the data store memory (RAM).
Both EPROM and RAM have their own separate addressing
space with separate address buses. The architecture,
though based on the Harvard architecture, permits transfer
of data from EPROM to RAM.
6.1 CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (tC) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
DS012838-10
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
FIGURE 5. I/O Port Configurations
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). With reset the SP is initialized to
RAM address 02F Hex (devices with 64 bytes of RAM), or
initialized to RAM address 06F Hex (devices with 128 bytes
of RAM).
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
6.2 PROGRAM MEMORY
The program memory consists of 1024, 2048, or 4096 bytes
of EPROM or ROM. Table 1 shows the program memory
sizes for the different devices. These bytes may hold pro-
gram instructions or constant data (data tables for the LAID
instruction, jump vectors for the JID instruction, and interrupt
vectors for the VIS instruction). The program memory is
addressed by the 15-bit program counter (PC). All interrupts
in the device vector to program memory location 0FF Hex.
The program memory reads 00 Hex in the erased state.
DS012838-12
FIGURE 6. I/O Port Configurations—Output Mode
6.3 DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
The data memory consists of 64 or 128 bytes of RAM. Table
1 shows the data memory sizes for the different devices.
Fifteen bytes of RAM are mapped as “registers” at ad-
dresses 0F0 to 0FE Hex. These registers can be loaded
immediately, and also decremented and tested with the
DRSZ (decrement register and skip if zero) instruction. The
memory pointer registers X, SP and B are memory mapped
into this space at address locations 0FC to 0FE Hex respec-
tively, with the other registers (except 0FF) being available
for general usage. Address location 0FF is reserved for
future RAM expansion. If compatibility with future devices
(with more RAM) is not desired, this location can be used as
a general purpose RAM location.
DS012838-11
FIGURE 7. I/O Port Configurations—Input Mode
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs
(except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.7 V
to prevent the chip from entering special modes. Also
CC
keep the external loading on D2 to less than 1000 pF.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
15
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6.5 USER STORAGE SPACE IN EPROM
6.0 Functional Description (Continued)
In addition to the ECON register, there are 8 bytes of
EPROM available for “user information”. ECON and these 8
bytes are outside of the code area and are not protected by
the security bit of the ECON register. Even when security is
set, information in the 8-byte USER area is both read and
write enabled allowing the user to read from and write into
the area at all times while still protecting the code from
unauthorized access.
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumu-
lator (A) bits can also be directly and individually tested.
RAM contents are undefined upon power-up.
TABLE 1. Program/Data Memory Sizes
Program
Memory
(Bytes)
1024
Data
Memory
(Bytes)
64
User
Both ECON and USER area, 9 bytes total, are outside of the
normal address range of the EPROM and can not be ac-
cessed by the executing software. This allows for the stor-
age of non-secured information. Typical uses are for storage
of serial numbers, data codes, version numbers, copyright
information, lot numbers, etc.
Device
Storage
(Bytes)
COP8SAA7
COP8SAB7
COP8SAC7
8
8
8
2048
128
The COP8 assembler defines a special ROM section type,
CONF, into which the ECON and USER data may be coded.
Both ECON and User Data are programmed automatically
by programmers that are certified by National.
4096
128
6.4 ECON (CONFIGURATION) REGISTER
The ECON register is used to configure the user selectable
clock, security, power-on reset, WATCHDOG, and HALT
options. The register can be programmed and read only in
EPROM programming mode. Therefore, the register should
be programmed at the same time as the program memory.
The contents of the ECON register shipped from the factory
read 00 Hex (windowed device), 80 Hex (OTP device) or as
specified by the customer (ROM device).
The following examples illustrate the declaration of ECON
and the User information.
Syntax:
[label:] .sect econ, conf
.db
value ;1 byte,
;configures options
.db
The format of the ECON register is as follows:
.endsect<user information>
;up to 8 bytes
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Example: The following sets a value in the ECON register
and User Identification for a COP8SAC728M7. The ECON
bit values shown select options: Power-on enabled, Security
disabled, Crystal oscillator with on-chip bias disabled,
WATCHDOG enabled and HALT mode enabled.
X
POR SECURITY
CKI 2
CKI 1 WATCH Reserved HALT
DOG
Bit 7
Bit 6
= x
This is for factory test. The polarity is al-
ways 0.
= 1
= 0
= 1
Power-on reset enabled.
Power-on reset disabled.
.chip 8SAC
.sect econ, conf
Bit 5
Security enabled. EPROM read and write
are not allowed.
.db 0x55
;por, extal, wd, halt
.db 'my v1.00' ;user data declaration
.endsect
...
.end start
= 0
Security disabled. EPROM read and write
are allowed.
Bits 4, 3 = 0, 0 External CKI option selected. G7 is avail-
able as a HALT restart and/or general pur-
pose input. CKI is clock input.
Note: All programmers certified for programming this family of parts will
support programming of the CONFiguration section. Please contact
National or your device programmer supplier for more information.
= 0, 1 R/C oscillator option selected. G7 is avail-
able as a HALT restart and/or general pur-
pose input. CKI clock input. Internal R/C
components are supplied for maximum
R/C frequency.
6.6 OTP SECURITY
The device has a security feature that, when enabled, pre-
vents external reading of the OTP program memory. The
security bit in the ECON register determines, whether secu-
rity is enabled or disabled. If the security feature is disabled,
the contents of the internal EPROM may be read.
= 1, 0 Crystal oscillator with on-chip crystal bias
resistor disabled. G7 (CKO) is the clock
generator output to crystal/resonator.
If the security feature is enabled, then any attempt to
externally read the contents of the EPROM will result in
the value FF Hex being read from all program locations.
Under no circumstances can a secured part be read. In
addition, with the security feature enabled, the write opera-
tion to the EPROM program memory and ECON register is
inhibited. The ECON register is readable regardless of the
state of the security bit. The security bit, when set, cannot
be erased, even in windowed packages. If the security bit
is set in a device in a windowed package, that device may be
erased but will not be further programmable.
= 1, 1 Crystal oscillator with on-chip crystal bias
resistor enabled. G7 (CKO) is the clock
generator output to crystal/resonator.
Bit 2
= 1
WATCHDOG feature disabled. G1 is a
general purpose I/O.
= 0
WATCHDOG feature enabled. G1 pin is
WATCHDOG output with waek pullup.
Bit 1
Bit 0
=
Reserved.
= 1
= 0
HALT mode disabled.
HALT mode enabled.
If security is being used, it is recommended that all other bits
in the ECON register be programmed first. Then the security
bit can be programmed.
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16
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 tC–32 tC clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will go high.
6.0 Functional Description (Continued)
6.7 RESET
The device is initialized when the RESET pin is pulled low or
the On-chip Power-On Reset is enabled.
6.7.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up ini-
tialization, the user must ensure that the RESET pin is held
low until the device is within the specified VCC voltage. An
R/C circuit on the RESET pin with a delay 5 times (5x)
greater than the power supply rise time or 15 µs whichever is
greater, is recommended. Reset should also be wide enough
to ensure crystal start-up upon Power-Up.
DS012838-13
FIGURE 8. Reset Logic
RESET may also be used to cause an exit from the HALT
mode.
The following occurs upon initialization:
Port L: TRISTATE
A recommended reset circuit for this deviced is shown in
Figure 9.
Port C: TRISTATE
Port G: TRISTATE
Port F: TRISTATE
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR: UNAFFECTED after RESET with power already
applied
RANDOM after RESET at power-on
T1CNTRL: CLEARED
DS012838-14
>
RC 5x power supply rise time or 15 µs, whichever is greater.
Accumulator, Timer 1:
RANDOM after RESET with crystal clock option
(power already applied)
FIGURE 9. Reset Circuit Using External Reset
6.7.2 On-Chip Power-On Reset
UNAFFECTED after RESET with R/C clock option
(power already applied)
The on-chip reset circuit is selected by a bit in the ECON
register. When enabled, the device generates an internal
reset as VCC rises to a voltage level above 2.0V. The on-chip
reset circuitry is able to detect both fast and slow rise times
on VCC (VCC rise time between 10 ns and 50 ms).
RANDOM after RESET at power-on
WKEN, WKEDG: CLEARED
WKPND: RANDOM
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
RESET pin should be connected directly to VCC. The output
of the power-on reset detector will always preset the Idle
timer to 0FFF(4096 tC). At this time, the internal reset will be
generated.
SP (Stack Pointer):
Initialized to RAM address 02F Hex (devices with
64 bytes of RAM), or initialized to
RAM address 06F Hex (devices with
128 bytes of RAM).
If the Power-On Reset feature is enabled, the internal reset
will not be turned off until the Idle timer underflows. The
internal reset will perform the same functions as external
reset. The user is responsible for ensuring that VCC is at the
minimum level for the operating frequency within the 4096
tC. After the underflow, the logic is designed such that no
additional internal resets occur as long as VCC remains
above 2.0V.
Note: While the POR feature of the COP8SAx was never intended to function
as a brownout detector, there are certain constraints of this block that
the system designer must address to properly recover from a brownout
condition. This is true regardless of whether the internal POR or the
external reset feature is used.
B and X Pointers:
UNAFFECTED after RESET with power
already applied
RANDOM after RESET at power-on
RAM:
UNAFFECTED after RESET with power already
applied
RANDOM after RESET at power-on
WATCHDOG (if enabled):
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are
inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k tC clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
A brownout condition is reached when V
of the device goes below
CC
the minimum operating conditions of the device. The minimum guar-
@
anteed operating conditions are defined as V = 4.5V 10 MHz CKI,
CC
@
= 2.7V 4 MHz, or V = 2.0V during HALT mode (or when CKI
CC
V
CC
is stopped) operation.
When using either the external reset or the POR feature to recover
from a brownout condition, V
must be lowered to 0.25V or an
CC
external reset must be applied whenever it goes below the minimum
operating conditions as stated above.
17
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6.8.1 Crystal Oscillator
6.0 Functional Description (Continued)
The crystal Oscillator mode can be selected by programming
ECON Bit 4 to 1. CKI is the clock input while G7/CKO is the
clock generator output to the crystal. An on-chip bias resistor
connected between CKI and CKO can be enabled by pro-
gramming ECON Bit 3 to 1 with the crystal oscillator option
selection. The value of the resistor is in the range of 0.5M to
2M (typically 1.0M). Table 3 shows the component values
required for various standard crystal values. Resistor R2 is
only used when the on-chip bias resistor is disabled. Figure
12 shows the crystal oscillator connection diagram.
The contents of data registers and RAM are unknown fol-
lowing the on-chip reset.
TABLE 3. Crystal Oscillator Configuration,
TA = 25˚C, VCC = 5V
R1 (kΩ) R2 (MΩ) C1 (pF) C2 (pF)
CKI Freq. (MHz)
0
0
1
1
1
1
30
32
30
32
15
10
0
45
30–36
100–156
4
5.6
100
0.455
6.8.2 External Oscillator
The External Oscillator mode can be selected by program-
ming ECON Bit 3 to 0 and ECON Bit 4 to 0. CKI can be
driven by an external clock signal provided it meets the
specified duty cycle, rise and fall times, and input levels.
G7/CKO is available as a general purpose input G7 and/or
Halt control. Figure 13 shows the external oscillator connec-
tion diagram.
6.8.3 R/C Oscillator
DS012838-15
The R/C Oscillator mode can be selected by programming
ECON Bit 3 to 1 and ECON Bit 4 to 0. In R/C oscillation
mode, CKI is left floating, while G7/CKO is available as a
general purpose input G7 and/or HALT control. The R/C
controlled oscillator has on-chip resistor and capacitor for
maximum R/C oscillator frequency operation. The maximum
FIGURE 10. Reset Timing (Power-On Reset Enabled)
with VCC Tied to RESET
±
frequency is 6 MHz
35% for VCC between 4.5V to 5.5V
and temperature range of −40˚C to +85˚C. For max fre-
quency operation, the CKI pin should be left floating. For
lower frequencies, an external capacitor should be con-
nected between CKI and either VCC or GND. Immunity of the
R/C oscillator to external noise can be improved by connect-
ing one half the external capacitance to VCC and one half to
GND. PC board trace length on the CKI pin should be kept
as short as possible. Table 4 shows the oscillator frequency
as a function of approximate external capacitance on the
CKI pin. Figure 14 shows the R/C oscillator configuration.
DS012838-16
FIGURE 11. Reset Circuit Using Power-On Reset
6.8 OSCILLATOR CIRCUITS
There are four clock oscillator options available: Crystal
Oscillator with or without on-chip bias resistor, R/C Oscillator
with on-chip resistor and capacitor, and External Oscillator.
The oscillator feature is selected by programming the ECON
register, which is summarized in Table 2.
TABLE 4. R/C Oscillator Configuration,
−40˚C to +85˚C, VCC = 4.5V to 5.5V,
±
OSC Freq. Variation of 35%
TABLE 2. Oscillator Option
External Capacitor
R/C OSC Freq
Instr. Cycle
(µs)
ECON4 ECON3
Oscillator Option
External Oscillator
(pF)
0
(MHz)
0
1
0
1
0
0
1
1
6
1.667
2.5
Crystal Oscillator without Bias Resistor
R/C Oscillator
13
4
62
2
1
5.0
Crystal Oscillator with Bias Resistor
120
5600
10
32 kHz
312.5
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18
6.0 Functional Description (Continued)
With On-Chip Bias Resistor
Without On-Chip Bias Resistor
DS012838-17
DS012838-18
FIGURE 12. Crystal Oscillator
DS012838-19
FIGURE 13. External Oscillator
DS012838-20
DS012838-21
For operation at lower than maximum R/C oscillator frequency.
For operation at maximum R/C oscillator frequency.
FIGURE 14. R/C Oscillator
19
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T1ENB
Timer T1 Interrupt Enable for T1B Input cap-
ture edge
6.0 Functional Description (Continued)
6.9 CONTROL REGISTERS
7.0 Timers
CNTRL Register (Address X'00EE)
The device contains a very versatile set of timers (T0, T1).
Timer T1 and associated autoreload/capture registers power
up containing random data.
T1C3 T1C2 T1C1 T1C0 MSEL IEDG
Bit 7
SL1
SL0
Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
7.1 TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0. The Timer
T0 runs continuously at the fixed rate of the instruction cycle
clock, tC. The user cannot read or write to the IDLE Timer T0,
which is a count down timer.
T1C3
T1C2
T1C1
T1C0
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
The Timer T0 supports the following functions:
•
•
•
•
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
MSEL
IEDG
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
Timing the width of the internal power-on-reset
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
The IDLE Timer T0 can generate an interrupt when the
twelfth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4.096 ms at the maximum
clock frequency (tC = 1 µs). A control flag T0EN allows the
interrupt from the twelfth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while reset-
ting it will disable the interrupt.
PSW Register (Address X'00EF)
HC
C
T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 0
Bit 7
The PSW register contains the following select bits:
7.2 TIMER T1
HC
C
Half Carry Flag
Carry Flag
One of the main functions of a microcontroller is to provide
timing and counting capability for real-time control tasks. The
COP8 family offers a very versatile 16-bit timer/counter
structure, and two supporting 16-bit autoreload/capture reg-
isters (R1A and R1B), optimized to reduce software burdens
in real-time control applications. The timer block has two pins
associated with it, T1A and T1B. Pin T1A supports I/O re-
quired by the timer block, while pin T1B is an input to the
timer block.
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
T1ENA
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
EXPND External interrupt pending
BUSY
EXEN
GIE
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
The timer block has three operating modes: Processor Inde-
pendent PWM mode, External Event Counter mode, and
Input Capture mode.
Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
The control bits T1C3, T1C2, and T1C1 allow selection of the
different modes of operation.
7.2.1 Mode 1. Processor Independent PWM Mode
One of the timer’s operating modes is the Processor Inde-
pendent PWM mode. In this mode, the timer generates a
“Processor Independent” PWM signal because once the
timer is setup, no more action is required from the CPU
which translates to less software overhead and greater
throughput. The user software services the timer block only
when the PWM parameters require updating. This capability
is provided by the fact that the timer has two separate 16-bit
reload registers. One of the reload registers contains the
“ON” timer while the other holds the “OFF” time. By contrast,
a microcontroller that has only a single reload register re-
quires an additional software to update the reload value
(alternate between the on-time/off-time).
ICNTRL Register (Address X'00E8)
Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
Bit 7
Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and should to zero
LPEN
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
T0PND
T0EN
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
µWPND
µWEN
The timer can generate the PWM output with the width and
duty cycle controlled by the values stored in the reload
registers. The reload registers control the countdown values
and the reload values are automatically written into the timer
when it counts down through 0, generating interrupt on each
reload. Under software control and with minimal overhead,
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
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20
Underflows from the timer are alternately latched into two
pending flags, T1PNDA and T1PNDB. The user must reset
these pending flags under software control. Two control
enable flags, T1ENA and T1ENB, allow the interrupts from
the timer underflow to be enabled or disabled. Setting the
timer enable flag T1ENA will cause an interrupt when a timer
underflow causes the R1A register to be reloaded into the
timer. Setting the timer enable flag T1ENB will cause an
interrupt when a timer underflow causes the R1B register to
be reloaded into the timer. Resetting the timer enable flags
will disable the associated interrupts.
7.0 Timers (Continued)
the PMW outputs are useful in controlling motors, triacs, the
intensity of displays, and in providing inputs for data acqui-
sition and sine wave generators.
In this mode, the timer T1 counts down at a fixed rate of tC.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, R1A and R1B. The very
first underflow of the timer causes the timer to reload from
the register R1A. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register R1B.
Either or both of the timer underflow interrupts may be
enabled. This gives the user the flexibility of interrupting
once per PWM period on either the rising or falling edge of
the PWM output. Alternatively, the user may choose to inter-
rupt on both edges of the PWM output.
The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the
timer for PWM mode operation.
Figure 15 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the T1A output
pin. The underflows can also be programmed to generate
interrupts.
DS012838-22
FIGURE 15. Timer in PWM Mode
7.2.2 Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, T1, is clocked by the input signal from the T1A pin. The
T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer
to be clocked either on a positive or negative edge from the
T1A pin. Underflows from the timer are latched into the
T1PNDA pending flag. Setting the T1ENA control flag will
cause an interrupt when the timer underflows.
In this mode the input pin T1B can be used as an indepen-
dent positive edge sensitive interrupt input if the T1ENB
control flag is set. The occurrence of a positive edge on the
T1B input pin is latched into the T1PNDB flag.
Figure 16 shows a block diagram of the timer in External
Event Counter mode.
DS012838-23
Note: The PWM output is not available in this mode since the T1A pin is
being used as the counter input clock.
FIGURE 16. Timer in External Event Counter Mode
21
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fied either as a positive or a negative edge. The trigger
condition for each input pin can be specified independently.
7.0 Timers (Continued)
7.2.3 Mode 3. Input Capture Mode
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the T1A and T1B pins will be respectively latched into the
pending flags, T1PNDA and T1PNDB. The control flag
T1ENA allows the interrupt on T1A to be either enabled or
disabled. Setting the T1ENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
T1A pin. Similarly, the flag T1ENB controls the interrupts
from the T1B pin.
The device can precisely measure external frequencies or
time external events by placing the timer block, T1, in the
input capture mode. In this mode, the reload registers serve
as independent capture registers, capturing the contents of
the timer when an external event occurs (transition on the
timer input pin). The capture registers can be read while
maintaining count, a feature that lets the user measure
elapsed time and time between events. By saving the timer
value when the external event occurs, the time of the exter-
nal event is recorded. Most microcontrollers have a latency
time because they cannot determine the timer value when
the external event occurs. The capture register eliminates
the latency time, thereby allowing the applications program
to retrieve the timer value stored in the capture register.
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer T1C0
pending flag (the T1C0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the T1C0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the T1ENA control flag. When a T1A interrupt
occurs in the Input Capture mode, the user must check both
the T1PNDA and T1C0 pending flags in order to determine
whether a T1A input capture or a timer underflow (or both)
caused the interrupt.
In this mode, the timer T1 is constantly running at the fixed tC
rate. The two registers, R1A and R1B, act as capture regis-
ters. Each register acts in conjunction with a pin. The register
R1A acts in conjunction with the T1A pin and the register
R1B acts in conjunction with the T1B pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
T1C3, T1C2 and T1C1, allow the trigger events to be speci-
Figure 17 shows a block diagram of the timer in Input Cap-
ture mode.
DS012838-24
FIGURE 17. Timer in Input Capture Mode
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22
T1PNDA Timer Interrupt Pending Flag
7.0 Timers (Continued)
T1ENA
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
7.3 TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
T1C3
T1C2
T1C1
T1C0
Timer mode control
Timer mode control
Timer mode control
T1PNDB Timer Interrupt Pending Flag
T1ENB
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below:
Interrupt A
Interrupt B
Source
Timer
Mode
T1C3
T1C2
T1C1
Description
Source
Counts On
1
1
0
0
1
0
PWM: T1A Toggle
Autoreload RA
Autoreload RA
Autoreload RB
Autoreload RB
tC
1
PWM: No T1A
Toggle
tC
0
0
0
0
0
1
0
1
0
External Event
Counter
Timer
Underflow
Pos. T1B Edge
Pos. T1B Edge
Pos. T1B Edge
Pos. T1A
Edge
2
External Event
Counter
Timer
Underflow
Pos. T1A
Edge
Captures:
Pos. T1A Edge
or Timer
tC
tC
tC
tC
T1A Pos. Edge
T1B Pos. Edge
Captures:
Underflow
1
0
1
1
1
1
0
1
1
Pos. T1A
Neg. T1B
Edge
T1A Pos. Edge
T1B Neg. Edge
Captures:
Edge or Timer
Underflow
3
Neg. T1A
Neg. T1B
Edge
T1A Neg. Edge
T1B Neg. Edge
Captures:
Edge or Timer
Underflow
Neg. T1A
Neg. T1B
Edge
T1A Neg. Edge
T1B Neg. Edge
Edge or Timer
Underflow
23
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with a low to high transition on the CKO (G7) pin. This
method precludes the use of the crystal clock configuration
(since CKO becomes a dedicated output), and so may only
be used with an R/C clock configuration. The third method of
exiting the HALT mode is by pulling the RESET pin low.
8.0 Power Save Modes
Today, the proliferation of battery-operated based applica-
tions has placed new demands on designers to drive power
consumption down. Battery-operated systems are not the
only type of applications demanding low power. The power
budget constraints are also imposed on those consumer/
industrial applications where well regulated and expensive
power supply costs cannot be tolerated. Such applications
rely on low cost and low power supply voltage derived di-
rectly from the “mains” by using voltage rectifier and passive
components. Low power is demanded even in automotive
applications, due to increased vehicle electronics content.
This is required to ease the burden from the car battery. Low
power 8-bit microcontrollers supply the smarts to control
battery-operated, consumer/industrial, and automotive appli-
cations.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to
generate a fixed delay to ensure that the oscillator has
indeed stabilized before allowing instruction execution. In
this case, upon detecting a valid Wakeup signal, only the
oscillator circuitry is enabled. The IDLE timer is loaded with
a value of 256 and is clocked with the tC instruction cycle
clock. The tC clock is derived by dividing the oscillator clock
down by a factor of 10. The Schmitt trigger following the CKI
inverter on the chip ensures that the IDLE timer is clocked
only when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The start-up time-out
from the IDLE timer enables the clock signals to be routed to
the rest of the chip.
The COP8SAx devices offer system designers a variety of
low-power consumption features that enable them to meet
the demanding requirements of today’s increasing range of
low-power applications. These features include low voltage
operation, low current drain, and power saving features such
as HALT, IDLE, and Multi-Input wakeup (MIWU).
The devices offer the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board os-
cillator circuitry and timer T0 are active but all other micro-
controller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
If an R/C clock option is being used, the fixed delay is
introduced optionally. A control bit, CLKDLY, mapped as
configuration bit G7, controls whether the delay is to be
introduced or not. The delay is included if CLKDLY is set,
and excluded if CLKDLY is reset. The CLKDLY bit is cleared
on reset.
The device has two options associated with the HALT mode.
The first option enables the HALT mode feature, while the
second option disables the HALT mode selected through bit
0 of the ECON register. With the HALT mode enable option,
the device will enter and exit the HALT mode as described
above. With the HALT disable option, the device cannot be
placed in the HALT mode (writing a “1” to the HALT flag will
have no effect, the HALT flag will remain “0”).
Clock Monitor if enabled can be active in both modes.
8.1 HALT MODE
The device can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. The WATCH-
DOG logic on the device is disabled during the HALT mode.
However, the clock monitor circuitry, if enabled, remains
active and will cause the WATCHDOG output pin (WDOUT)
to go low. If the HALT mode is used and the user does not
want to activate the WDOUT pin, the Clock Monitor should
be disabled after the device comes out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register). In the HALT mode, the power requirements of the
device are minimal and the applied voltage (VCC) may be
decreased to Vr (Vr = 2.0V) without altering the state of the
machine.
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
If the device is placed in the HALT mode, with the R/C
oscillator selected, the clock input pin (CKI) is forced to a
logic high internally. With the crystal or external oscillator the
CKI pin is TRI-STATE.
The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on Port L. The second method is
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8.0 Power Save Modes (Continued)
DS012838-25
FIGURE 18. Wakeup from HALT
8.2 IDLE MODE
The user can enter the IDLE mode with the Timer T0 inter-
rupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the “Enter Idle
Mode” instruction.
The device is placed in the IDLE mode by writing a “1” to the
IDLE flag (G6 data bit). In this mode, all activities, except the
associated on-board oscillator circuitry and the IDLE Timer
T0, are stopped.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the “Enter IDLE Mode” instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
As with the HALT mode, the device can be returned to
normal operation with a reset, or with a Multi-Input Wakeup
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the twelfth bit
(representing 4.096 ms at internal clock frequency of
10 MHz, tC = 1 µs) of the IDLE Timer toggles.
This toggle condition of the twelfth bit of the IDLE Timer T0 is
latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the twelfth bit of the IDLE Timer T0. The interrupt can be
enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
DS012838-26
FIGURE 19. Wakeup from IDLE
25
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An example may serve to clarify this procedure. Suppose we
wish to change the edge select from positive (low going high)
to negative (high going low) for L Port bit 5, where bit 5 has
previously been enabled for an input interrupt. The program
would be as follows:
8.0 Power Save Modes (Continued)
8.3 MULTI-INPUT WAKEUP
The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
RBIT 5, WKEN
; Disable MIWU
SBIT 5, WKEDG ; Change edge polarity
RBIT 5, WKPND ; Reset pending flag
Figure 20 shows the Multi-Input Wakeup logic.
SBIT 5, WKEN
; Enable MIWU
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the register WKEN. The reg-
ister WKEN is an 8-bit read/write register, which contains a
control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety
procedure should also be followed to avoid wakeup condi-
tions. After the selected L port bits have been changed from
output to input but before the associated WKEN bits are
enabled, the associated edge select bits in WKEDG should
be set or reset for the desired edge selects, followed by the
associated WKPND bits being cleared.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the register WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
Wakeup condition as a result of the edge change. First, the
associated WKEN bit should be reset, followed by the edge
select change in WKEDG. Next, the associated WKPND bit
should be cleared, followed by the associated WKEN bit
being re-enabled.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for
Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user must
clear the pending flags before attempting to enter the HALT
mode.
WKEN and WKEDG are all read/write registers, and are
cleared at reset. WKPND register contains random value
after reset.
DS012838-27
FIGURE 20. Multi-Input Wake Up Logic
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26
The Software trap has the highest priority while the default
VIS has the lowest priority.
9.0 Interrupts
Each of the six maskable inputs has a fixed arbitration
ranking and vector.
9.1 INTRODUCTION
The device supports eight vectored interrupts. Interrupt
sources include Timer 1, Timer T0, Port L Wakeup, Software
Trap, MICROWIRE/PLUS, and External Input.
Figure 21 shows the Interrupt Block Diagram.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
DS012838-28
FIGURE 21. Interrupt Block Diagram
27
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interrupt, and jump to the interrupt handling routine corre-
sponding to the highest priority enabled and active interrupt.
Alternately, the user may choose to poll all interrupt pending
and enable bits to determine the source(s) of the interrupt. If
more than one interrupt is active, the user’s program must
decide which interrupt to service.
9.0 Interrupts (Continued)
9.2 MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable.
Each maskable interrupt has an associated enable bit and
pending flag bit. The pending bit is set to 1 when the interrupt
condition occurs. The state of the interrupt enable bit, com-
bined with the GIE bit determines whether an active pending
flag actually triggers an interrupt. All of the maskable inter-
rupt pending and enable bits are contained in mapped con-
trol registers, and thus can be controlled by the software.
Within a specific interrupt service routine, the associated
pending bit should be cleared. This is typically done as early
as possible in the service routine in order to avoid missing
the next occurrence of the same type of interrupt event.
Thus, if the same event occurs a second time, even while the
first occurrence is still being serviced, the second occur-
rence will be serviced immediately upon return from the
current interrupt routine.
A maskable interrupt condition triggers an interrupt under the
following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
An interrupt service routine typically ends with an RETI
instruction. This instruction sets the GIE bit back to 1, pops
the address stored on the stack, and restores that address to
the program counter. Program execution then proceeds with
the next instruction that would have been executed had
there been no interrupt. If there are any valid interrupts
pending, the highest-priority interrupt is serviced immedi-
ately upon return from the previous interrupt.
3. The device is not processing a non-maskable interrupt.
(If
a non-maskable interrupt is being serviced, a
maskable interrupt must wait until that service routine is
completed.)
An interrupt is triggered only when all of these conditions are
met at the beginning of an instruction. If different maskable
interrupts meet these conditions simultaneously, the highest
priority interrupt will be serviced first, and the other pending
interrupts must wait.
9.3 VIS INSTRUCTION
The general interrupt service routine, which starts at address
00FF Hex, must be capable of handling all types of inter-
rupts. The VIS instruction, together with an interrupt vector
table, directs the device to the specific interrupt handling
routine based on the cause of the interrupt.
Upon Reset, all pending bits, individual enable bits, and the
GIE bit are reset to zero. Thus, a maskable interrupt condi-
tion cannot trigger an interrupt until the program enables it by
setting both the GIE bit and the individual enable bit. When
enabling an interrupt, the user should consider whether or
not a previously activated (set) pending bit should be ac-
knowledged. If, at the time an interrupt is enabled, any
previous occurrences of the interrupt should be ignored, the
associated pending bit must be reset to zero prior to en-
abling the interrupt. Otherwise, the interrupt may be simply
enabled; if the pending bit is already set, it will immediately
trigger an interrupt. A maskable interrupt is active if its asso-
ciated enable and pending bits are set.
VIS is a single-byte instruction, typically used at the very
beginning of the general interrupt service routine at address
00FF Hex, or shortly after that point, just after the code used
for context switching. The VIS instruction determines which
enabled and pending interrupt has the highest priority, and
causes an indirect jump to the address corresponding to that
interrupt source. The jump addresses (vectors) for all pos-
sible interrupts sources are stored in a vector table.
The vector table may be as long as 32 bytes (maximum of 16
vectors) and resides at the top of the 256-byte block con-
taining the VIS instruction. However, if the VIS instruction is
at the very top of a 256-byte block (such as at 00FF Hex),
the vector table resides at the top of the next 256-byte block.
Thus, if the VIS instruction is located somewhere between
00FF and 01DF Hex (the usual case), the vector table is
located between addresses 01E0 and 01FF Hex. If the VIS
instruction is located between 01FF and 02DF Hex, then the
vector table is located between addresses 02E0 and 02FF
Hex, and so on.
An interrupt is an asychronous event which may occur be-
fore, during, or after an instruction cycle. Any interrupt which
occurs during the execution of an instruction is not acknowl-
edged until the start of the next normally executed instruction
is to be skipped, the skip is performed before the pending
interrupt is acknowledged.
At the start of interrupt acknowledgment, the following ac-
tions occur:
1. The GIE bit is automatically reset to zero, preventing any
subsequent maskable interrupt from interrupting the cur-
rent service routine. This feature prevents one maskable
interrupt from interrupting another one being serviced.
Each vector is 15 bits long and points to the beginning of a
specific interrupt service routine somewhere in the 32 kbyte
memory space. Each vector occupies two bytes of the vector
table, with the higher-order byte at the lower address. The
vectors are arranged in order of interrupt priority. The vector
of the maskable interrupt with the lowest rank is located to
0yE0 (higher-order byte) and 0yE1 (lower-order byte). The
next priority interrupt is located at 0yE2 and 0yE3, and so
forth in increasing rank. The Software Trap has the highest
rank and its vector is always located at 0yFE and 0yFF. The
number of interrupts which can become active defines the
size of the table.
2. The address of the instruction about to be executed is
pushed onto the stack.
3. The program counter (PC) is loaded with 00FF Hex,
causing a jump to that program memory location.
The device requires seven instruction cycles to perform the
actions listed above.
If the user wishes to allow nested interrupts, the interrupts
service routine may set the GIE bit to 1 by writing to the PSW
register, and thus allow other maskable interrupts to interrupt
the current service routine. If nested interrupts are allowed,
caution must be exercised. The user must write the program
in such a way as to prevent stack overflow, loss of saved
context information, and other unwanted conditions.
Table 5 shows the types of interrupts, the interrupt arbitration
ranking, and the locations of the corresponding vectors in
the vector table.
The vector table should be filled by the user with the memory
locations of the specific interrupt service routines. For ex-
The interrupt service routine stored at location 00FF Hex
should use the VIS instruction to determine the cause of the
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28
gram context (A, B, X, etc.) and executing the RETI instruc-
tion, an interrupt service routine can be terminated by return-
ing to the VIS instruction. In this case, interrupts will be
serviced in turn until no further interrupts are pending and
the default VIS routine is started. After testing the GIE bit to
ensure that execution is not erroneous, the routine should
restore the program context and execute the RETI to return
to the interrupted program.
9.0 Interrupts (Continued)
ample, if the Software Trap routine is located at 0310 Hex,
then the vector location 0yFE and -0yFF should contain the
data 03 and 10 Hex, respectively. When a Software Trap
interrupt occurs and the VIS instruction is executed, the
program jumps to the address specified in the vector table.
The interrupt sources in the vector table are listed in order of
rank, from highest to lowest priority. If two or more enabled
and pending interrupts are detected at the same time, the
one with the highest priority is serviced first. Upon return
from the interrupt service routine, the next highest-level
pending interrupt is serviced.
This technique can save up to fifty instruction cycles (t
c), or
more, (50 µs at 10 MHz oscillator) of latency for pending
interrupts with a penalty of fewer than ten instruction cycles
if no further interrupts are pending.
To ensure reliable operation, the user should always use the
VIS instruction to determine the source of an interrupt. Al-
though it is possible to poll the pending bits to detect the
source of an interrupt, this practice is not recommended. The
use of polling allows the standard arbitration ranking to be
altered, but the reliability of the interrupt system is compro-
mised. The polling routine must individually test the enable
and pending bits of each maskable interrupt. If a Software
Trap interrupt should occur, it will be serviced last, even
though it should have the highest priority. Under certain
conditions, a Software Trap could be triggered but not ser-
viced, resulting in an inadvertent “locking out” of all
maskable interrupts by the Software Trap pending flag.
Problems such as this can be avoided by using VIS
instruction.
If the VIS instruction is executed, but no interrupts are en-
abled and pending, the lowest-priority interrupt vector is
used, and a jump is made to the corresponding address in
the vector table. This is an unusual occurrence, and may be
the result of an error. It can legitimately result from a change
in the enable bits or pending flags prior to the execution of
the VIS instruction, such as executing a single cycle instruc-
tion which clears an enable flag at the same time that the
pending flag is set. It can also result, however, from inad-
vertent execution of the VIS command outside of the context
of an interrupt.
The default VIS interrupt vector can be useful for applica-
tions in which time critical interrupts can occur during the
servicing of another interrupt. Rather than restoring the pro-
TABLE 5. Interrupt Vector Table
Arbitration
Ranking
Vector (Note 20)
Source
Description
Address
(Hi-Low Byte)
(1) Highest
(2)
Software
INTR Instruction
0yFE–0yFF
Reserved
External
Future
0yFC–0yFD
0yFA–0yFB
0yF8–0yF9
0yF6–0yF7
0yF4–0yF5
0yF2–0yF3
0yF0–0yF1
0yEE–0yEF
0yEC–0yED
0yEA–0yEB
0yE8–0yE9
0yE6–0yE7
0yE4–0yE5
0yE2–0yE3
0yE0–0yE1
(3)
G0
(4)
Timer T0
Underflow
(5)
Timer T1
T1A/Underflow
(6)
Timer T1
T1B
(7)
MICROWIRE/PLUS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Port L/Wakeup
BUSY Low
(8)
Future
(9)
Future
(10)
(11)
(12)
(13)
(14)
(15)
Future
Future
Future
Future
Future
Port L Edge
(16) Lowest Default
VIS Instruction
Execution without any interrupts
Note 20: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last
address of a block. In this case, the table must be in the next block.
29
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remains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration
ranking. This vector is read from program memory and
placed into the PC which is now pointed to the 1st instruction
of the service routine of the active interrupt with the highest
arbitration ranking.
9.0 Interrupts (Continued)
9.3.1 VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active
interrupt is software trap, than E0 is generated. This number
replaces the lower byte of the PC. The upper byte of the PC
Figure 22 illustrates the different steps performed by the VIS
instruction. Figure 23 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
DS012838-29
FIGURE 22. VIS Operation
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9.0 Interrupts (Continued)
DS012838-30
FIGURE 23. VIS Flowchart
31
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9.0 Interrupts (Continued)
Programming Example: External Interrupt
PSW
CNTRL
RBIT
RBIT
SBIT
SBIT
SBIT
JP
=00EF
=00EE
0,PORTGC
0,PORTGD
IEDG, CNTRL
GIE, PSW
EXEN, PSW
WAIT
; G0 pin configured Hi-Z
; Ext interrupt polarity; falling edge
; Set the GIE bit
; Enable the external interrupt
; Wait for external interrupt
WAIT:
.
.
.
.=0FF
VIS
; The interrupt causes a
; branch to address 0FF
;The VIS causes a branch to
;interrupt vector table
.
.
.
.=01FA
.ADDRW SERVICE
; Vector table (within 256 byte
; of VIS inst.) containing the ext
;interrupt service routine
.
.
.
SERVICE:
; Interrupt Service Routine
RBIT, EXPND, PSW
; Reset ext interrupt pend. bit
.
.
.
RET
; Return, set the GIE bit
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32
Programming a return to normal execution requires careful
consideration. If the Software Trap routine is interrupted by
another Software Trap, the RPND instruction in the service
routine for the second Software Trap will reset the STPND
flag; upon return to the first Software Trap routine, the
STPND flag will have the wrong state. This will allow
maskable interrupts to be acknowledged during the servicing
of the first Software Trap. To avoid problems such as this, the
user program should contain the Software Trap routine to
perform a recovery procedure rather than a return to normal
execution.
9.0 Interrupts (Continued)
9.4 NON-MASKABLE INTERRUPT
9.4.1 Pending Flag
There is a pending flag bit associated with the non-maskable
interrupt, called STPND. This pending flag is not
memory-mapped and cannot be accessed directly by the
software.
The pending flag is reset to zero when a device Reset
occurs. When the non-maskable interrupt occurs, the asso-
ciated pending bit is set to 1. The interrupt service routine
should contain an RPND instruction to reset the pending flag
to zero. The RPND instruction always resets the STPND
flag.
Under normal conditions, the STPND flag is reset by a
RPND instruction in the Software Trap service routine. If a
programming error or hardware condition (brownout, power
supply glitch, etc.) sets the STPND flag without providing a
way for it to be cleared, all other interrupts will be locked out.
To alleviate this condition, the user can use extra RPND
instructions in the main program and in the WATCHDOG
service routine (if present). There is no harm in executing
extra RPND instructions in these parts of the program.
9.4.2 Software Trap
The Software Trap is a special kind of non-maskable inter-
rupt which occurs when the INTR instruction (used to ac-
knowledge interrupts) is fetched from program memory and
placed in the instruction register. This can happen in a
variety of ways, usually because of an error condition. Some
examples of causes are listed below.
9.5 PORT L INTERRUPTS
Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into the
same service subroutine.
If the program counter incorrectly points to a memory loca-
tion beyond the available program memory space, the
non-existent or unused memory location returns zeroes
which is interpreted as the INTR instruction.
The interrupt from Port L shares logic with the wake up
circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
If the stack is popped beyond the allowed limit (address 02F
or 06F Hex), a Software Trap is triggered.
A Software Trap can be triggered by a temporary hardware
condition such as a brownout or power supply glitch.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
The Software Trap has the highest priority of all interrupts.
When a Software Trap occurs, the STPND bit is set. The GIE
bit is not affected and the pending bit (not accessible by the
user) is used to inhibit other interrupts and to direct the
program to the ST service routine with the VIS instruction.
Nothing can interrupt a Software Trap service routine except
for another Software Trap. The STPND can be reset only by
the RPND instruction or a chip Reset.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable inter-
rupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the
interrupt service routine and then revert to normal operation.
(See HALT MODE for clock option wakeup information.)
The Software Trap indicates an unusual or unknown error
condition. Generally, returning to normal execution at the
point where the Software Trap occurred cannot be done
reliably. Therefore, the Software Trap service routine should
reinitialize the stack pointer and perform a recovery proce-
dure that restarts the software at some known point, similar
to a device Reset, but not necessarily performing all the
same functions as a device Reset. The routine must also
execute the RPND instruction to reset the STPND flag.
Otherwise, all other interrupts will be locked out. To the
extent possible, the interrupt routine should record or indi-
cate the context of the device so that the cause of the
Software Trap can be determined.
9.6 INTERRUPT SUMMARY
The device uses the following types of interrupts, listed
below in order of priority:
1. The Software Trap non-maskable interrupt, triggered by
the INTR (00 opcode) instruction. The Software Trap is
acknowledged immediately. This interrupt service rou-
tine can be interrupted only by another Software Trap.
The Software Trap should end with two RPND instruc-
tions followed by a restart procedure.
If the user wishes to return to normal execution from the
point at which the Software Trap was triggered, the user
must first execute RPND, followed by RETSK rather than
RETI or RET. This is because the return address stored on
the stack is the address of the INTR instruction that triggered
the interrupt. The program must skip that instruction in order
to proceed with the next one. Otherwise, an infinite loop of
Software Traps and returns will occur.
2. Maskable interrupts, triggered by an on-chip peripheral
block or an external device connected to the device.
Under ordinary conditions, a maskable interrupt will not
interrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be inter-
rupted by the non-maskable interrupt request.
A
maskable interrupt routine should end with an RETI
instruction.
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10.2 WATCHDOG/CLOCK MONITOR OPERATION
10.0 WATCHDOG/Clock Monitor
The WATCHDOG is enabled by bit 2 of the ECON register.
When this ECON bit is 0, the WATCHDOG is enabled and
pin G1 becomes the WATCHDOG output with a weak pullup.
The devices contain a user selectable WATCHDOG and
clock monitor. The following section is applicable only if
WATCHDOG feature has been selected in the ECON regis-
ter. The WATCHDOG is designed to detect the user program
getting stuck in infinite loops resulting in loss of program
control or “runaway” programs.
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, in-
cluding the case where the oscillator fails to start.
The WATCHDOG logic contains two separate service win-
dows. While the user programmable upper window selects
the WATCHDOG service time, the lower window provides
protection against an infinite program loop that contains the
WATCHDOG service instruction.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCH-
DOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table 8 shows the se-
quence of events that can occur.
The COP8SAx devices provide the added feature of a soft-
ware trap that provides protection against stack overpops
and addressing locations outside valid user program space.
The Clock Monitor is used to detect the absence of a clock or
a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 6 shows the WDSVR register.
The user must service the WATCHDOG at least once before
the upper limit of the service window expires. The WATCH-
DOG may not be serviced more than once in every lower
limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
TABLE 6. WATCHDOG Service Register (WDSVR)
Window
Select
Key Data
Clock
Monitor
Y
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low and must be externally connected to the RESET pin or to
some other external logic which handles WATCHDOG event.
The WDOUT pin has a weak pullup in the inactive state. This
pull-up is sufficient to serve as the connection to VCC for
systems which use the internal Power On Reset. Upon
triggering the WATCHDOG, the logic will pull the WDOUT
(G1) pin low for an additional 16 tC–32 tC cycles after the
signal level on WDOUT pin goes below the lower Schmitt
trigger threshold. After this delay, the device will stop forcing
the WDOUT output low. The WATCHDOG service window
will restart when the WDOUT pin goes high.
X
X
0
1
1
0
0
The lower limit of the service window is fixed at 256 instruc-
tion cycles. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.
Table 7 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flex-
ibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
A WATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
time out and WDOUT will go high.
TABLE 7. WATCHDOG Service Window Select
WDSVR WDSVR
Clock
Service Window
(Lower-Upper Limits)
2048–8k tC Cycles
Bit 7
Bit 6
Monitor
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified
value, after which the G1 output will go high following 16
tC–32 tC clock cycles. The Clock Monitor generates a con-
tinual Clock Monitor error if the oscillator fails to start, or fails
to reach the minimum specified frequency. The specification
for the Clock Monitor is as follows:
0
0
1
1
x
x
0
1
0
1
x
x
x
x
x
x
0
1
2048–16k tC Cycles
2048–32k tC Cycles
2048–64k tC Cycles
Clock Monitor Disabled
Clock Monitor Enabled
>
1/tC 10 kHz—No clock rejection.
<
1/tC 10 Hz—Guaranteed clock rejection.
10.1 CLOCK MONITOR
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/tC) is greater or equal to 10 kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
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10.0 WATCHDOG/Clock Monitor (Continued)
TABLE 8. WATCHDOG Service Actions
Key
Window Clock
Action
Data
Data
Monitor
Match
Match
Match
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Don’t Care
Mismatch
Don’t Care
Mismatch
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Mismatch
10.3 WATCHDOG AND CLOCK MONITOR SUMMARY
•
A hardware WATCHDOG service occurs just as the de-
vice exits the IDLE mode. Consequently, the WATCH-
DOG should not be serviced for at least 256 instruction
cycles following IDLE, but must be serviced within the
selected window to avoid a WATCHDOG error.
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
•
Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET.
•
Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed any-
where within the maximum service window (65,536 in-
struction cycles) initialized by RESET. Note that this initial
WATCHDOG service may be programmed within the ini-
tial 256 instruction cycles without causing a WATCHDOG
error.
•
Following RESET, the WATCHDOG and CLOCK MONI-
TOR are both enabled, with the WATCHDOG having the
maximum service window selected.
•
•
•
•
The WATCHDOG service window and CLOCK MONI-
TOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in
order to avoid a WATCHDOG error.
•
In order to RESET the device on the occurrence of a
WATCH event, the user must connect the WDOUT pin
(G1) pin to the RESET external to the device. The weak
pull-up on the WDOUT pin is sufficient to provide the
RESET connection to VCC for devices which use both
Power On Reset and WATCHDOG.
Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG
errors.
The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
10.4 DETECTION OF ILLEGAL CONDITIONS
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
•
•
The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
Reading of undefined ROM gets zeroes. The opcode for
software interrupt is 00. If the program fetches instructions
from undefined ROM, this will force a software interrupt, thus
signaling that an illegal condition has occurred.
The CLOCK MONITOR detector circuit is active during
both the HALT and IDLE modes. Consequently, the de-
vice inadvertently entering the HALT mode will be de-
tected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program).
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each
return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more re-
turns than calls, the stack pointer will point to addresses 070
and 071 Hex (which are undefined RAM). Undefined RAM
from addresses 070 to 07F (Segment 0), and all other seg-
ments (i.e., Segments 4 … etc.) is read as all 1’s, which in
turn will cause the program to return to address 7FFF Hex.
This is an undefined ROM location and the instruction
fetched (all 0’s) from this location will generate a software
interrupt signaling an illegal condition.
•
•
With the single-pin R/C oscillator option selected and the
CLKDLY bit reset, the WATCHDOG service window will
resume following HALT mode from where it left off before
entering the HALT mode.
With the crystal oscillator option selected, or with the
single-pin R/C oscillator option selected and the CLKDLY
bit set, the WATCHDOG service window will be set to its
selected value from WDSVR following HALT. Conse-
quently, the WATCHDOG should not be serviced for at
least 256 instruction cycles following HALT, but must be
serviced within the selected window to avoid a WATCH-
DOG error.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM
•
•
The IDLE timer T0 is not initialized with external RESET.
2. Over “POP”ing the stack by having more returns than
calls.
The user can sync in to the IDLE counter cycle with an
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the twelfth bit of the
IDLE counter toggles (every 4096 instruction cycles). The
user is responsible for resetting the T0PND flag.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restart-
ing (this recovery program is probably similar to that follow-
ing reset, but might not contain the same program initializa-
tion procedures). The recovery program should reset the
software interrupt pending bit using the RPND instruction.
35
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11.1 MICROWIRE/PLUS OPERATION
11.0 MICROWIRE/PLUS
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 24 shows how
two microcontroller devices and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
MICROWIRE/PLUS is a serial SPI compatible synchronous
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with MICROWIRE/PLUS
or SPI peripherals (i.e. A/D converters, display drivers, EE-
PROMs etc.) and with other microcontrollers which support
the MICROWIRE/PLUS or SPI interface. It consists of an
8-bit serial shift register (SIO) with serial data input (SI),
serial data output (SO) and serial shift clock (SK). Figure 24
shows a block diagram of the MICROWIRE/PLUS logic.
WARNING
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift clock
is called the Slave mode of operation.
The SIO register should only be loaded when the SK clock is
in the idle phase. Loading the SIO register while the SK clock
is in the active phase, will result in undefined data in the SIO
register.
Setting the BUSY flag when the input SK clock is in the
active phase while in the MICROWIRE/PLUS is in the slave
mode may cause the current SK clock for the SIO shift
register to be narrow. For safety, the BUSY flag should only
be set when the input SK clock is in the idle phase.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table 9 details the
different clock rates that may be selected.
11.1.1 MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. In the slave mode, the shift clock
stops after 8 clock pulses. Table 10 summarizes the bit
settings required for Master mode of operation.
TABLE 9. MICROWIRE/PLUS
Master Mode Clock Select
SL1
0
SL0
SK Period
0
1
x
2 x tC
4 x tC
8 x tC
0
1
Where t is the instruction cycle clock
C
DS012838-32
FIGURE 24. MICROWIRE/PLUS Application
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36
The user must set the BUSY flag immediately upon entering
the Slave mode. This ensures that all data bits sent by the
Master is shifted properly. After eight clock pulses the BUSY
flag is clear, the shift clock is stopped, and the sequence
may be repeated.
11.0 MICROWIRE/PLUS (Continued)
11.1.2 MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
register. Table 10 summarizes the settings required to enter
the Slave mode of operation.
10.1.3 Alternate SK Phase Operation
and SK Idle Polarity
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted
in on the falling edge of the SK clock and shifted out on the
rising edge of the SK clock. Bit 6 of Port G configuration
register selects the SK edge.
This table assumes that the control flag MSEL is set.
TABLE 10. MICROWIRE/PLUS Mode Settings
G4 (SO)
Config. Bit
1
G5 (SK)
Config. Bit
1
G4
Fun.
SO
G5
Fun.
Int.
Operation
MICROWIRE/PLUS
Master
SK
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configu-
ration bit. The SKSEL flag will power up in the reset condi-
tion, selecting the normal SK signal.
0
1
0
1
0
0
TRI-
STATE
SO
Int.
MICROWIRE/PLUS
Master
SK
Ext.
SK
MICROWIRE/PLUS
Slave
TRI-
Ext.
SK
MICROWIRE/PLUS
Slave
STATE
TABLE 11. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
Port G
SK Idle
Phase
SK Phase
G6 (SKSEL)
G5
SO Clocked Out On:
SI Sampled On:
Config. Bit
Data Bit
Normal
Alternate
Alternate
Normal
0
1
0
1
0
0
1
1
SK Falling Edge
SK Rising Edge
SK Rising Edge
SK Falling Edge
SK Rising Edge
SK Falling Edge
SK Falling Edge
SK Rising Edge
Low
Low
High
High
DS012838-33
FIGURE 25. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
DS012838-34
FIGURE 26. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low
37
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11.0 MICROWIRE/PLUS (Continued)
DS012838-35
FIGURE 27. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High
DS012838-31
FIGURE 28. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High
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12.0 Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
RAM
Select
Address
ADD REG
02 to 2F
30 to 7F
00 to 6F
70 to 7F
80 to 93
94
Contents
On-Chip RAM (48 Bytes)
64 On-Chip RAM Bytes.
(COP8SAAx)
Unused RAM (Reads as all ones)
On-Chip RAM (112 Bytes)
Unused RAM (Reads as all ones)
Reserved
128 On-Chip RAM Bytes
(COP8SABx/SACx)
Port F Data Register
95
Port F Configuration Register
Port F Input Pins (Read Only)
Reserved
96
97
A0 to C6
C7
Reserved
WATCHDOG Service Register (Reg: WDSVR)
MIWU Edge Select Register (Reg: WKEDG)
MIWU Enable Register (Reg: WKEN)
MIWU Pending Register (Reg: WKPND)
Reserved
C8
C9
CA
CB to CF
D0
Port L Data Register
D1
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved
D2
D3
D4
Port G Data Register
D5
Port G Configuration Register
Port G Input Pins (Read Only)
Reserved
D6
D7
D8
Port C Data Register
D9
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved
DA
DB
DC
Port D
DD to DF
E0 to E5
E6
Reserved
Reserved
Timer T1 Autoload Register T1RB Lower Byte
Timer T1 Autoload Register T1RB Upper Byte
ICNTRL Register
E7
E8
E9
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
EA
EB
Timer T1 Upper Byte
EC
Timer T1 Autoload Register T1RA Lower Byte
Timer T1 Autoload Register T1RA Upper Byte
CNTRL Control Register
PSW Register
ED
EE
EF
F0 to FB
FC
On-Chip RAM Mapped as Registers
X Register
FD
SP Register
FE
B Register
FF
Reserved (Segment Register)
Reading any undefined memory location in the address range of 0080H–00FFH will return undefined data.
39
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•
•
Register B or X Indirect
Register or Indirect with Post-Incrementing/
13.0 Instruction Set
B
X
Decrementing
13.1 INTRODUCTION
•
•
•
Immediate
This section defines the instruction set of the COP8SAx
Family members. It contains information about the instruc-
tion set features, addressing modes and types.
Immediate Short
Indirect from Program Memory
The addressing modes are described below. Each de-
scription includes an example of an assembly language
instruction using the described addressing mode.
13.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the follow-
ing features:
Direct. The memory address is specified directly as a byte
in the instruction. In assembly language, the direct ad-
dress is written as a numerical value (or a label that has
been defined elsewhere in the program as a numerical
value).
•
•
•
•
•
•
Mostly single-byte opcode instructions minimize pro-
gram size.
One instruction cycle for the majority of single-byte
instructions to minimize program execution time.
Many single-byte, multiple function instructions such
as DRSZ.
Example: Load Accumulator Memory Direct
LD A,05
Three memory mapped pointers: two for register indi-
rect addressing, and one for the software stack.
Reg/Data
Memory
Contents
Before
Contents
After
Sixteen memory mapped registers that allow an opti-
mized implementation of certain instructions.
Accumulator
Memory Location
0005 Hex
XX Hex
A6 Hex
A6 Hex
A6 Hex
Ability to set, reset, and test any individual bit in data
memory
address
space,
including
the
memory-mapped I/O ports and registers.
Register B or X Indirect. The memory address is specified
by the contents of the B Register or X register (pointer
register). In assembly language, the notation [B] or [X] speci-
fies which register serves as the pointer.
•
Register-Indirect LOAD and EXCHANGE instructions
with optional automatic post-incrementing or decre-
menting of the register pointer. This allows for greater
efficiency (both in cycle time and program code) in
loading, walking across and processing fields in data
memory.
Example: Exchange Memory with Accumulator, B Indirect
X A,[B]
•
Unique instructions to optimize program size and
throughput efficiency. Some of these instructions are
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
Reg/Data
Memory
Contents
Before
Contents
After
Accumulator
Memory Location
0005 Hex
01 Hex
87 Hex
87 Hex
01 Hex
12.3 ADDRESSING MODES
The instruction set offers a variety of methods for speci-
fying memory addresses. Each method is called an ad-
dressing mode. These modes are classified into two cat-
B Pointer
05 Hex
05 Hex
Register
B or X Indirect with Post-Incrementing/
egories:
operand
addressing
modes
and
Decrementing. The relevant memory address is specified
by the contents of the B Register or X register (pointer
register). The pointer register is automatically incremented
or decremented after execution, allowing easy manipulation
of memory blocks with software loops. In assembly lan-
guage, the notation [B+], [B−], [X+], or [X−] specifies which
register serves as the pointer, and whether the pointer is to
be incremented or decremented.
transfer-of-control addressing modes. Operand address-
ing modes are the various methods of specifying an ad-
dress for accessing (reading or writing) data.
Transfer-of-control addressing modes are used in con-
junction with jump instructions to control the execution
sequence of the software program.
13.3.1 Operand Addressing Modes
Example: Exchange Memory with Accumulator, B Indirect
with Post-Increment
The operand of an instruction specifies what memory
location is to be affected by that instruction. Several dif-
ferent operand addressing modes are available, allowing
memory locations to be specified in a variety of ways. An
instruction can specify an address directly by supplying
the specific address, or indirectly by specifying a register
pointer. The contents of the register (or in some cases,
two registers) point to the desired memory location. In the
immediate mode, the data byte to be used is contained in
the instruction itself.
X A,[B+]
Reg/Data
Memory
Contents
Before
Contents
After
Accumulator
Memory Location
0005 Hex
03 Hex
62 Hex
62 Hex
03 Hex
B Pointer
05 Hex
06 Hex
Each addressing mode has its own advantages and dis-
advantages with respect to flexibility, execution speed,
and program compactness. Not all modes are available
with all instructions. The Load (LD) instruction offers the
largest number of addressing modes.
Intermediate. The data for the operation follows the instruc-
tion opcode in program memory. In assembly language, the
number sign character (#) indicates an immediate operand.
The available addressing modes are:
•
Direct
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40
The available transfer-of-control addressing modes are:
13.0 Instruction Set (Continued)
•
•
•
•
Jump Relative
Example: Load Accumulator Immediate
Jump Absolute
Jump Absolute Long
Jump Indirect
#
LD A, 05
Reg/Data
Contents
Before
Contents
After
Memory
The transfer-of-control addressing modes are described be-
low. Each description includes an example of a Jump in-
struction using a particular addressing mode, and the effect
on the Program Counter bytes of executing that instruction.
Accumulator
XX Hex
05 Hex
Immediate Short. This is a special case of an immediate
instruction. In the “Load B immediate” instruction, the 4-bit
immediate value in the instruction is loaded into the lower
nibble of the B register. The upper nibble of the B register is
reset to 0000 binary.
Jump Relative. In this 1-byte instruction, six bits of the
instruction opcode specify the distance of the jump from the
current program memory location. The distance of the jump
can range from −31 to +32. A JP+1 instruction is not allowed.
The programmer should use a NOP instead.
Example: Load B Register Immediate Short
LD B,#7
Example: Jump Relative
JP 0A
Reg/Data
Memory
B Pointer
Contents
Before
Contents
After
Reg
Contents
Before
Contents
After
12 Hex
07 Hex
Indirect from Program Memory. This is a special case of
an indirect instruction that allows access to data tables
stored in program memory. In the “Load Accumulator Indi-
rect” (LAID) instruction, the upper and lower bytes of the
Program Counter (PCU and PCL) are used temporarily as a
pointer to program memory. For purposes of accessing pro-
gram memory, the contents of the Accumulator and PCL are
exchanged. The data pointed to by the Program Counter is
loaded into the Accumulator, and simultaneously, the original
contents of PCL are restored so that the program can re-
sume normal execution.
PCU
PCL
02 Hex
05 Hex
02 Hex
0F Hex
Jump Absolute. In this 2-byte instruction, 12 bits of the
instruction opcode specify the new contents of the Program
Counter. The upper three bits of the Program Counter re-
main unchanged, restricting the new Program Counter ad-
dress to the same 4 kbyte address space as the current
instruction.
(This restriction is relevant only in devices using more than
one 4 kbyte program memory space.)
Example: Load Accumulator Indirect
LAID
Example: Jump Absolute
JMP 0125
Reg/Data
Memory
Contents
Before
04 Hex
35 Hex
1F Hex
25 Hex
Contents
After
Reg
Contents
Before
Contents
After
PCU
04 Hex
36 Hex
25 Hex
25 Hex
PCU
PCL
0C Hex
77 Hex
01 Hex
25 Hex
PCL
Accumulator
Memory Location
041F Hex
Jump Absolute Long. In this 3-byte instruction, 15 bits of
the instruction opcode specify the new contents of the Pro-
gram Counter.
Example: Jump Absolute Long
JMP 03625
13.3.2 Tranfer-of-Control Addressing Modes
Program instructions are usually executed in sequential or-
der. However, Jump instructions can be used to change the
normal execution sequence. Several transfer-of-control ad-
dressing modes are available to specify jump addresses.
Reg/
Memory
PCU
Contents
Before
Contents
After
42 Hex
36 Hex
36 Hex
25 Hex
A change in program flow requires a non-incremental
change in the Program Counter contents. The Program
Counter consists of two bytes, designated the upper byte
(PCU) and lower byte (PCL). The most significant bit of PCU
is not used, leaving 15 bits to address the program memory.
PCL
Different addressing modes are used to specify the new
address for the Program Counter. The choice of addressing
mode depends primarily on the distance of the jump. Farther
jumps sometimes require more instruction bytes in order to
completely specify the new Program Counter contents.
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Jump to Subroutine Long (JSRL)
Return from Subroutine (RET)
Return from Subroutine and Skip (RETSK)
Return from Interrupt (RETI)
13.0 Instruction Set (Continued)
Jump Indirect. In this 1-byte instruction, the lower byte of
the jump address is obtained from a table stored in program
memory, with the Accumulator serving as the low order byte
of a pointer into program memory. For purposes of access-
ing program memory, the contents of the Accumulator are
written to PCL (temporarily). The data pointed to by the
Program Counter (PCH/PCL) is loaded into PCL, while PCH
remains unchanged.
Software Trap Interrupt (INTR)
Vector Interrupt Select (VIS)
13.4.3 Load and Exchange Instructions
The load and exchange instructions write byte values in
registers or memory. The addressing mode determines the
source of the data.
Example: Jump Indirect
JID
Load (LD)
Reg/
Memory
PCU
Contents
Before
01 Hex
C4 Hex
26 Hex
Contents
After
Load Accumulator Indirect (LAID)
Exchange (X)
01 Hex
32 Hex
26 Hex
PCL
13.4.4 Logical Instructions
The logical instructions perform the operations AND, OR,
and XOR (Exclusive OR). Other logical operations can be
performed by combining these basic operations. For ex-
ample, complementing is accomplished by exclusiveORing
the Accumulator with FF Hex.
Accumulator
Memory
Location
0126 Hex
32 Hex
32 Hex
The VIS instruction is a special case of the Indirect Transfer
of Control addressing mode, where the double-byte vector
associated with the interrupt is transferred from adjacent
addresses in program memory into the Program Counter in
order to jump to the associated interrupt service routine.
Logical AND (AND)
Logical OR (OR)
Exclusive OR (XOR)
13.4.5 Accumulator Bit Manipulation Instructions
The Accumulator bit manipulation instructions allow the user
to shift the Accumulator bits and to swap its two nibbles.
13.4 INSTRUCTION TYPES
The instruction set contains a wide variety of instructions.
The available instructions are listed below, organized into
related groups.
Rotate Right Through Carry (RRC)
Rotate Left Through Carry (RLC)
Swap Nibbles of Accumulator (SWAP)
Some instructions test a condition and skip the next instruc-
tion if the condition is not true. Skipped instructions are
executed as no-operation (NOP) instructions.
13.4.6 Stack Control Instructions
Push Data onto Stack (PUSH)
Pop Data off of Stack (POP)
13.4.1 Arithmetic Instructions
The arithmetic instructions perform binary arithmetic such as
addition and subtraction, with or without the Carry bit.
13.4.7 Memory Bit Manipulation Instructions
Add (ADD)
The memory bit manipulation instructions allow the user to
set and reset individual bits in memory.
Add with Carry (ADC)
Subtract (SUB)
Set Bit (SBIT)
Subtract with Carry (SUBC)
Increment (INC)
Reset Bit (RBIT)
Reset Pending Bit (RPND)
Decrement (DEC)
Decimal Correct (DCOR)
Clear Accumulator (CLR)
Set Carry (SC)
13.4.8 Conditional Instructions
The conditional instruction test a condition. If the condition is
true, the next instruction is executed in the normal manner; if
the condition is false, the next instruction is skipped.
Reset Carry (RC)
If Equal (IFEQ)
If Not Equal (IFNE)
13.4.2 Transfer-of-Control Instructions
If Greater Than (IFGT)
If Carry (IFC)
The transfer-of-control instructions change the usual se-
quential program flow by altering the contents of the Pro-
gram Counter. The Jump to Subroutine instructions save the
Program Counter contents on the stack before jumping; the
Return instructions pop the top of the stack back into the
Program Counter.
If Not Carry (IFNC)
If Bit (IFBIT)
If B Pointer Not Equal (IFBNE)
And Skip if Zero (ANDSZ)
Decrement Register and Skip if Zero (DRSZ)
Jump Relative (JP)
Jump Absolute (JMP)
Jump Absolute Long (JMPL)
Jump Indirect (JID)
Jump to Subroutine (JSR)
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42
13.0 Instruction Set (Continued)
13.4.9 No-Operation Instruction
The no-operation instruction does nothing, except to occupy
space in the program memory and time in execution.
No-Operation (NOP)
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt
service routine.
13.5 REGISTER AND SYMBOL DEFINITION
The following abbreviations represent the nomenclature
used in the instruction description and the COP8
cross-assembler.
Registers
A
8-Bit Accumulator Register
8-Bit Address Register
B
X
8-Bit Address Register
SP
PC
PU
PL
C
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1 Bit of PSW Register for Carry
1 Bit of PSW Register for Half Carry
HC
GIE
1 Bit of PSW Register for Global Interrupt
Enable
VU
VL
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
Symbols
[B]
Memory Indirectly Addressed by B Register
Memory Indirectly Addressed by X Register
Direct Addressed Memory
[X]
MD
Mem
Meml
Direct Addressed Memory or [B]
Direct Addressed Memory or [B] or
Immediate Data
Imm
Reg
8-Bit Immediate Data
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit
←
↔
Bit Number (0 to 7)
Loaded with
Exchanged with
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13.0 Instruction Set (Continued)
13.6 INSTRUCTION SET SUMMARY
←
←
ADD
ADC
A,Meml
A,Meml
ADD
A
A
A + Meml
A + Meml + C, C Carry,
←
ADD with Carry
←
HC Half Carry
← ←
A − MemI + C, C Carry,
SUBC
A,Meml
Subtract with Carry
A
←
HC Half Carry
←
AND
ANDSZ
OR
A,Meml
A,Imm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Logical AND
A
A and Meml
Logical AND Immed., Skip if Zero
Logical OR
Skip next if (A and Imm) = 0
←
←
A
A
A or Meml
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
X
Logical EXclusive OR
IF EQual
A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
IF EQual
≠
Compare A and Meml, Do next if A Meml
IF Not Equal
>
IF Greater Than
Compare A and Meml, Do next if A Meml
≠
If B Not Equal
Do next if lower 4 bits of B Imm
←
Reg
Decrement Reg., Skip if Zero
Set BIT
Reg Reg − 1, Skip if Reg = 0
#
#
#
,Mem
,Mem
,Mem
1 to bit, Mem (bit = 0 to 7 immediate)
0 to bit, Mem
Reset BIT
#
IF BIT
If bit , A or Mem is true do next instruction
Reset PeNDing Flag
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.
EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.
CLeaR A
Reset Software Interrupt Pending Flag
↔
↔
←
←
←
A,Mem
A,[X]
A
A
A
A
B
Mem
[X]
X
LD
A,Meml
A,[X]
Meml
[X]
LD
LD
B,Imm
Imm
←
Mem Imm
LD
Mem,Imm
Reg,Imm
←
Reg Imm
LD
↔
↔
←
←
±
±
±
±
X
A, [B
A, [X
]
]
A
A
A
A
[B], (B
[X], (X
B
X
B
1)
1)
1)
←
X
←
←
±
±
LD
A, [B ]
[B], (B
←
±
±
LD
A, [X ]
[X], (X X 1)
←
←
±
±
LD
[B ],Imm
[B] Imm, (B B 1)
←
←
←
←
←
→
CLR
INC
A
A
A
A
A
A
A
A
C
C
0
INCrement A
A + 1
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
DECrement A
A − 1
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
ROM (PU,A)
A
A
A
A
BCD correction of A (follows ADC, SUBC)
→
←
→
←
→
A0 C
A7
A7
…
…
←
←
←
A0 C, HC A0
↔
A7…A4 A3…A0
←
←
←
←
C
C
1, HC
0, HC
1
0
RC
Reset C
IFC
IF C
IF C is true, do next instruction
IFNC
POP
PUSH
VIS
IF Not C
If C is not true, do next instruction
← ←
SP SP + 1, A [SP]
A
A
POP the stack into A
PUSH A onto the stack
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
←
←
[SP] A, SP SP − 1
←
←
PU [VU], PL [VL]
←
PC ii (ii = 15 bits, 0 to 32k)
JMPL
JMP
JP
Addr.
Addr.
Disp.
←
PC9…0 i (i = 12 bits)
←
PC PC + r (r is −31 to +32, except 1)
Jump relative short
www.national.com
44
13.0 Instruction Set (Continued)
← ← ←
[SP] PL, [SP−1] PU,SP−2, PC ii
JSRL
JSR
Addr.
Addr.
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
←
←
←
[SP] PL, [SP−1] PU,SP−2, PC9…0
i
←
PL ROM (PU,A)
JID
← ←
SP + 2, PL [SP], PU [SP−1]
RET
RETurn from subroutine
RETurn and SKip
←
←
RETSK
SP + 2, PL [SP],PU [SP−1],
skip next instruction
←
←
←
RETI
INTR
NOP
RETurn from Interrupt
Generate an Interrupt
No OPeration
SP + 2, PL [SP],PU [SP−1],GIE
1
←
←
←
[SP] PL, [SP−1] PU, SP−2, PC 0FF
←
PC PC + 1
13.7 INSTRUCTION EXECUTION TIME
Instructions Using A & C
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
CLRA
INCA
DECA
LAID
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
DCORA
RRCA
RLCA
SWAPA
SC
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
RC
Arithmetic and Logic Instructions
IFC
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
3/4
Immed.
2/2
IFNC
ADD
ADC
SUBC
AND
OR
PUSHA
POPA
ANDSZ
3/4
2/2
3/4
2/2
3/4
2/2
Transfer of Control Instructions
3/4
2/2
JMPL
JMP
JP
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
3/4
2/2
3/4
2/2
3/4
2/2
JSRL
JSR
1/3
3/4
3/4
3/4
JID
1/1
1/1
1/1
VIS
RET
RETSK
RETI
INTR
NOP
RPND
1/1
45
www.national.com
13.0 Instruction Set (Continued)
Memory Transfer Instructions
Register
Indirect
Direct Immed.
Register Indirect
Auto Incr. & Decr.
[B]
1/1
1/1
[X]
1/3
1/3
[B+, B−]
1/2
[X+, X−]
1/3
1/3
X A, (Note 21)
LD A, (Note 21)
LD B, Imm
2/3
2/3
2/2
1/1
2/2
1/2
2/2
<
(If B 16)
>
(If B 15)
LD B, Imm
LD Mem, Imm
LD Reg, Imm
IFEQ MD, Imm
2/2
3/3
2/3
3/3
>
Memory location addressed by B or X or directly.
Note 21:
=
www.national.com
46
N i b b l e L o w e r
47
www.national.com
development. Supports all COP8 devices. (DOS/Win16
v4.10.2 available with limited support). (Compatible with
WCOP8 IDE, COP8C, and DriveWay COP8).
14.0 Mask Options
For mask options information on COP8SAx5 devices, please
refer to Section 6.4 ECON (CONFIGURATION) REGISTER.
•
•
COP8-NSDEV: Very low cost Software Development
Package for Windows. An integrated development envi-
ronment for COP8, including WCOP8 IDE, COP8C (lim-
ited version), COP8-NSASM, COP8-MLSIM.
15.0 Development Tools Support
15.1 OVERVIEW
COP8C: Moderately priced C Cross-Compiler and Code
Development System from Byte Craft (no code limit).
Includes BCLIDE (Byte Craft Limited Integrated Develop-
ment Environment) for Win32, editor, optimizing C Cross-
Compiler, macro cross assembler, BC-Linker, and Met-
aLink tools support. (DOS/SUN versions available;
Compiler is installable under WCOP8 IDE; Compatible
with DriveWay COP8).
National is engaged with an international community of in-
dependent 3rd party vendors who provide hardware and
software development tool support. Through National’s inter-
action and guidance, these tools cooperate to form a choice
of solutions that fits each developer’s needs.
This section provides a summary of the tool and develop-
ment kits currently available. Up-to-date information, selec-
tion guides, free tools, demos, updates, and purchase infor-
mation can be obtained at our web site at:
www.national.com/cop8.
•
•
EWCOP8-KS: Very Low cost ANSI C-Compiler and Em-
bedded Workbench from IAR (Kickstart version:
COP8Sx/Fx only with 2k code limit; No FP). A fully inte-
grated Win32 IDE, ANSI C-Compiler, macro assembler,
editor, linker, Liberian, C-Spy simulator/debugger, PLUS
MetaLink EPU/DM emulator support.
15.2 SUMMARY OF TOOLS
COP8 Evaluation Tools
•
COP8–NSEVAL: Free Software Evaluation package for
Windows. A fully integrated evaluation environment for
COP8, including versions of WCOP8 IDE (Integrated
Development Environment), COP8-NSASM, COP8-
EWCOP8-AS: Moderately priced COP8 Assembler and
Embedded Workbench from IAR (no code limit). A fully
integrated Win32 IDE, macro assembler, editor, linker,
librarian, and C-Spy high-level simulator/debugger with
I/O and interrupts support. (Upgradeable with optional
C-Compiler and/or MetaLink Debugger/Emulator sup-
port).
™
MLSIM, COP8C, DriveWay COP8, Manuals, and other
COP8 information.
•
•
COP8–MLSIM: Free Instruction Level Simulator tool for
Windows. For testing and debugging software instruc-
tions only (No I/O or interrupt support).
•
EWCOP8-BL: Moderately priced ANSI C-Compiler and
Embedded Workbench from IAR (Baseline version: All
COP8 devices; 4k code limit; no FP). A fully integrated
Win32 IDE, ANSI C-Compiler, macro assembler, editor,
linker, librarian, and C-Spy high-level simulator/debugger.
(Upgradeable; CWCOP8-M MetaLink tools interface sup-
port optional).
COP8–EPU: Very Low cost COP8 Evaluation & Pro-
gramming Unit. Windows based evaluation and
hardware-simulation tool, with COP8 device programmer
and erasable samples. Includes COP8-NSDEV, Drive-
way COP8 Demo, MetaLink Debugger, I/O cables and
power supply.
•
•
EWCOP8: Full featured ANSI C-Compiler and Embed-
ded Workbench for Windows from IAR (no code limit). A
fully integrated Win32 IDE, ANSI C-Compiler, macro as-
sembler, editor, linker, librarian, and C-Spy high-level
simulator/debugger. (CWCOP8-M MetaLink tools inter-
face support optional).
•
•
COP8–EVAL-HIxx: Low cost target application evalua-
tion and development board for COP8Sx Families, from
Hilton Inc. Real-time environment with integrated A/D,
Temp Sensor, and Peripheral I/O.
COP8–EVAL-ICUxx: Very Low cost evaluation and de-
sign test board for COP8ACC and COP8SGx Families,
from ICU. Real-time environment with add-on A/D, D/A,
and EEPROM. Includes software routines and reference
designs.
EWCOP8-M: Full featured ANSI C-Compiler and Embed-
ded Workbench for Windows from IAR (no code limit). A
fully integrated Win32 IDE, ANSI C-Compiler, macro as-
sembler, editor, linker, librarian, C-Spy high-level
simulator/debugger, PLUS MetaLink debugger/hardware
interface (CWCOP8-M).
•
Manuals, Applications Notes, Literature: Available free
from our web site at: www.national.com/cop8.
COP8 Productivity Enhancement Tools
COP8 Integrated Software/Hardware Design Develop-
ment Kits
•
WCOP8 IDE: Very Low cost IDE (Integrated Develop-
ment Environment) from KKD. Supports COP8C, COP8-
NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink
debugger under a common Windows Project Manage-
ment environment. Code development, debug, and emu-
lation tools can be launched from the project window
framework.
•
COP8-EPU: Very Low cost Evaluation & Programming
Unit. Windows based development and hardware-
simulation tool for COPSx/xG families, with COP8 device
programmer and samples. Includes COP8-NSDEV,
Driveway COP8 Demo, MetaLink Debugger, cables and
power supply.
•
DriveWay-COP8: Low cost COP8 Peripherals Code
Generation tool from Aisys Corporation. Automatically
generates tested and documented C or Assembly source
code modules containing I/O drivers and interrupt han-
dlers for each on-chip peripheral. Application specific
code can be inserted for customization using the inte-
grated editor. (Compatible with COP8-NSASM, COP8C,
and WCOP8 IDE.)
•
COP8-DM: Moderate cost Debug Module from MetaLink.
A Windows based, real-time in-circuit emulation tool with
COP8 device programmer. Includes COP8-NSDEV,
DriveWay COP8 Demo, MetaLink Debugger, power sup-
ply, emulation cables and adapters.
COP8 Development Languages and Environments
•
COP8-NSASM: Free COP8 Assembler v5 for Win32.
Macro assembler, linker, and librarian for COP8 software
www.national.com
48
•
IM-COP8: MetaLink iceMASTER®. A full featured, real-
time in-circuit emulator for COP8 devices. Includes
COP8-NSDEV, Driveway COP8 Demo, MetaLink Win-
dows Debugger, and power supply. Package-specific
probes and surface mount adaptors are ordered sepa-
rately.
15.0 Development Tools Support
(Continued)
•
•
COP8-UTILS: Free set of COP8 assembly code ex-
amples, device drivers, and utilities to speed up code
development.
COP8 Device Programmer Support
COP8-MLSIM: Free Instruction Level Simulator tool for
Windows. For testing and debugging software instruc-
tions only (No I/O or interrupt support).
•
MetaLink’s EPU and Debug Module include development
device programming capability for COP8 devices.
COP8 Real-Time Emulation Tools
•
Third-party programmers and automatic handling equip-
ment cover needs from engineering prototype and pilot
production, to full production environments.
•
COP8-DM: MetaLink Debug Module.
A moderately
priced real-time in-circuit emulation tool, with COP8 de-
vice programmer. Includes MetaLink Debugger, power
supply, emulation cables and adapters.
•
Factory programming available for high-volume require-
ments.
15.3 TOOLS ORDERING NUMBERS FOR THE COP8SAx FAMILY DEVICES
Note: The following order numbers apply to the COP8 devices in this datasheet only.
Vendor
Tools
COP8-NSEVAL
COP8-NSDEV
COP8-REF
Order Number
COP8-NSEVAL
Cost
VL
L
Notes
Order from web site.
COP8-NSDEV
None
Included in EM. Order CD from web site
COP8-EVAL
COP8-EM
COP8-EVAL-COB1
COP8-EM-SA
VL
M
Order from web site
Included p/s, 20/28/40 pin DIP target cable, manuals,
software
EM Target
Cables and
Adapters
COP8-EMC-44P
COP8-EMC-28CSP
COP8-EMA-16D
COP8-EMA-xxSO
COP8-EMA-44QFP
COP8SAC7Q
VL
L
44 PLCC Target Cable
28 CSP Target Cable
L
20 DIP to 16 DIP Adapter
DIP to SOIC Cable Converter
44 pin PLCC to 44 QFP Cable Converter
4k Eraseable/OTP devices
L
L
Development
Devices
VL
COP8-PM
COP8-PM-00
L
Included p/s, manuals, software, 16/20/28/40 DIP/SO
and 44 PLCC programming socket; add OTP adapter
(if needed)
OTP
Programming
Adapters
COP8-PGMA-44QFP
COP8-PGMA-28CSP
COP8-PGMA-44CSP
COP8-PGMA-28SO
L
For programming 44 QFP on any programmer
For programming 28 CSP on any programmer
For programming 44 CSP on any programmer
For programming 16/20/28 SOIC on any programmer
L
L
VL
49
www.national.com
15.0 Development Tools Support (Continued)
MetaLink COP8-DM
DM5-KCOP8-SA
M
Included p/s (PS-10), target cables (DIP and PLCC),
16/20/28/40 DIP/SO and 44 PLCC programming
sockets. Add OTP adapter (if needed) and target
adapter (if needed)
DM Target
Adapters
MHW-CNVxx (xx = 33, 34
etc.)
L
L
DM target converters for
16DIP/20SO/28SO/44QFP/28CSP; (i.e. MHW-CNV38
for 20 pin DIP to SO package converter)
OTP
Programming
Adapters
MHW-COP8-PGMA-DS
For programming 16/20/28 SOIC and 44 PLCC on the
EPU
MHW-COP8-PGMA-44QFP
MHW-COP8-PGMA-28CSP
L
L
For programming 44 QFP on any programmer
For programming 28 CSP on any programmer
COP8-IM
IM-COP8-AD-464 (-220)
(10 MHz maximum)
H
Base unit 10 MHz; -220 = 220V; add probe card
(required) and target adapter (if needed); included
software and manuals
IM Probe Card
PC-COP8SA44PW-AD-10
PC-COP8SA40DW-AD-10
M
M
L
10 MHz 44 PLCC probe card; 2.5V to 6.0V
10 MHz 40 DIP probe card; 2.5V to 6.0V
16 or 20 or 28 pin SOIC adapter for probe card
IM Probe Target
Adapters
MHW-SOICxx (xx = 16,
20, 28)
MHW-CONV33
L
44 pin QFP adapter for 44 PLCC probe card
Included in DM and EM
KKD
IAR
WCOP8-IDE
EWCOP8-xx
COP8C
WCOP8-IDE
VL
See summary above
COP8C COP8CWIN
L - H Included all software and manuals
Byte
Craft
M
Included all software and manuals
Aisys
DriveWay COP8
DriveWay COP8
L
Included all software and manuals
Go to:
www.national.com/cop8
L - H A wide variety world-wide
OTP Programmers
<
Cost: Free; VL = $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k
www.national.com
50
15.0 Development Tools Support (Continued)
15.4 WHERE TO GET TOOLS
Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.
Vendor
Home Office
U.S.A.: Santa Clara, CA
1-408-327-8820
Electronic Sites
Other Main Offices
Distributors
Aisys
www.aisysinc.com
@
info aisysinc.com
fax: 1-408-327-8830
U.S.A.
Byte Craft
IAR
www.bytecraft.com
Distributors
@
1-519-888-6911
info bytecraft.com
fax: 1-519-746-6751
Sweden: Uppsala
+46 18 16 78 00
fax: +46 18 16 78 38
www.iar.se
U.S.A.: San Francisco
1-415-765-5500
@
info iar.se
@
info iar.com
fax: 1-415-765-5503
U.K.: London
@
info iarsys.co.uk
@
info iar.de
+44 171 924 33 34
fax: +44 171 924 53 41
Germany: Munich
+49 89 470 6022
fax: +49 89 470 956
Switzeland: Hoehe
+41 34 497 28 20
fax: +41 34 497 28 21
ICU
Sweden: Polygonvaegen
+46 8 630 11 20
www.icu.se
@
support icu.se
@
fax: +46 8 630 11 70
Denmark:
support icu.ch
KKD
www.kkd.dk
MetaLink
U.S.A.: Chandler, AZ
1-800-638-2423
www.metaice.com
Germany: Kirchseeon
80-91-5696-0
@
sales metaice.com
@
fax: 1-602-926-1198
support metaice.com
fax: 80-91-2386
@
bbs: 1-602-962-0013
www.metalink.de
islanger metalink.de
Distributors Worldwide
National
U.S.A.: Santa Clara, CA
1-800-272-9959
www.national.com/cop8
Europe: +49 (0) 180 530 8585
fax: +49 (0) 180 530 8586
Distributors Worldwide
@
support nsc.com
@
fax: 1-800-737-7018
europe.support nsc.com
The following companies have approved COP8 program-
mers in a variety of configurations. Contact your local office
or distributor. You can link to their web sites and get the
latest listing of approved programmers from National’s
COP8 OTP Support page at: www.national.com/cop8.
15.5 CUSTOMER SUPPORT
Complete product information and technical support is avail-
able from National’s customer response centers, and from
our on-line COP8 customer support sites.
Advantech; Dataman; EE Tools; Minato; BP Microsystems;
Data I/O; Hi-Lo Systems; ICE Technology; Lloyd Research;
Logical Devices; MQP; Needhams; Phyton; SMS; Stag Pro-
grammers; System General; Tribal Microsystems; Xeltek.
51
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Hermetic Dual-In-Line Package, EPROM (D)
Order Number COP8SAC720Q3
NS Package Number D20CQ
www.national.com
52
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Small Outline Package (WM)
Order Number COP8SAA716M8 or COP8SAA716M9
NS Package Number M16B
Molded Dual-In-Line Package (N)
Order Number COP8SAA716N8 or COP8SAA716N9
NS Package Number N16A
53
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded SO Wide Body Package (WM)
Order Number COP8SAA720M9, COP8SAB720M9, COP8SAC720M9
COP8SAA720M8, COP8SAB720M8 or COP8SAC720M8
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number COP8SAA720N9, COP8SAB720N9, COP8SAC720N9,
COP8SAA720N8, COP8SAB720N8 or COP8SAC720N8
NS Package Number N20A
www.national.com
54
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Hermetic Dual-In-Line Package EPROM (D)
Order Number COP8SAC728Q3
NS Package Number D28JQ
55
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded SO Wide Body Package (WM)
Order Number COP8SAA728M9, COP8SAB728M9, COP8SAC728M9,
COP8SAA728M8, COP8SAB728M8 or COP8SAC728M8
NS Package Number M28B
Molded Dual-In-Line Package (N),
Order Number COP8SAA728N9, COP8SAB728N9, COP8SAC728N9,
COP8SAA728N8, COP8SAB728N8 or COP8SAC728N8
NS Package Number N28B
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56
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28 Lead Chip Scale Package (SLB)
Order Number COP8SAA7SLB9, COP8SAB7SLB9 or COP8SAC7SLB9
NS Package Number SLB28A
57
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
40-Lead Hermetic DIP EPROM (D)
Order Number COP8SAC740Q3
NS Package Number D40KQ
Molded Dual-In-Line Package (N)
Order Number COP8SAC740N9 or COP8SAC740N8
NS Package Number N40A
www.national.com
58
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
44-Lead EPROM Leaded Chip Carrier (EL)
Order Number COP8SAC744Q3
NS Package Number EL44C
59
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number COP8SAC744V9 or COP8SAC744V8
NS Package Number V44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 180-530 85 86
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Products > Microcontrollers > 8-Bit COP8 Family > OTPs > COP8SAA7
COP8SAA7 Product Folder
8-Bit CMOS OTP Microcontroller with 1k Memory, 64 RAM, Power On Reset (POR), and Very
Small Packaging
Generic P/N 8SAA7
General
Description
Package
& Models
Samples
& Pricing
Design
Tools
Application
Notes
Datasheet
WEBENCH Live Simulation!
Parametric Table
COP8SAA7 Webench™ Custom
Design/Analyze/Build It
Code Memory
1 K
OTP
64
Memory Technology
RAM
Simulate this
I/O Pins
16/24
yes/yes
Yes
Halt/Idle
MIWU
16 Bit Timer
TO Timer
1
Yes
Voltage Range
Interrupts
2.7 to 5.5V
8
Power on Reset
Watchdog/Clock Monitor
A/D Converter
Microwire Plus
USART Interface
CAN
Yes
Yes/Yes
n/a
Yes
No
No
Comparators
Temp Sensor
n/a
No
-
Datasheet
Title
Size in Kbytes Date
Receive via
Email
Download
View Online
COP8SA Family 8-Bit CMOS ROM
Based and One-Time
Programmable (OTP)
View Online Download Receive via Email
30-Nov-00
Microcontroller with 1k to 4k
Memory[comma] Power On
Reset[comma] and Very Small
Packaging
776 Kbytes
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Package Availability, Models, Samples & Pricing
Budgetary
Pricing
Package
Type Pins MSL
Models
Samples &
Electronic
Orders
Std
Pack
Size
Package
Marking
Part Number
Status
$US
SPICE IBIS
Qty
each
rail
of
45
[logo]¢U¢Z¢2¢T
COP8SAA7
16M7
SOIC
WIDE
Samples
MSL
MSL
COP8SAA716M7
COP8SAA716M8
16
16
Production
N/A
N/A
N/A
N/A
1K+ $0.8000
Samples
rail [logo]¢U¢Z¢2¢T¢P
of
45
SOIC
WIDE
Full
production
1K+ $0.7600
COP8SAA7
16M8
Buy Now
Samples
rail [logo]¢U¢Z¢2¢T¢P
SOIC
WIDE
Full
production
MSL
MSL
MSL
COP8SAA716M9
COP8SAA720M7
COP8SAA720M8
16
20
20
N/A
N/A
N/A
N/A
N/A
N/A
1K+ $0.7500
1K+ $0.9300
1K+ $0.9000
of
45
COP8SAA7
16M9
Buy Now
rail
of
36
[logo]¢U¢Z¢2¢T
COP8SAA7
20M7
SOIC
WIDE
Samples
Production
Production
Samples
rail
of
36
[logo]¢U¢Z¢2¢T
COP8SAA7
20M8
SOIC
WIDE
Buy Now
Samples
rail [logo]¢U¢Z¢2¢T¢P
SOIC
WIDE
Full
production
MSL
MSL
COP8SAA720M9
COP8SAA728M8
20
28
N/A
N/A
N/A
N/A
1K+ $0.8700
1K+ $1.2300
of
36
COP8SAA7
20M9
Buy Now
Samples
rail
of
26
SOIC
WIDE
Full
production
[logo]¢U¢Z¢2¢T¢P
COP8SAA728M8
Buy Now
Samples
rail
of
26
SOIC
WIDE
Full
production
[logo]¢U¢Z¢2¢T¢P
COP8SAA728M9
MSL
MSL
MSL
COP8SAA728M9
COP8SAA716N7
COP8SAA716N8
28
16
16
N/A
N/A
N/A
N/A
N/A
N/A
1K+ $1.2100
1K+ $0.8000
1K+ $0.7600
Buy Now
rail
of
25
[logo]¢U¢Z¢3¢T¢P
COP8SAA716N7
Samples
MDIP
MDIP
Production
Samples
rail
of
25
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAA716N8
Buy Now
Samples
rail
of
25
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAA716N9
MDIP
MDIP
MSL
MSL
COP8SAA716N9
COP8SAA720N7
16
20
N/A
N/A
N/A
N/A
1K+ $0.7500
1K+ $0.9300
Buy Now
rail
of
18
[logo]¢U¢Z¢3¢T¢P
COP8SAA720N7
Samples
Production
Samples
rail
of
18
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAA720N8
MDIP
MDIP
MDIP
MSL
MSL
MSL
COP8SAA720N8
COP8SAA720N9
COP8SAA728N8
20
20
28
N/A
N/A
N/A
N/A
N/A
N/A
1K+ $0.9100
1K+ $0.8700
1K+ $1.2500
Buy Now
rail
of
18
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAA720N9
Samples
Samples
rail
of
13
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAA728N8
Buy Now
Samples
rail
of
13
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAA728N9
MDIP
MSL
COP8SAA728N9
28
N/A
N/A
1K+ $1.2500
Buy Now
reel
of
2500
[logo]¢U¢Z¢2¢T
COP8SAA7
SLB8
Laminate
CSP
Full
production
Samples
Samples
MSL
MSL
COP8SAA7SLB8
COP8SAA7SLB9
28
28
N/A
N/A
N/A
N/A
1K+ $2.1500
1K+ $2.1000
reel
of
2500
[logo]¢U¢Z¢2¢P
COP8SAA7
SLB9
Laminate
CSP
Full
production
General Description
Note: COP8SAx devices are instruction set and pin compatible supersets of the COP800 Family
devices, and are replacements for these in new designs when possible.
The COPSAx Rom based and OTP microcontrollers are highly integrated COP8™ feature core devices, with 1k
to 4k memory and advanced features including low EMI. These single-chip CMOS devices are suited for low
cost applications requiring a full featured controller, low EMI, and POR. 100% form-fit-function compatible
OTP versions are available with 1k, 2k, and 4k memory, and in a variety of packages including 28-pin CSP.
Erasable windowed versions are available for use with a range of COP8 software and hardware development
tools.
Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1 µs instruction cycle, one
multi-function 16-bit timer/counter with PWM output, MICROWIRE/PLUS™ serial I/O, two power saving
HALT/IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12 high current outputs, user selectable options
(WATCHDOG™, 4 clock/oscillator modes, power-on-reset), low EMI 2.7V to 5.5V operation, and
16/20/28/40/44 pin packages.
Devices included in this datasheet are:
Memory
(bytes)
Device
RAM (bytes) I/O Pins
Packages
Temperature
16/20/28
DIP/SOIC, 28
CSP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAA5
COP8SAB5
COP8SAC5
1k ROM
64
12/16/24
16/24
20/28 DIP/SOIC, 0 to +70°C, -40 to
28 CSP
2k ROM
4k ROM
128
128
+85°C, -40 to +125°C
20/28 DIP/SOIC,
16/24/36/40 28 CSP, 40 DIP,
44 PLCC/QFP
0 to +70°C, -40 to
+85°C, -40 to +125°C
16/20/28
DIP/SOIC, 28
CSP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAA7
1k OTP EPROM 64
12/16/24
20/28 DIP/SOIC, 0 to +70°C, -40 to
COP8SAB7
COP8SAC7
2k OTP EPROM 128
4k OTP EPROM 128
16/24
16/24
28 CSP
+85°C, -40 to +125°C
20/28 DIP/SOIC,
28 CSP, 40 DIP,
44 PLCC/QFP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAC7-Q3 4k EPROM
COP8SAC7-J3 4k EPROM
128
128
16/24/36
40
20/28/40 DIP
44 PLCC
Room Temp. Only
Room Temp. Only
Design Tools
Title
Size in Kbytes Date
Receive via Email
Download
View Online
Tools for Evaluation, Design,
and Programming
28-Nov-
2001
View Online Download Receive via Email
36 Kbytes
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Application Notes
Size in
Kbytes
Title
Date
Receive via
Email
Download
View Online
AN-1098: Application Note 1098
Loading PLL Frequency Synthesizers 102 Kbytes
with COP8SAx7
Receive via
Email
View Online Download
View Online Download
View Online Download
26-Jan-99
4-Oct-96
4-Oct-96
AN-1043: Comparison of COP878x
to the Enhanced COP8SAx7 Family - 79 Kbytes
Hardware/Software Considerations
Receive via
Email
AN-1044: Comparison of COP82xCJ
to the Enhanced COP8SAx7 Family - 81 Kbytes
Hardware/Software Considerations
Receive via
Email
If you have trouble printing or viewing PDF file(s), see Printing Problems.
[Information as of 5-Aug-2002]
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Products
COP8SAA5 Product Folder
8-Bit CMOS ROM Microcontroller with 1k Memory, 64 RAM, Power On Reset (POR), and
Very Small Packaging
Generic P/N 8SAA5
General
Description
Package
& Models
Samples
& Pricing
Design
Tools
Datasheet
WEBENCH Live Simulation!
COP8SAA5 Webench™ Custom
Design/Analyze/Build It
Simulate this
Datasheet
Title
Size in Kbytes Date
Receive via
Email
Download
View Online
COP8SA Family 8-Bit CMOS ROM
Based and One-Time
Programmable (OTP)
View Online Download Receive via Email
30-Nov-00
Microcontroller with 1k to 4k
Memory[comma] Power On
Reset[comma] and Very Small
Packaging
776 Kbytes
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Package Availability, Models, Samples & Pricing
Budgetary
Pricing
Samples
&
Electronic
Orders
Package
Models
Std
Pack
Size
Package
Marking
Part Number
Status
$US
Qty
Type Pins MSL
SPICE IBIS
each
rail [logo]¢U¢Z¢2¢T¢P
SOIC
WIDE
MSL
MSL
MSL
COP8SAA516M7XXX
COP8SAA516M8XXX
COP8SAA516M9XXX
16
16
16
Production N/A
Production N/A
Production N/A
N/A
N/A
N/A
of
N/A
COP8SAA5
16M7XXX
[logo]¢U¢Z¢2¢T
COP8SAA5
SOIC
WIDE
10000+ $0.7400
10000+ $0.7300
1
1
16M8XXX
[logo]¢U¢Z¢2¢T
COP8SAA5
SOIC
WIDE
16M9XXX
[logo]¢U¢Z¢2¢T
COP8SAA5
SOIC
WIDE
MSL
MSL
MSL
MSL
MSL
MSL
COP8SAA520M8XXX
COP8SAA520M9XXX
COP8SAA528M8XXX
COP8SAA528M9XXX
COP8SAA516N8XXX
COP8SAA516N9XXX
20
20
28
28
16
16
Production N/A
Production N/A
Production N/A
Production N/A
Production N/A
Production N/A
N/A
N/A
N/A
N/A
N/A
N/A
10000+ $0.8500
10000+ $0.8300
10000+ $1.2000
10000+ $1.1800
10000+ $0.7400
10000+ $0.7300
1
1
1
1
1
1
20M8XXX
[logo]¢U¢Z¢2¢T
COP8SAA5
SOIC
WIDE
20M9XXX
[logo]¢U¢Z¢2¢T
COP8SAA5
SOIC
WIDE
28M8XXX
[logo]¢U¢Z¢2¢T
COP8SAA5
SOIC
WIDE
28M9XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAA5
MDIP
MDIP
16N8XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAA5
16N9XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAA520N8XXX
MDIP
MDIP
MSL
MSL
COP8SAA520N8XXX
COP8SAA520N9XXX
20
20
Production N/A
Production N/A
N/A
N/A
10000+ $0.8500
10000+ $0.8200
1
1
[logo]¢U¢Z¢3¢T¢P
COP8SAA520N9XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAA5
MDIP
MDIP
MSL
MSL
MSL
MSL
COP8SAA528N8XXX
COP8SAA528N9XXX
COP8SAA5SLB8XXX
COP8SAA5SLB9XXX
28
28
28
28
Production N/A
Production N/A
Production N/A
Production N/A
N/A
N/A
N/A
N/A
10000+ $1.2200
10000+ $1.2000
1
1
28N8XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAA5
28N9XXX
reel
of
N/A
[logo]¢U¢Z¢2¢T
COP8SAA5
Laminate
CSP
SLB8XXX
reel
of
N/A
[logo]¢U¢Z¢2¢P
COP8SAA5
Laminate
CSP
SLB9XXX
General Description
Note: COP8SAx devices are instruction set and pin compatible supersets of the COP800 Family
devices, and are replacements for these in new designs when possible.
The COPSAx Rom based and OTP microcontrollers are highly integrated COP8™ feature core devices, with 1k
to 4k memory and advanced features including low EMI. These single-chip CMOS devices are suited for low
cost applications requiring a full featured controller, low EMI, and POR. 100% form-fit-function compatible
OTP versions are available with 1k, 2k, and 4k memory, and in a variety of packages including 28-pin CSP.
Erasable windowed versions are available for use with a range of COP8 software and hardware development
tools.
Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1 µs instruction cycle, one
multi-function 16-bit timer/counter with PWM output, MICROWIRE/PLUS™ serial I/O, two power saving
HALT/IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12 high current outputs, user selectable options
(WATCHDOG™, 4 clock/oscillator modes, power-on-reset), low EMI 2.7V to 5.5V operation, and
16/20/28/40/44 pin packages.
Devices included in this datasheet are:
Memory
(bytes)
Device
RAM (bytes) I/O Pins
Packages
Temperature
16/20/28
DIP/SOIC, 28
CSP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAA5
COP8SAB5
COP8SAC5
1k ROM
2k ROM
4k ROM
64
12/16/24
16/24
20/28 DIP/SOIC, 0 to +70°C, -40 to
28 CSP
128
128
+85°C, -40 to +125°C
20/28 DIP/SOIC,
16/24/36/40 28 CSP, 40 DIP,
44 PLCC/QFP
0 to +70°C, -40 to
+85°C, -40 to +125°C
16/20/28
DIP/SOIC, 28
CSP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAA7
COP8SAB7
COP8SAC7
1k OTP EPROM 64
2k OTP EPROM 128
4k OTP EPROM 128
12/16/24
16/24
20/28 DIP/SOIC, 0 to +70°C, -40 to
28 CSP
+85°C, -40 to +125°C
20/28 DIP/SOIC,
28 CSP, 40 DIP,
44 PLCC/QFP
0 to +70°C, -40 to
+85°C, -40 to +125°C
16/24
COP8SAC7-Q3 4k EPROM
COP8SAC7-J3 4k EPROM
128
128
16/24/36
40
20/28/40 DIP
44 PLCC
Room Temp. Only
Room Temp. Only
Design Tools
Title
Size in Kbytes Date
Receive via Email
Download
View Online
Tools for Evaluation, Design,
and Programming
28-Nov-
2001
View Online Download Receive via Email
36 Kbytes
If you have trouble printing or viewing PDF file(s), see Printing Problems.
[Information as of 5-Aug-2002]
Search
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Feedback
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Products
Products > Microcontrollers > 8-Bit COP8 Family > OTPs > COP8SAB7
COP8SAB7 Product Folder
8-Bit CMOS OTP Microcontroller with 2k Memory, 128 RAM, Power On Reset (POR), and
Very Small Packaging
Generic P/N 8SAB7
General
Description
Package
& Models
Samples
& Pricing
Design
Tools
Application
Notes
Datasheet
WEBENCH Live Simulation!
Parametric Table
COP8SAB7 Webench™ Custom
Design/Analyze/Build It
Code Memory
2 K
Memory Technology
RAM
OTP
128
Simulate this
I/O Pins
16/24
yes/yes
Yes
Halt/Idle
MIWU
16 Bit Timer
TO Timer
1
Yes
Voltage Range
Interrupts
2.7 to 5.5V
8
Power on Reset
Watchdog/Clock Monitor
A/D Converter
Microwire Plus
USART Interface
CAN
Yes
Yes/Yes
n/a
Yes
No
No
Comparators
Temp Sensor
n/a
No
-
Datasheet
Title
Size in Kbytes Date
Receive via
Email
Download
View Online
COP8SA Family 8-Bit CMOS ROM
Based and One-Time
Programmable (OTP)
View Online Download Receive via Email
30-Nov-00
Microcontroller with 1k to 4k
Memory[comma] Power On
Reset[comma] and Very Small
Packaging
776 Kbytes
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Package Availability, Models, Samples & Pricing
Budgetary
Pricing
Package
Type Pins MSL
Models
Samples &
Electronic
Orders
Std
Pack
Size
Package
Marking
Part Number
Status
$US
SPICE IBIS
Qty
each
rail
of
N/A
SOIC
WIDE
[logo]¢U¢Z¢2¢T¢P
COP8SAB720M7
Samples
MSL
MSL
COP8SAB720M7
COP8SAB720M8
20
20
Production
N/A
N/A
N/A
N/A
Samples
rail
of
36
SOIC
WIDE
Full
production
[logo]¢U¢Z¢2¢T¢P
COP8SAB720M8
1K+ $1.3000
1K+ $1.2800
Buy Now
Samples
rail
of
36
SOIC
WIDE
Full
production
[logo]¢U¢Z¢2¢T¢P
COP8SAB720M9
MSL
MSL
MSL
COP8SAB720M9
COP8SAB728M7
COP8SAB728M8
20
28
28
N/A
N/A
N/A
N/A
N/A
N/A
Buy Now
rail
of
N/A
SOIC
WIDE
[logo]¢U¢Z¢2¢T¢P
COP8SAB728M7
Samples
Production
Samples
rail
of
26
SOIC
WIDE
Full
production
[logo]¢U¢Z¢2¢T¢P
COP8SAB728M8
1K+ $1.4300
1K+ $1.4500
Buy Now
Samples
rail
of
26
SOIC
WIDE
Full
production
[logo]¢U¢Z¢2¢T¢P
COP8SAB728M9
MSL
MSL
MSL
COP8SAB728M9
COP8SAB720N7
COP8SAB720N8
28
20
20
N/A
N/A
N/A
N/A
N/A
N/A
Buy Now
rail
of
N/A
[logo]¢U¢Z¢3¢T¢P
COP8SAB720N7
Samples
MDIP
MDIP
Production
Samples
rail
of
18
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAB720N8
1K+ $1.3000
1K+ $1.2800
Buy Now
Samples
rail
of
18
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAB720N9
MDIP
MDIP
MDIP
MSL
MSL
MSL
COP8SAB720N9
COP8SAB728N7
COP8SAB728N8
20
28
28
N/A
N/A
N/A
N/A
N/A
N/A
Buy Now
rail
of
N/A
[logo]¢U¢Z¢3¢T¢P
COP8SAB728N7
Samples
Production
Samples
rail
of
13
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAB728N8
1K+ $1.5000
Buy Now
Samples
rail
of
13
Full
production
[logo]¢U¢Z¢3¢T¢P
COP8SAB728N9
MDIP
MSL
MSL
COP8SAB728N9
COP8SAB7SLB8
28
28
N/A
N/A
N/A
N/A
1K+ $1.4500
1K+ $2.2500
Buy Now
reel
of
2500
[logo]¢U¢Z¢2¢T
COP8SAB7
SLB8
Laminate
CSP
Full
production
Samples
reel
of
2500
[logo]¢U¢Z¢2¢P
COP8SAB7
SLB9
Laminate
CSP
Full
production
Samples
MSL
COP8SAB7SLB9
28
N/A
N/A
1K+ $2.2000
General Description
Note: COP8SAx devices are instruction set and pin compatible supersets of the COP800 Family
devices, and are replacements for these in new designs when possible.
The COPSAx Rom based and OTP microcontrollers are highly integrated COP8™ feature core devices, with 1k
to 4k memory and advanced features including low EMI. These single-chip CMOS devices are suited for low
cost applications requiring a full featured controller, low EMI, and POR. 100% form-fit-function compatible
OTP versions are available with 1k, 2k, and 4k memory, and in a variety of packages including 28-pin CSP.
Erasable windowed versions are available for use with a range of COP8 software and hardware development
tools.
Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1 µs instruction cycle, one
multi-function 16-bit timer/counter with PWM output, MICROWIRE/PLUS™ serial I/O, two power saving
HALT/IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12 high current outputs, user selectable options
(WATCHDOG™, 4 clock/oscillator modes, power-on-reset), low EMI 2.7V to 5.5V operation, and
16/20/28/40/44 pin packages.
Devices included in this datasheet are:
Memory
(bytes)
Device
RAM (bytes) I/O Pins
Packages
Temperature
16/20/28
DIP/SOIC, 28
CSP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAA5
COP8SAB5
COP8SAC5
1k ROM
64
12/16/24
16/24
20/28 DIP/SOIC, 0 to +70°C, -40 to
28 CSP
2k ROM
4k ROM
128
128
+85°C, -40 to +125°C
20/28 DIP/SOIC,
16/24/36/40 28 CSP, 40 DIP,
44 PLCC/QFP
0 to +70°C, -40 to
+85°C, -40 to +125°C
16/20/28
DIP/SOIC, 28
CSP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAA7
COP8SAB7
COP8SAC7
1k OTP EPROM 64
2k OTP EPROM 128
4k OTP EPROM 128
12/16/24
16/24
20/28 DIP/SOIC, 0 to +70°C, -40 to
28 CSP
+85°C, -40 to +125°C
20/28 DIP/SOIC,
28 CSP, 40 DIP,
44 PLCC/QFP
0 to +70°C, -40 to
+85°C, -40 to +125°C
16/24
COP8SAC7-Q3 4k EPROM
COP8SAC7-J3 4k EPROM
128
128
16/24/36
40
20/28/40 DIP
44 PLCC
Room Temp. Only
Room Temp. Only
Design Tools
Title
Size in Kbytes Date
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Tools for Evaluation, Design,
and Programming
28-Nov-
2001
View Online Download Receive via Email
36 Kbytes
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Application Notes
Size in
Kbytes
Title
Date
Receive via
Email
Download
View Online
AN-1043: Comparison of COP878x
to the Enhanced COP8SAx7 Family - 79 Kbytes
Hardware/Software Considerations
View Online Download Receive via Email
View Online Download Receive via Email
4-Oct-96
4-Oct-96
AN-1044: Comparison of COP82xCJ
to the Enhanced COP8SAx7 Family - 81 Kbytes
Hardware/Software Considerations
If you have trouble printing or viewing PDF file(s), see Printing Problems.
[Information as of 5-Aug-2002]
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See Audio Products
COP8SAC5 Product Folder
8-Bit CMOS ROM Microcontroller with 4k Memory, 128 RAM, Power On Reset (POR), and
Very Small Packaging
Generic P/N 8SAC5
General
Description
Package
& Models
Samples
& Pricing
Design
Tools
Datasheet
Datasheet
Title
Size in Kbytes Date
Receive via
Email
Download
View Online
COP8SA Family 8-Bit CMOS ROM
Based and One-Time
Programmable (OTP)
View Online Download Receive via Email
30-Nov-00
Microcontroller with 1k to 4k
Memory[comma] Power On
Reset[comma] and Very Small
Packaging
776 Kbytes
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Package Availability, Models, Samples & Pricing
Budgetary
Pricing
Samples
&
Electronic
Orders
Package
Models
Std
Pack
Size
Package
Marking
Part Number
Status
$US
Qty
Type Pins MSL
SPICE IBIS
each
rail [logo]¢U¢Z¢2¢T¢P
SOIC
WIDE
MSL
MSL
MSL
MSL
MSL
COP8SAC520M7XXX
COP8SAC520M8XXX
COP8SAC520M9XXX
COP8SAC528M8XXX
COP8SAC528M9XXX
20
20
20
28
28
Production N/A
Production N/A
Production N/A
Production N/A
Production N/A
N/A
N/A
N/A
N/A
N/A
of
N/A
COP8SAC5
20M7XXX
[logo]¢U¢Z¢2¢T
COP8SAC5
SOIC
WIDE
10000+ $1.4000
10000+ $1.3800
10000+ $1.5500
10000+ $1.5300
1
1
1
1
20M8XXX
[logo]¢U¢Z¢2¢T
COP8SAC5
SOIC
WIDE
20M9XXX
[logo]¢U¢Z¢2¢T
COP8SAC5
SOIC
WIDE
28M8XXX
[logo]¢U¢Z¢2¢T
COP8SAC5
SOIC
WIDE
28M9XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAC520N8XXX
MDIP
MDIP
MSL
MSL
COP8SAC520N8XXX
COP8SAC520N9XXX
20
20
Production N/A
Production N/A
N/A
N/A
10000+ $1.4000
10000+ $1.4000
1
1
[logo]¢U¢Z¢3¢T¢P
COP8SAC520N9XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAC5
MDIP
MDIP
MSL
MSL
COP8SAC528N8XXX
COP8SAC528N9XXX
28
28
Production N/A
Production N/A
N/A
N/A
10000+ $1.5700
10000+ $1.5500
1
1
28N8XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAC5
28N9XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAC540N8XXX
MDIP
MDIP
MSL
MSL
COP8SAC540N8XXX
COP8SAC540N9XXX
40
40
Production N/A
Production N/A
N/A
N/A
10000+ $1.8800
10000+ $1.7800
1
1
[logo]¢U¢Z¢3¢T¢P
COP8SAC540N9XXX
reel
of
N/A
[logo]¢U¢Z¢2¢T
COP8SAC5
Laminate
CSP
MSL
MSL
MSL
MSL
COP8SAC5SLB8XXX
COP8SAC5SLB9XXX
COP8SAC544V8XXX
COP8SAC544V9XXX
28
28
44
44
Production N/A
Production N/A
Production N/A
Production N/A
N/A
N/A
N/A
N/A
SLB8XXX
reel
of
N/A
[logo]¢U¢Z¢2¢P
COP8SAC5
Laminate
CSP
SLB9XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAC5
PLCC
PLCC
10000+ $1.7500
10000+ $1.7200
1
1
44V8XXX
[logo]¢U¢Z¢3¢T¢P
COP8SAC5
44V9XXX
General Description
Note: COP8SAx devices are instruction set and pin compatible supersets of the COP800 Family
devices, and are replacements for these in new designs when possible.
The COPSAx Rom based and OTP microcontrollers are highly integrated COP8™ feature core devices, with 1k
to 4k memory and advanced features including low EMI. These single-chip CMOS devices are suited for low
cost applications requiring a full featured controller, low EMI, and POR. 100% form-fit-function compatible
OTP versions are available with 1k, 2k, and 4k memory, and in a variety of packages including 28-pin CSP.
Erasable windowed versions are available for use with a range of COP8 software and hardware development
tools.
Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1 µs instruction cycle, one
multi-function 16-bit timer/counter with PWM output, MICROWIRE/PLUS™ serial I/O, two power saving
HALT/IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12 high current outputs, user selectable options
(WATCHDOG™, 4 clock/oscillator modes, power-on-reset), low EMI 2.7V to 5.5V operation, and
16/20/28/40/44 pin packages.
Devices included in this datasheet are:
Memory
(bytes)
Device
RAM (bytes) I/O Pins
Packages
Temperature
16/20/28
DIP/SOIC, 28
CSP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAA5
COP8SAB5
COP8SAC5
1k ROM
64
12/16/24
16/24
20/28 DIP/SOIC, 0 to +70°C, -40 to
28 CSP
2k ROM
4k ROM
128
128
+85°C, -40 to +125°C
20/28 DIP/SOIC,
16/24/36/40 28 CSP, 40 DIP,
44 PLCC/QFP
0 to +70°C, -40 to
+85°C, -40 to +125°C
16/20/28
DIP/SOIC, 28
CSP
0 to +70°C, -40 to
+85°C, -40 to +125°C
COP8SAA7
COP8SAB7
COP8SAC7
1k OTP EPROM 64
2k OTP EPROM 128
4k OTP EPROM 128
12/16/24
16/24
20/28 DIP/SOIC, 0 to +70°C, -40 to
28 CSP
+85°C, -40 to +125°C
20/28 DIP/SOIC,
28 CSP, 40 DIP,
44 PLCC/QFP
0 to +70°C, -40 to
+85°C, -40 to +125°C
16/24
COP8SAC7-Q3 4k EPROM
COP8SAC7-J3 4k EPROM
128
128
16/24/36
40
20/28/40 DIP
44 PLCC
Room Temp. Only
Room Temp. Only
Design Tools
Title
Size in Kbytes Date
Receive via Email
Download
View Online
Tools for Evaluation, Design,
and Programming
28-Nov-
2001
View Online Download Receive via Email
36 Kbytes
If you have trouble printing or viewing PDF file(s), see Printing Problems.
[Information as of 5-Aug-2002]
Search
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Purchasing
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Home
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Contact Us . Site Terms & Conditions of Use . Copyright 2002 © National Semiconductor Corporation . My Preferences .
Feedback
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