COP8SGF828V9_技术文档

October 2001

COP8SG Family

8-Bit CMOS ROM Based and OTP Microcontrollers with

8k to 32k Memory, Two Comparators and USART

Erasable windowed versions (Q3) are available for use with

a range of COP8 software and hardware development tools.

General Description

The COP8SG Family ROM and OTP based microcontrollers

Family features include an 8-bit memory mapped architec-

ture, 15 MHz CKI with 0.67 µs instruction cycle, 14 inter-

rupts, three multi-function 16-bit timer/counters with PWM,

™

are highly integrated COP8 Feature core devices with 8k

to 32k memory and advanced features including Analog

comparators, and zero external components. These single-

chip CMOS devices are suited for more complex applica-

tions requiring a full featured controller with larger memory,

™

full duplex USART, MICROWIRE/PLUS , two analog com-

parators, two power saving HALT/IDLE modes, MIWU, idle

timer, on-chip R/C oscillator, high current outputs, user se-

low EMI, two comparators, and

a full-duplex USART.

™

lectable options (WATCHDOG , 4 clock/oscillator modes,

COP8SGx7 devices are 100% form-fit-function compatible

OTP (One Time Programmable) versions for use in produc-

tion or development of the COP8SGx5 ROM.

power-on-reset), 2.7V to 5.5V operation, program code se-

curity, and 28/40/44 pin packages.

Devices included in this datasheet are:

RAM

Device

Memory (bytes)

8k ROM

I/O Pins

24/36/40

Packages

Temperature

(bytes)

28 DIP/SOIC, 40 DIP,

44 PLCC/QFP/CSP

28 DIP/SOIC, 40 DIP,

44 PLCC/QFP/CSP

28 DIP/SOIC, 40 DIP,

44 PLCC/QFP/CSP

28 DIP/SOIC, 40 DIP,

44 PLCC/QFP/CSP

28 DIP/SOIC, 40 DIP,

44 PLCC/QFP/CSP

28 DIP/SOIC, 40 DIP,

44 PLCC/QFP/CSP

28 DIP/SOIC, 40 DIP,

44 PLCC/QFP/CSP

28 DIP, 40 DIP, 44 PLCC

-40 to +85˚C,

-40 to +125˚C

-40 to +85˚C,

-40 to +125˚C

-40 to +85˚C,

-40 to +125˚C

-40 to +85˚C,

-40 to +125˚C

-40 to +85˚C,

-40 to +125˚C

-40 to +85˚C,

-40 to +125˚C

-40 to +85˚C,

-40 to +125˚C

Room Temp.

COP8SGE5

COP8SGG5

COP8SGH5

COP8SGK5

COP8SGR5

COP8SGE7

256

16k ROM

512

256

20k ROM

24k ROM

32k ROM

8k OTP EPROM

COP8SGR7

32k OTP EPROM

32k EPROM

512

24/36/40

COP8SGR7-Q3

n Fourteen multi-source vectored interrupts servicing

— External interrupt / Timers T0 — T3

— MICROWIRE/PLUS Serial Interface

— Multi-Input Wake Up

Key Features

n Low cost 8-bit microcontroller

n Quiet Design (low radiated emissions)

n Multi-Input Wakeup pins with optional interrupts (8 pins)

n Mask selectable clock options

— Crystal oscillator

— Crystal oscillator option with on-chip bias resistor

— External oscillator

— Software Trap

— USART (2; 1 receive and 1 transmit)

— Default VIS (default interrupt)

n 8-bit Stack Pointer SP (stack in RAM)

n Two 8-bit Register Indirect Data Memory Pointers

n True bit manipulation

— Internal R/C oscillator

n Internal Power-On-Reset—user selectable

n WATCHDOG and Clock Monitor Logic—user selectable

n Eight high current outputs

n 256 or 512 bytes on-board RAM

n 8k to 32k ROM or OTP EPROM with security feature

n BCD arithmetic instructions

Peripheral Features

n Multi-Input Wakeup Logic

n Three 16-bit timers (T1 — T3), each with two 16-bit

registers supporting:

— Processor Independent PWM mode

— External Event Counter mode

— Input Capture mode

CPU Features

n Versatile easy to use instruction set

n 0.67 µs instruction cycle time

™

COP8 is a trademark of National Semiconductor Corporation.

DS101317

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Peripheral Features (Continued)

Fully Static CMOS Design

<

n Low current drain (typically 4 µA)

n Idle Timer (T0)

n MICROWIRE/PLUS Serial Interface (SPI Compatible)

n Full Duplex USART

n Two power saving modes: HALT and IDLE

Temperature Range

n −40˚C to +85˚C, −40˚C to +125˚C

n Two Analog Comparators

I/O Features

Development Support

n Windowed packages for DIP and PLCC

n Real time emulation and debug tools available

n Software selectable I/O options (TRI-STATE^®

Output,Push-Pull Output, Weak Pull-Up Input, and High

Impedance Input)

n Schmitt trigger inputs on ports G and L

n Eight high current outputs

n Packages: 28 SO with 24 I/O pins, 40 DIP with 36 I/O

pins, 44 PLCC, PQFP and CSP with 40 I/O pins

Block Diagram

10131744

FIGURE 1. COP8SGx Block Diagram

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2

incrementing and post-decrementing, to name just a few

examples. In many cases, the instruction set can simulta-

neously execute as many as three functions with the same

single-byte instruction.

1.0 Device Description

1.1 ARCHITECTURE

The COP8 family is based on a modified Harvard architec-

ture, which allows data tables to be accessed directly from

program memory. This is very important with modern

microcontroller-based applications, since program memory

is usually ROM or EPROM, while data memory is usually

RAM. Consequently data tables need to be contained in

non-volatile memory, so they are not lost when the micro-

controller is powered down. In a modified Harvard architec-

ture, instruction fetch and memory data transfers can be

overlapped with a two stage pipeline, which allows the next

instruction to be fetched from program memory while the

current instruction is being executed using data memory.

This is not possible with a Von Neumann single-address bus

architecture.

JID: (Jump Indirect); Single byte instruction; decodes exter-

nal events and jumps to corresponding service routines

(analogous to “DO CASE” statements in higher level lan-

guages).

LAID: (Load Accumulator-Indirect); Single byte look up table

instruction provides efficient data path from the program

memory to the CPU. This instruction can be used for table

lookup and to read the entire program memory for checksum

calculations.

RETSK: (Return Skip); Single byte instruction allows return

from subroutine and skips next instruction. Decision to

branch can be made in the subroutine itself, saving code.

AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These

instructions use the two memory pointers B and X to effi-

ciently process a block of data (analogous to “FOR NEXT” in

higher level languages).

The COP8 family supports a software stack scheme that

allows the user to incorporate many subroutine calls. This

capability is important when using High Level Languages.

With a hardware stack, the user is limited to a small fixed

number of stack levels.

1.2.3 Bit-Level Control

Bit-level control over many of the microcontroller’s I/O ports

provides a flexible means to ease layout concerns and save

board space. All members of the COP8 family provide the

ability to set, reset and test any individual bit in the data

memory address space, including memory-mapped I/O ports

and associated registers.

1.2 INSTRUCTION SET

In today’s 8-bit microcontroller application arena cost/

performance, flexibility and time to market are several of the

key issues that system designers face in attempting to build

well-engineered products that compete in the marketplace.

Many of these issues can be addressed through the manner

in which a microcontroller’s instruction set handles process-

ing tasks. And that’s why COP8 family offers a unique and

code-efficient instruction set—one that provides the flexibil-

ity, functionality, reduced costs and faster time to market that

today’s microcontroller based products require.

1.2.4 Register Set

Three memory-mapped pointers handle register indirect ad-

dressing and software stack pointer functions. The memory

data pointers allow the option of post-incrementing or post-

decrementing with the data movement instructions (LOAD/

EXCHANGE). And 15 memory-maped registers allow de-

signers to optimize the precise implementation of certain

specific instructions.

Code efficiency is important because it enables designers to

pack more on-chip functionality into less program memory

space. Selecting

a microcontroller with less program

memory size translates into lower system costs, and the

added security of knowing that more code can be packed

into the available program memory space.

1.3 EMI REDUCTION

The COP8SGx5 family of devices incorporates circuitry that

guards against electromagnetic interference—an increasing

problem in today’s microcontroller board designs. National’s

patented EMI reduction technology offers low EMI clock

circuitry, gradual turn-on output drivers (GTOs) and internal

I_CCsmoothing filters, to help circumvent many of the EMI

issues influencing embedded control designs. National has

achieved 15 dB–20 dB reduction in EMI transmissions when

designs have incorporated its patented EMI reducing cir-

cuitry.

1.2.1 Key Instruction Set Features

The COP8 family incorporates a unique combination of in-

struction set features, which provide designers with optimum

code efficiency and program memory utilization.

Single Byte/Single Cycle Code Execution

The efficiency is due to the fact that the majority of instruc-

tions are of the single byte variety, resulting in minimum

program space. Because compact code does not occupy a

substantial amount of program memory space, designers

can integrate additional features and functionality into the

microcontroller program memory space. Also, the majority

instructions executed by the device are single cycle, result-

ing in minimum program execution time. In fact, 77% of the

instructions are single byte single cycle, providing greater

code and I/O efficiency, and faster code execution.

1.4 PACKAGING/PIN EFFICIENCY

Real estate and board configuration considerations demand

maximum space and pin efficiency, particularly given today’s

high integration and small product form factors. Microcon-

troller users try to avoid using large packages to get the I/O

needed. Large packages take valuable board space and

increases device cost, two trade-offs that microcontroller

designs can ill afford.

1.2.2 Many Single-Byte, Multifunction Instructions

The COP8 family offers a wide range of packages and do not

waste pins: up to 90.9% (or 40 pins in the 44-pin package)

are devoted to useful I/O.

The COP8 instruction set utilizes many single-byte, multi-

function instructions. This enables a single instruction to

accomplish multiple functions, such as DRSZ, DCOR, JID,

LD (Load) and

X (Exchange) instructions with post-

3

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Connection Diagrams

10131704

Top View

10131753

Top View

Order Number COP8SGXY28M8

See NS Package Number M28B

Order Number COP8SGXY28N8

See NS Package Number N28B

Order Number COP8SGR728Q3

See NS Package Number D28JQ

Order Number COP8SGR7HLQ8

See NS Package Number LQA44A

10131705

Top View

Order Number COP8SGXY40N8

See NS Package Number N40A

Order Number COP8SGR5740Q3

See NS Package Number D40KQ

10131706

10131743

Top View

Order Number COP8SGXY44V8

Order Number COP8SGXYVEJ8

See NS Package Number VEJ44A

See NS Package Number V44A

Order Number COP8SGR744J3

See NS Package Number EL44C

Note 1: X = E for 8k, G for 16k,

H for 20k, K for 24k, R for 32k

Y = 5 for ROM, 7 for OTP

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4

Pinouts for 28 -, 40- and 44-Pin Packages

28-Pin

44-Pin

PLCC

17

18

19

20

25

26

27

28

39

40

41

42

3

Port

Type

Alt. Fun

40-Pin DIP

44-Pin PQFP

44-Pin CSP

SO

11

12

13

14

15

16

17

18

25

26

27

28

1

L0

I/O

I

MIWU

17

18

19

20

21

22

23

24

35

36

37

38

3

11

12

13

14

19

20

21

22

33

34

35

36

41

42

43

44

23

24

25

26

27

28

29

30

3

12

13

14

15

20

21

22

23

34

35

36

37

42

43

44

1

L1

MIWU or CKX

MIWU or TDX

MIWU or RDX

MIWU or T2A

MIWU or T2B

MIWU or T3A

MIWU or T3B

INT

L2

L3

L4

L5

L6

L7

G0

G1

G2

G3

G4

G5

G6

G7

D0

D1

D2

D3

D4

D5

D6

D7

F0

F1

F2

F3

F4

F5

F6

F7

C0

C1

C2

C3

C4

C5

C6

C7

WDOUT*

T1B

T1A

SO

SK

2

4

SI

3

5

I

CKO

4

6

O

19

20

21

22

25

26

27

28

29

30

31

32

9

29

30

31

32

33

34

35

36

9

24

25

26

27

28

29

30

31

4

O

I/O

7

8

COMP1IN−

COMP1IN+

COMP1OUT

COMP2IN−

COMP2IN+

COMP2OUT

10

11

12

13

14

15

16

39

40

1

10

11

12

13

14

15

16

43

44

1

4

5

9

5

6

10

6

7

8

9

10

11

38

39

40

41

16

17

18

19

3

10

37

38

39

40

15

16

17

18

2

21

22

23

24

V_CC

6

23

5

8

33

7

8

37

7

GND

CKI

31

1

32

2

I

RESET

24

34

38

32

33

* G1 operation as WDOUT is controlled by ECON bit 2.

5

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2.1 Ordering Information

10131708

FIGURE 2. Part Numbering Scheme

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3.0 Electrical Characteristics

Total Current out of

GND Pin (Sink)

Storage Temperature

Range

110 mA

Absolute Maximum Ratings ^{(Note 2)}

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

−65˚C to +140˚C

2kV (Human Body

Model)

ESD Protection Level

Supply Voltage (V_CC

Voltage at Any Pin

)

7V

Note 2: Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

−0.3V to V_CC+0.3V

Total Current into V_CC

Pin (Source)

100 mA

DC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C unless otherwise specified.

Parameter

Operating Voltage

Conditions

Min

2.7

10

0

Typ

Max

5.5

50 x 10⁶

Units

V

Power Supply Rise Time

V_CCStart Voltage to Guarantee POR

ns

V

0.25

Power Supply Ripple (Note 4)

Supply Current (Note 5)

CKI = 15 MHz

Peak-to-Peak

0.1 V_cc

V

V_CC= 5.5V, t_C= 0.67 µs

V_CC= 5.5V, t_C= 1 µs

9.0

6.0

2.1

10

mA

µA

CKI = 10 MHz

CKI = 4 MHz

V_CC= 4.5V, t_C= 2.5 µs

V_CC= 5.5V, CKI = 0 MHz

<

HALT Current (Note 6)

IDLE Current (Note 5)

CKI = 15 MHz

4

V_CC= 5.5V, t_C= 0.67 µs

V_CC= 5.5V, t_C= 1 µs

V_CC= 4.5V, t_C= 2.5 µs

2.25

1.5

mA

CKI = 10 MHz

CKI = 4 MHz

0.8

Input Levels (V_IH, V_IL)

RESET

Logic High

0.8 V_cc

V

Logic Low

0.2 V_cc

CKI, All Other Inputs

Logic High

0.7 V_cc

0.5

V

Logic Low

0.2 V_cc

2

Internal Bias Resistor for the

Crystal/Resonator Oscillator

CKI Resistance to V_CCor GND when R/C

Oscillator is selected

Hi-Z Input Leakage

Input Pullup Current

G and L Port Input Hysteresis

1

MΩ

V_CC= 5.5V

5

8

11

kΩ

V_CC= 5.5V

−2

−40

+2

µA

V

V_CC= 5.5V, V_IN= 0V

V_CC= 5.5V

−250

0.25 V_cc

7

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DC Electrical Characteristics (Continued)

−40˚C ≤ T_A≤ +85˚C unless otherwise specified.

Parameter

Output Current Levels

Conditions

Min

Typ

Max

Units

D Outputs

Source

V_CC= 4.5V, V_OH= 3.3V

V_CC= 2.7V, V_OH= 1.8V

V_CC= 4.5V, V_OL= 1.0V

V_CC= 2.7V, V_OL= 0.4V

−0.4

-0.2

10

mA

Sink

2

All Others

Source (Weak Pull-Up Mode)

V_CC= 4.5V, V_OH= 2.7V

V_CC= 2.7V, V_OH= 1.8V

V_CC= 4.5V, V_OH= 3.3V

V_CC= 2.7V, V_OH= 1.8V

V_CC= 4.5V, V_OL= 0.4V

V_CC= 2.7V, V_OL= 0.4V

V_CC= 5.5V

−10.0

-2.5

−0.4

-0.2

1.6

−110

-33

µA

Source (Push-Pull Mode)

Sink (Push-Pull Mode)

mA

µA

0.7

TRI-STATE Leakage

−2

+2

Allowable Sink Current per Pin (Note 9)

D Outputs and L0 to L3

15

3

mA

All Others

Maximum Input Current without Latchup

(Note 7)

Room Temp.

±

200

mA

RAM Retention Voltage, Vr

V_CCRise Time from a V_CC≥ 2.0V

EPROM Data Retenton (Note 8), (Note 9)

Input Capacitance

2.0

12

V

µs

(Note 10)

T_A= 55˚C

(Note 9)

>

29

years

pF

7

1000

Load Capacitance on D2

pF

AC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t_C)

Crystal/Resonator, External

4.5V ≤ V_CC≤ 5.5V

2.7V ≤ V_CC≤ 4.5V

4.5V ≤ V_CC≤ 5.5V

fr = Max

0.67

2

µs

%

R/C Oscillator (Internal)

Frequency Variation (Note 9)

External CKI Clock Duty Cycle (Note 9)

Rise Time (Note 9)

2

±

35

45

55

8

%

fr = 10 MHz Ext Clock

ns

Fall Time (Note 9)

5

MICROWIRE Setup Time (t_UWS) (Note

11)

20

56

MICROWIRE Hold Time (t_UWH) (Note

11)

ns

MICROWIRE Output Propagation Delay

(t_UPD) (Note 11)

220

Input Pulse Width (Note 9)

Interrupt Input High Time

Interrupt Input Low Time

Timer 1, 2, 3, Input High Time

Timer 1 2, 3, Input Low Time

Reset Pulse Width

1

t_C

µs

Note 3: t = Instruction cycle time.

C

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8

AC Electrical Characteristics (Continued)

<

Note 4: Maximum rate of voltage change must be 0.5 V/ms.

Note 5: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, External Oscillator, inputs connected to V and outputs driven low

CC

but not connected to a load.

Note 6: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal

or external configuration, CKI is TRI-STATE. Measurement of I

HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5

DD

programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V ; clock monitor disabled. Parameter refers

CC

to HALT mode entered via setting bit 7 of the G Port data register.

>

Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages

V

and the pins will have sink current to V when

CC CC

>

biased at voltages

V

(the pins do not have source current when biased at a voltage below V ). The effective resistance to V is 750Ω (typical). These two

C

<

pins will not latch up. The voltage at the pins must be limited to 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes

ESD transients.

Note 8: National Semiconductor uses the High Temperature Storage Life (HTSL) test to evaluate the data retention capabilities of the EPROM memory cells used

in our OTP microcontrollers. Qualification devices have been stressed at 150˚C for 1000 hours. Under these conditions, our EPROM cells exhibit data retention

capabilities in excess of 29 years. This is based on an activation energy of 0.7eV derated to 55˚C.

Note 9: Parameter characterized but not tested.

Note 10: Rise times faster than the minimum specification may trigger an internal power-on-reset.

Note 11: MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See and the MICROWIRE

operation description.

Comparators AC and DC Characteristics

V_CC= 5V, −40˚C ≤ T_A≤ +85˚C.

Parameter

Input Offset Voltage (Note 12)

Input Common Mode Voltage Range

Voltage Gain

Conditions

Min

Typ

Max

Units

mV

V

±

0.4V ≤ V_IN≤ V_CC− 1.5V

5

15

0.4

V_CC− 1.5

100

dB

Low Level Output Current

High Level Output Current

DC Supply Current per Comparator

(When Enabled)

V_OL= 0.4V

−1.6

1.6

mA

µA

V_OH= V_CC− 0.4V

150

Response Time (Note 13)

200 mV step input

100 mV Overdrive,

100 pF Load

600

ns

Comparator Enable Time(Note 14)

Note 12: The comparator inputs are high impedance port inputs and, as such, input current is limited to port input leakage current.

Note 13: Response time is measured from a step input to a valid logic level at the comparator output. software response time is dependent of instruction execution.

Note 14: Comparator enable time is that delay time required between the end of the instruction cycle that enables the comparator and using the output of the

comparator, either by hardware or by software.

10131709

FIGURE 3. MICROWIRE/PLUS Timing

9

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Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature

Range

−65˚C to +140˚C

2kV (Human Body

Model)

ESD Protection Level

Supply Voltage (V_CC

Voltage at Any Pin

)

7V

Note 15: Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

−0.3V to V_CC+0.3V

Total Current into V_CC

Pin (Source)

100 mA

110 mA

Total Current out of

GND Pin (Sink)

DC Electrical Characteristics

−40˚C ≤ T_A≤ +125˚C unless otherwise specified.

Parameter

Operating Voltage

Conditions

Min

4.5

10

0

Typ

Max

5.5

50 x 10⁶

Units

V

Power Supply Rise Time

V_CCStart Voltage to Guarantee POR

ns

V

0.25

Power Supply Ripple (Note 4)

Supply Current (Note 5)

CKI = 10 MHz

Peak-to-Peak

0.1 V_cc

V

V_CC= 5.5V, t_C= 1 µs

6.0

2.1

10

mA

µA

CKI = 4 MHz

V_CC= 4.5V, t_C= 2.5 µs

V_CC= 5.5V, CKI = 0 MHz

<

HALT Current (Note 6)

IDLE Current (Note 5)

CKI = 10 MHz

4

V_CC= 5.5V, t_C= 1 µs

V_CC= 4.5V, t_C= 2.5 µs

1.5

0.8

mA

CKI = 4 MHz

Input Levels (V_IH, V_IL)

RESET

Logic High

0.8 V_cc

V

Logic Low

0.2 V_cc

CKI, All Other Inputs

Logic High

0.7 V_cc

0.5

V

Logic Low

0.2 V_cc

2

Internal Bias Resistor for the

Crystal/Resonator Oscillator

CKI Resistance to V_CCor GND when R/C

Oscillator is selected

Hi-Z Input Leakage

Input Pullup Current

G and L Port Input Hysteresis

Output Current Levels

D Outputs

1

MΩ

V_CC= 5.5V

5

8

11

kΩ

V_CC= 5.5V

−5

−35

+5

µA

V

V_CC= 5.5V, V_IN= 0V

V_CC= 5.5V

−400

0.25 V_cc

Source

V_CC= 4.5V, V_OH= 3.3V

V_CC= 4.5V, V_OL= 1.0V

−0.4

9

mA

Sink

All Others

Source (Weak Pull-Up Mode)

Source (Push-Pull Mode)

Sink (Push-Pull Mode)

TRI-STATE Leakage

Allowable Sink Current per Pin (Note 9)

D Outputs and L0 to L3

All Others

V_CC= 4.5V, V_OH= 2.7V

V_CC= 4.5V, V_OH= 3.3V

V_CC= 4.5V, V_OL= 0.4V

V_CC= 5.5V

−9

−0.4

1.4

−5

−140

+5

µA

mA

µA

15

3

mA

3

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10

DC Electrical Characteristics (Continued)

−40˚C ≤ T_A≤ +125˚C unless otherwise specified.

Parameter

Maximum Input Current without Latchup

(Note 7)

Conditions

Min

Typ

Max

Units

Room Temp.

±

200

mA

RAM Retention Voltage, Vr

V_CCRise Time from a V_CC≥ 2.0V

EPROM Data Retenton (Note 8),(Note 9)

Input Capacitance

2.0

12

V

µs

(Note 10)

T_A= 55˚C

(Note 9)

>

29

years

pF

7

Load Capacitance on D2

1000

pF

11

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AC Electrical Characteristics

−40˚C ≤ T_A≤ +125˚C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t_C)

Crystal/Resonator, External

R/C Oscillator (Internal)

Frequency Variation (Note 9)

External CKI Clock Duty Cycle (Note 9)

Rise Time (Note 9)

4.5V ≤ V_CC≤ 5.5V

fr = Max

1

µs

%

2

±

35

45

55

12

8

%

fr = 10 MHz Ext Clock

ns

Fall Time (Note 9)

MICROWIRE Setup Time (t_UWS) (Note

11)

20

56

MICROWIRE Hold Time (t_UWH) (Note

11)

ns

MICROWIRE Output Propagation Delay

(t_UPD) (Note 11)

220

Input Pulse Width (Note 9)

Interrupt Input High Time

Interrupt Input Low Time

Timer 1, 2, 3, Input High Time

Timer 1 2, 3, Input Low Time

Reset Pulse Width

1

t_C

µs

Comparators AC and DC Characteristics

V_CC= 5V, −40˚C ≤ T_A≤ +125˚C.

Parameter

Input Offset Voltage (Note 12)

Input Common Mode Voltage Range

Voltage Gain

Conditions

Min

Typ

Max

Units

±

0.4V ≤ V_IN≤ V_CC− 1.5V

5

25

mV

V

0.4

V_CC− 1.5

100

dB

mA

µA

Low Level Output Current

High Level Output Current

DC Supply Current per Comparator

(When Enabled)

V_OL= 0.4V

−1.6

1.6

V_OH= V_CC− 0.4V

150

Response Time (Note 13)

200 mV step input

100 mV Overdrive,

600

ns

Comparator Enable Time

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12

Typical Performance Characteristics T_A= 25˚C (unless otherwise specified)

10131749

10131750

10131751

10131752

13

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dedicated WATCHDOG output with weak pullup if

WATCHDOG feature is selected by the Mask Option reg-

ister. The pin is a general purpose I/O if WATCHDOG

feature is not selected. If WATCHDOG feature is selected,

bit 1 of the Port G configuration and data register does not

have any effect on Pin G1 setup. Pin G7 is either input or

output depending on the oscillator option selected. With the

crystal oscillator option selected, G7 serves as the dedicated

output pin for the CKO clock output. With the internal R/C or

the external oscillator option selected, G7 serves as a gen-

eral purpose Hi-Z input pin and is also used to bring the

device out of HALT mode with a low to high transition on G7.

4.0 Pin Descriptions

The COP8SGx I/O structure enables designers to reconfig-

ure the microcontroller’s I/O functions with a single instruc-

tion. Each individual I/O pin can be independently configured

as output pin low, output high, input with high impedance or

input with weak pull-up device. A typical example is the use

of I/O pins as the keyboard matrix input lines. The input lines

can be programmed with internal weak pull-ups so that the

input lines read logic high when the keys are all open. With

a key closure, the corresponding input line will read a logic

zero since the weak pull-up can easily be overdriven. When

the key is released, the internal weak pull-up will pull the

input line back to logic high. This eliminates the need for

external pull-up resistors. The high current options are avail-

able for driving LEDs, motors and speakers. This flexibility

helps to ensure a cleaner design, with less external compo-

nents and lower costs. Below is the general description of all

available pins.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin (crystal clock option) or general purpose

input (R/C or external clock option), the associated bits in the

data and configuration registers for G6 and G7 are used for

special purpose functions as outlined below. Reading the G6

and G7 data bits will return zeroes.

Each device will be placed in the HALT mode by writing a “1”

to bit 7 of the Port G Data Register. Similarly the device will

be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

V_CCand GND are the power supply pins. All V_CCand GND

pins must be connected.

CKI is the clock input. This can come from the Internal R/C

oscillator, external, or a crystal oscillator (in conjunction with

CKO). See Oscillator Description section.

Writing a “1” to bit 6 of the Port G Configuration Register

enables the MICROWIRE/PLUS to operate with the alter-

nate phase of the SK clock. The G7 configuration bit, if set

high, enables the clock start up delay after HALT when the

R/C clock configuration is used.

RESET is the master reset input. See Reset description

section.

Each device contains four bidirectional 8-bit I/O ports (C, G,

L and F), where each individual bit may be independently

configured as an input (Schmitt trigger inputs on ports L and

G), output or TRI-STATE under program control. Three data

memory address locations are allocated for each of these

I/O ports. Each I/O port has two associated 8-bit memory

mapped registers, the CONFIGURATION register and the

output DATA register. A memory mapped address is also

reserved for the input pins of each I/O port. (See the memory

map for the various addresses associated with the I/O ports.)

Figure 4 shows the I/O port configurations. The DATA and

CONFIGURATION registers allow for each port bit to be

individually configured under software control as shown be-

low:

Config. Reg.

CLKDLY

Alternate SK

Data Reg.

HALT

IDLE

G7

G6

Port G has the following alternate features:

G7 CKO Oscillator dedicated output or general purpose

input

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

CONFIGURATION

Register

DATA

Port Set-Up

Hi-Z Input

Register

G1 WDOUT WATCHDOG and/or CLock Monitor if WATCH-

DOG enabled, otherwise it is a general purpose I/O

0

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

G0 INTR (External Interrupt Input)

0

1

0

1

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation on these unterminated pins

will return unpredictable values. The 28 pin device do not

offer Port C. On this device, the associated Port C Data and

Configuration registers should not be used.

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on

the inputs.

Port L supports the Multi-Input Wake Up feature on all eight

pins. Port L has the following alternate pin functions:

Port F is an 8-bit I/O port. The 28--pin device does not have

a full complement of Port F pins. The unavailable pins are

not terminated. A read operation on these unterminated pins

will return unpredictable values.

L7 Multi-input Wakeup or T3B (Timer T3B Input)

L6 Multi-input Wakeup or T3A (Timer T3A Input)

L5 Multi-input Wakeup or T2B (Timer T2B Input)

L4 Multi-input Wakeup or T2A (Timer T2A Input)

L3 Multi-input Wakeup and/or RDX (USART Receive)

L2 Multi-input Wakeup or TDX (USART Transmit)

L1 Multi-input Wakeup and/or CKX (USART Clock)

L0 Multi-input Wakeup

Port F1–F3 are used for Comparator 1. Port F4–F6 are used

for Comparator 2.

The Port F has the following alternate features:

F6 COMP2OUT (Comparator 2 Output)

F5 COMP2+IN (Comparator 2 Positive Input)

F4 COMP2-IN (Comparator 2 Negative Input)

F3 COMP1OUT (Comparator 1 Output)

Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O

ports. Pin G6 is always a general purpose Hi-Z input. All pins

have Schmitt Triggers on their inputs.Pin G1 serves as the

F2 COMP1+IN (Comparator 1 Positive Input)

F1 COMP1-IN (Comparator 1 Negative Input)

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14

4.0 Pin Descriptions (Continued)

Note: For compatibility with existing software written for COP888xG devices

and with existing Mask ROM devices, a read of the Port I input pins

(address xxD7) will return the same data as reading the Port F input

pins (address xx96). It is recommended new applications which will go

to production with the COP8SGx use the Port F addresses. Note that

compatible ROM devices contains the input only Port I instead of the

bi-directional Port F.

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs

(except D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At RESET, the

external loads on this pin must ensure that the output voltages stay

above 0.7 V

to prevent the chip from entering special modes. Also

CC

keep the external loading on D2 to less than 1000 pF.

10131712

FIGURE 5. I/O Port Configurations—Output Mode

10131710

FIGURE 4. I/O Port Configurations

10131711

FIGURE 6. I/O Port Configurations—Input Mode

15

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dresses 0F0 to 0FE Hex. These registers can be loaded

immediately, and also decremented and tested with the

DRSZ (decrement register and skip if zero) instruction. The

memory pointer registers X, SP and B are memory mapped

into this space at address locations 0FC to 0FE Hex respec-

tively, with the other registers (except 0FF) being available

for general usage.

5.0 Functional Description

The architecture of the devices are a modified Harvard ar-

chitecture. With the Harvard architecture, the program

memory ROM is separated from the data store memory

(RAM). Both ROM and RAM have their own separate ad-

dressing space with separate address buses. The architec-

ture, though based on the Harvard architecture, permits

transfer of data from ROM to RAM.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumu-

lator (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

5.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t_C) cycle time.

There are six CPU registers:

5.4 DATA MEMORY SEGMENT RAM EXTENSION

A is the 8-bit Accumulator Register

Data memory address 0FF is used as a memory mapped

location for the Data Segment Address Register (S).

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

The data store memory is either addressed directly by a

single byte address within the instruction, or indirectly rela-

tive to the reference of the B, X, or SP pointers (each

contains a single-byte address). This single-byte address

allows an addressing range of 256 locations from 00 to FF

hex. The upper bit of this single-byte address divides the

data store memory into two separate sections as outlined

previously. With the exception of the RAM register memory

from address locations 00F0 to 00FF, all RAM memory is

memory mapped with the upper bit of the single-byte ad-

dress being equal to zero. This allows the upper bit of the

single-byte address to determine whether or not the base

address range (from 0000 to 00FF) is extended. If this upper

bit equals one (representing address range 0080 to 00FF),

then address extension does not take place. Alternatively, if

this upper bit equals zero, then the data segment extension

register S is used to extend the base address range (from

0000 to 007F) from XX00 to XX7F, where XX represents the

8 bits from the S register. Thus the 128-byte data segment

extensions are located from addresses 0100 to 017F for

data segment 1, 0200 to 027F for data segment 2, etc., up to

FF00 to FF7F for data segment 255. The base address

range from 0000 to 007F represents data segment 0.

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

S is the 8-bit Segment Address Register used to extend the

lower half of the address range (00 to 7F) into 256 data

segments of 128 bytes each.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). With reset the SP is initialized to

RAM address 02F Hex (devices with 64 bytes of RAM), or

initialized to RAM address 06F Hex (devices with 128 bytes

of RAM).

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

5.2 PROGRAM MEMORY

The program memory consists of varies sizes of ROM.

These bytes may hold program instructions or constant data

(data tables for the LAID instruction, jump vectors for the JID

instruction, and interrupt vectors for the VIS instruction). The

program memory is addressed by the 15-bit program

counter (PC). All interrupts in the device vector to program

memory location 0FF Hex. The contents of the program

memory read 00 Hex in the erased state. Program execution

starts at location 0 after RESET.

Figure 7 illustrates how the S register data memory exten-

sion is used in extending the lower half of the base address

range (00 to 7F hex) into 256 data segments of 128 bytes

each, with a total addressing range of 32 kbytes from XX00

to XX7F. This organization allows a total of 256 data seg-

ments of 128 bytes each with an additional upper base

segment of 128 bytes. Furthermore, all addressing modes

are available for all data segments. The S register must be

changed under program control to move from one data

segment (128 bytes) to another. However, the upper base

segment (containing the 16 memory registers, I/O registers,

control registers, etc.) is always available regardless of the

contents of the S register, since the upper base segment

(address range 0080 to 00FF) is independent of data seg-

ment extension.

5.3 DATA MEMORY

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

register, and the various registers, and counters associated

with the timers (with the exception of the IDLE timer). Data

memory is addressed directly by the instruction or indirectly

by the B, X and SP pointers.

The data memory consists of 256 or 512 bytes of RAM.

Sixteen bytes of RAM are mapped as “registers” at ad-

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16

5.0 Functional Description (Continued)

10131745

FIGURE 7. RAM Organization

The format of the ECON register is as follows:

The instructions that utilize the stack pointer (SP) always

reference the stack as part of the base segment (Segment

0), regardless of the contents of the S register. The S register

is not changed by these instructions. Consequently, the

stack (used with subroutine linkage and interrupts) is always

located in the base segment. The stack pointer will be initial-

ized to point at data memory location 006F as a result of

reset.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

POR

SECURITY CKI 2

CKI 1 WATCH

DOG

F-Port

HALT

Bit 7

Bit 6

= x

This is for factory test. The polarity is “Don’t

Care.”

= 1

= 0

= 1

Power-on reset enabled.

Power-on reset disabled.

Security enabled.

The 128 bytes of RAM contained in the base segment are

split between the lower and upper base segments. The first

112 bytes of RAM are resident from address 0000 to 006F in

the lower base segment, while the remaining 16 bytes of

RAM represent the 16 data memory registers located at

addresses 00F0 to 00FF of the upper base segment. No

RAM is located at the upper sixteen addresses (0070 to

007F) of the lower base segment.

Bit 5

Bits 4, 3 = 0, 0 External CKI option selected. G7 is avail-

able as a HALT restart and/or general pur-

pose input. CKI is clock input.

= 0, 1 R/C oscillator option selected. G7 is avail-

able as a HALT restart and/or general pur-

pose input. CKI clock input. Internal R/C

components are supplied for maximum R/C

frequency.

Additional RAM beyond these initial 128 bytes, however, will

always be memory mapped in groups of 128 bytes (or less)

at the data segment address extensions (XX00 to XX7F) of

the lower base segment. The additional 384 bytes of RAM in

this device are memory mapped at address locations 0100

to 017F, 0200 to 027F and 0300 to 037F hex.

= 1, 0 Crystal oscillator with on-chip crystal bias

resistor disabled. G7 (CKO) is the clock

generator output to crystal/resonator.

Memory address ranges 0200 to 027F and 0300 to 037F are

unavailable on the COP8SGx5 and, if read, will return un-

derfined data.

= 1, 1 Crystal oscillator with on-chip crystal bias

resistor enabled. G7 (CKO) is the clock gen-

erator output to crystal/resonator.

Bit 2

Bit 1

= 1

= 0

= 1

WATCHDOG feature disabled. G1 is a gen-

eral purpose I/O.

5.5 ECON (CONFIGURATION) REGISTER

For compatibility with COP8SGx7 devices, mask options are

defined by an ECON Configuration Register which is pro-

grammed at the same time as the program code. Therefore,

the register is programmed at the same time as the program

memory.

WATCHDOG feature enabled. G1 pin is

WATCHDOG output with weak pullup.

Force port I compatibility. Disable port F

outputs and pull-ups. This is intended for

compatibility with existing code and Mask

ROMMed devices only. This bit should be

17

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The recommended erasure procedure for windowed devices

is exposure to short wave ultraviolet light which has a wave-

length of 2537 Angstroms (Å). The integrated dose (i.e. UV

intensity X exposure time) for erasure should be a minimum

of 15W-sec/cm².

5.0 Functional Description (Continued)

programmed to 0 for all other applications.

= 0

= 1

= 0

Enable full port F capability.

HALT mode disabled.

HALT mode enabled.

Bit 0

5.9 RESET

The devices are initialized when the RESET pin is pulled low

or the On-chip Power-On Reset is enabled.

5.6 USER STORAGE SPACE IN EPROM

The ECON register is outside of the normal address range of

the ROM and can not be accessed by the executing soft-

ware.

The COP8 assembler defines a special ROM section type,

CONF, into which the ECON may be coded. Both ECON and

User Data are programmed automatically by programmers

that are certified by National.

The following examples illustrate the declaration of ECON

and the User information.

10131713

Syntax:

[label:] .sect

.db

econ, conf

value ;1 byte,

FIGURE 8. Reset Logic

;configures options

; up to 8 bytes

The following occurs upon initialization:

Port L: TRI-STATE (High Impedance Input)

Port C: TRI-STATE (High Impedance Input)

Port G: TRI-STATE (High Impedance Input)

Port F: TRI-STATE (High Impedance Input)

Port D: HIGH

.db

.endsect

Example: The following sets a value in the ECON register

and User Identification for a COP8SGR728M7. The ECON

bit values shown select options: Power-on enabled, Security

disabled, Crystal oscillator with on-chip bias disabled,

WATCHDOG enabled and HALT mode enabled.

PC: CLEARED to 0000

.sect econ, conf

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR:

.db

0x55

;por, xtal, wd, halt

'my v1.00' ;user data declaration

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

T2CNTRL: CLEARED

.endsect

5.7 OTP SECURITY

The device has a security feature that, when enabled, pre-

vents external reading of the OTP program memory. The

security bit in the ECON register determines, whether secu-

rity is enabled or disabled. If the security feature is disabled,

the contents of the internal EPROM may be read.

T3CNTRL: CLEARED

Accumulator, Timer 1, Timer 2 and Timer 3:

RANDOM after RESET with crystal clock option

(power already applied)

If the security feature is enabled, then any attempt to

externally read the contents of the EPROM will result in

the value FF Hex being read from all program locations

Under no circumstances can a secured part be read. In

addition, with the security feature enabled, the write opera-

tion to the EPROM program memory and ECON register is

inhibited. The ECON register is readable regardless of the

state of the security bit. The security bit, when set, cannot

be erased, even in windowed packages. If the security bit

is set in a device in a windowed package, that device may be

erased but will not be further programmable.

UNAFFECTED after RESET with R/C clock option

(power already applied)

RANDOM after RESET at power-on

WKEN, WKEDG: CLEARED

WKPND: RANDOM

SP (Stack Pointer):

Initialized to RAM address 06F Hex

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

S Register: CLEARED

If security is being used, it is recommended that all other bits

in the ECON register be programmed first. Then the security

bit can be programmed.

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

USART:

5.8 ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that era-

sure begins to occur when exposed to light with wavelengths

shorter than approximately 4000 Angstroms (Å). It should be

noted that sunlight and certain types of fluorescent lamps

have wavelengths in the 3000Å - 4000Å range.

PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit

which is set to one.

COMPARATORS:

After programming, opaque labels should be placed over the

window of windowed devices to prevent unintentional era-

sure. Covering the window will also prevent temporary func-

tional failure due to the generation of photo currents.

CMPSL; CLEARED

WATCHDOG (if enabled):

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18

RESET pin should be connected directly, or through a

pull-up resistor, to V_CC. The output of the power-on reset

detector will always preset the Idle timer to 0FFF(4096 t_C).

At this time, the internal reset will be generated.

5.0 Functional Description (Continued)

The device comes out of reset with both the WATCH-

DOG logic and the Clock Monitor detector armed, with the

WATCHDOG service window bits set and the Clock Monitor

bit set. The WATCHDOG and Clock Monitor circuits are

inhibited during reset. The WATCHDOG service window bits

being initialized high default to the maximum WATCHDOG

service window of 64k t_Cclock cycles. The Clock Monitor bit

being initialized high will cause a Clock Monitor error follow-

ing reset if the clock has not reached the minimum specified

frequency at the termination of reset. A Clock Monitor error

will cause an active low error output on pin G1. This error

output will continue until 16 t_C–32 t_Cclock cycles following

the clock frequency reaching the minimum specified value,

at which time the G1 output will go high.

If the Power-On Reset feature is enabled, the internal reset

will not be turned off until the Idle timer underflows. The

internal reset will perform the same functions as external

reset. The user is responsible for ensuring that V_CCis at the

minimum level for the operating frequency within the 4096

t_C. After the underflow, the logic is designed such that no

additional internal resets occur as long as V_CCremains

above 2.0V.

The contents of data registers and RAM are unknown fol-

lowing the on-chip reset.

5.9.1 External Reset

The RESET input when pulled low initializes the device. The

RESET pin must be held low for a minimum of one instruc-

tion cycle to guarantee a valid reset. During Power-Up ini-

tialization, the user must ensure that the RESET pin is held

low until the device is within the specified V_CCvoltage. An

R/C circuit on the RESET pin with a delay 5 times (5x)

greater than the power supply rise time or 15 µs whichever is

greater, is recommended. Reset should also be wide enough

to ensure crystal start-up upon Power-Up.

RESET may also be used to cause an exit from the HALT

mode.

A recommended reset circuit for this device is shown in

Figure 9.

10131714

>

RC 5x power supply rise time or 15 µs, whichever is greater.

10131715

FIGURE 9. Reset Circuit Using External Reset

5.9.2 On-Chip Power-On Reset

FIGURE 10. Reset Timing (Power-On Reset Enabled)

with V_CCTied to RESET

The on-chip reset circuit is selected by a bit in the ECON

register. When enabled, the device generates an internal

reset as V_CCrises to a voltage level above 2.0V. The on-chip

reset circuitry is able to detect both fast and slow rise times

on V_CC(V_CCrise time between 10 ns and 50 ms).To guar-

antee an on-chip power-on-reset, V_CCmust start at a voltage

less than the start voltage specified in the DC characteris-

tics. Also, if V_CCbe lowered to the start voltage before

powering back up to the operating range. If this is not pos-

sible, it is recommended that external reset be used.

10131716

Under no circumstances should the RESET pin be allowed

to float. If the on-chip Power-On Reset feature is being used,

FIGURE 11. Reset Circuit Using Power-On Reset

19

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specified duty cycle, rise and fall times, and input levels.

G7/CKO is available as a general purpose input G7 and/or

Halt control. Figure 13 shows the external oscillator connec-

tion diagram.

5.0 Functional Description (Continued)

5.10 OSCILLATOR CIRCUITS

There are four clock oscillator options available: Crystal

Oscillator with or without on-chip bias resistor, R/C Oscillator

with on-chip resistor and capacitor, and External Oscillator.

The oscillator feature is selected by programming the ECON

register, which is summarized in Table 1.

5.10.3 R/C Oscillator

The R/C Oscillator mode can be selected by programming

ECON Bit 3 to 1 and ECON Bit 4 to 0. In R/C oscillation

mode, CKI is left floating, while G7/CKO is available as a

general purpose input G7 and/or HALT control. The R/C

controlled oscillator has on-chip resistor and capacitor for

maximum R/C oscillator frequency operation. The maximum

TABLE 1. Oscillator Option

ECON4 ECON3

Oscillator Option

External Oscillator

±

frequency is 5 MHz

35% for V_CCbetween 4.5V to 5.5V

0

1

0

1

0

1

and temperature range of −40˚C to +85˚C. For max fre-

quency operation, the CKI pin should be left floating. For

lower frequencies, an external capacitor should be con-

nected between CKI and either V_CCor GND. Immunity of the

R/C oscillator to external noise can be improved by connect-

ing one half the external capacitance to V_CCand one half to

GND. PC board trace length on the CKI pin should be kept

as short as possible. Table 3 shows the oscillator frequency

as a function of external capacitance on the CKI pin. Figure

14 shows the R/C oscillator configuration.

Crystal Oscillator without Bias Resistor

R/C Oscillator

Crystal Oscillator with Bias Resistor

5.10.1 Crystal Oscillator

The crystal Oscillator mode can be selected by programming

ECON Bit 4 to 1. CKI is the clock input while G7/CKO is the

clock generator output to the crystal. An on-chip bias resistor

connected between CKI and CKO can be enabled by pro-

gramming ECON Bit 3 to 1 with the crystal oscillator option

selection. The value of the resistor is in the range of 0.5M to

2M (typically 1.0M). Table 2 shows the component values

required for various standard crystal values. Resistor R2 is

only used when the on-chip bias resistor is disabled. Figure

12 shows the crystal oscillator connection diagram.

TABLE 3. R/C Oscillator Configuration,

−40˚C to +85˚C, V_CC= 4.5V to 5.5V,

±

OSC Freq. Variation of 35%

External R/C OSC Freq Instr. Cycle (µs)

Capacitor (pF)*

(MHz)

0

9

5

2.0

2.5

TABLE 2. Crystal Oscillator Configuration,

T_A= 25˚C, V_CC= 5V

4

52

2

1

5.0

CKI Freq.

R1 (kΩ) R2 (MΩ)

C1 (pF)

C2 (pF)

125

6100

10

(MHz)

15

32 kHz

312.5

0

1

18

20

18

20

* Assumes 3-5 pF board capacitance.

10

0

25

4

5.6

100

100–156

0.455

5.10.2 External Oscillator

The External Oscillator mode can be selected by program-

ming ECON Bit 3 to 0 and ECON Bit 4 to 0. CKI can be

driven by an external clock signal provided it meets the

With On-Chip Bias Resistor

Without On-Chip Bias Resistor

10131717

10131718

FIGURE 12. Crystal Oscillator

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20

PSW Register (Address X'00EF)

5.0 Functional Description (Continued)

HC

C

T1PNDA T1ENA

EXPND

BUSY EXEN GIE

Bit 0

Bit 7

The PSW register contains the following select bits:

HC

C

Half Carry Flag

Carry Flag

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA

in mode 1, T1 Underflow in Mode 2, T1A capture

edge in mode 3)

T1ENA Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

10131719

EXPND External interrupt pending

BUSY

EXEN

GIE

MICROWIRE/PLUS busy shifting flag

Enable external interrupt

FIGURE 13. External Oscillator

Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that

affect the Carry flag. The SC (Set Carry) and R/C (Reset

Carry) instructions will respectively set or clear both the carry

flags. In addition to the SC and R/C instructions, ADC,

SUBC, RRC and RLC instructions affect the Carry and Half

Carry flags.

ICNTRL Register (Address X'00E8)

10131720

Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB

For operation at lower than maximum R/C oscillator frequency.

Bit 7

Bit 0

The ICNTRL register contains the following bits:

Reserved This bit is reserved and must be zero

LPEN

L

Port

Wakeup/Interrupt)

Timer T0 Interrupt pending

Timer T0 Interrupt Enable (Bit 12 toggle)

Interrupt

Enable

(Multi-Input

T0PND

T0EN

µWPND MICROWIRE/PLUS interrupt pending

µWEN Enable MICROWIRE/PLUS interrupt

10131721

T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-

ture edge

For operation at maximum R/C oscillator frequency.

T1ENB

Timer T1 Interrupt Enable for T1B Input capture

edge

FIGURE 14. R/C Oscillator

5.11 CONTROL REGISTERS

T2CNTRL Register (Address X'00C6)

CNTRL Register (Address X'00EE)

T2C3

Bit 7

T2C2

T2C1

T2C0

T2PNDA T2ENA T2PNDB T2ENB

Bit 0

T1C3 T1C2 T1C1 T1C0 MSEL IEDG

Bit 7

SL1

SL0

Bit 0

The T2CNTRL control register contains the following bits:

The Timer1 (T1) and MICROWIRE/PLUS control register

contains the following bits:

T2C3

T2C2

T2C1

T2C0

Timer T2 mode control bit

T1C3

T1C2

T1C1

T1C0

Timer T1 mode control bit

Timer T1 Start/Stop control in timer

Timer T2 Start/Stop control in timer

modes 1 and 2, T2 Underflow Interrupt Pend-

ing Flag in timer mode 3

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload

RA in mode 1, T2 Underflow in mode 2, T2A

capture edge in mode 3)

modes 1 and 2, T1 Underflow Interrupt

Pending Flag in timer mode 3

MSEL

IEDG

Selects G5 and G4 as MICROWIRE/PLUS

signals SK and SO respectively

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

External interrupt edge polarity select

(0 = Rising edge, 1 = Falling edge)

T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

by (00 = 2, 01 = 4, 1x = 8)

T2ENB

Timer T2 Interrupt Enable for Timer Underflow

or T2B Input capture edge

21

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The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

5.0 Functional Description (Continued)

T3CNTRL Register (Address X'00B6)

6.2.1 Mode 1. Processor Independent PWM Mode

T3C3

Bit 7

T3C2

T3C1

T3C0

T3PNDA T3ENA T3PNDB T3ENB

Bit 0

One of the timer’s operating modes is the Processor Inde-

pendent PWM mode. In this mode, the timer generates a

“Processor Independent” PWM signal because once the

timer is setup, no more action is required from the CPU

which translates to less software overhead and greater

throughput. The user software services the timer block only

when the PWM parameters require updating. This capability

is provided by the fact that the timer has two separate 16-bit

reload registers. One of the reload registers contains the

“ON” timer while the other holds the “OFF” time. By contrast,

a microcontroller that has only a single reload register re-

quires an additional software to update the reload value

(alternate between the on-time/off-time).

The T3CNTRL control register contains the following bits:

T3C3

T3C2

T3C1

T3C0

Timer T3 mode control bit

Timer T3 Start/Stop control in timer

modes 1 and 2, T3 Underflow Interrupt Pend-

ing Flag in timer mode 3

T3PNDA Timer T3 Interrupt Pending Flag (Autoreload

RA in mode 1, T3 Underflow in mode 2, T3A

capture edge in mode 3)

The timer can generate the PWM output with the width and

duty cycle controlled by the values stored in the reload

registers. The reload registers control the countdown values

and the reload values are automatically written into the timer

when it counts down through 0, generating interrupt on each

reload. Under software control and with minimal overhead,

the PMW outputs are useful in controlling motors, triacs, the

intensity of displays, and in providing inputs for data acqui-

sition and sine wave generators.

T3ENA

Timer T3 Interrupt Enable for Timer Underflow

or T3A Input capture edge

T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-

ture edge

T3ENB

Timer T3 Interrupt Enable for Timer Underflow

or T3B Input capture edge

6.0 Timers

Each device contains a very versatile set of timers (T0, T1,

T2 and T3). Timer T1, T2 and T3 and associated autoreload/

capture registers power up containing random data.

In this mode, the timer Tx counts down at a fixed rate of t_C.

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, RxA and RxB. The very

first underflow of the timer causes the timer to reload from

the register RxA. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

register RxB.

6.1 TIMER T0 (IDLE TIMER)

Each device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE timer T0. The Timer

T0 runs continuously at the fixed rate of the instruction cycle

clock, t_C. The user cannot read or write to the IDLE Timer T0,

which is a count down timer.

Figure 15 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the TxA output

pin. The underflows can also be programmed to generate

interrupts.

The Timer T0 supports the following functions:

Underflows from the timer are alternately latched into two

pending flags, TxPNDA and TxPNDB. The user must reset

these pending flags under software control. Two control

enable flags, TxENA and TxENB, allow the interrupts from

the timer underflow to be enabled or disabled. Setting the

timer enable flag TxENA will cause an interrupt when a timer

underflow causes the RxA register to be reloaded into the

timer. Setting the timer enable flag TxENB will cause an

interrupt when a timer underflow causes the RxB register to

be reloaded into the timer. Resetting the timer enable flags

will disable the associated interrupts.

•

Exit out of the Idle Mode (See Idle Mode description)

WATCHDOG logic (See WATCHDOG description)

Start up delay out of the HALT mode

Timing the width of the internal power-on-reset

The IDLE Timer T0 can generate an interrupt when the

twelfth bit toggles. This toggle is latched into the T0PND

pending flag, and will occur every 2.731 ms at the maximum

clock frequency (t_C= 0.67 µs). A control flag T0EN allows the

interrupt from the twelfth bit of Timer T0 to be enabled or

disabled. Setting T0EN will enable the interrupt, while reset-

ting it will disable the interrupt.

Either or both of the timer underflow interrupts may be

enabled. This gives the user the flexibility of interrupting

once per PWM period on either the rising or falling edge of

the PWM output. Alternatively, the user may choose to inter-

rupt on both edges of the PWM output.

6.2 TIMER T1, TIMER T2 and TIMER T3

Each device have a set of three powerful timer/counter

blocks, T1, T2 and T3. Since T1, T2, and T3 are identical, all

comments are equally applicable to any of the three timer

blocks which will be referred to as Tx.

6.2.2 Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin. The

Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to

be clocked either on a positive or negative edge from the

TxA pin. Underflows from the timer are latched into the

TxPNDA pending flag. Setting the TxENA control flag will

cause an interrupt when the timer underflows.

Each timer block consists of a 16-bit timer, Tx, and two

supporting 16-bit autoreload/capture registers, RxA and

RxB. Each timer block has two pins associated with it, TxA

and TxB. The pin TxA supports I/O required by the timer

block, while the pin TxB is an input to the timer block. The

timer block has three operating modes: Processor Indepen-

dent PWM mode, External Event Counter mode, and Input

Capture mode.

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22

value when the external event occurs, the time of the exter-

nal event is recorded. Most microcontrollers have a latency

time because they cannot determine the timer value when

the external event occurs. The capture register eliminates

the latency time, thereby allowing the applications program

to retrieve the timer value stored in the capture register.

6.0 Timers (Continued)

In this mode, the timer Tx is constantly running at the fixed t_C

rate. The two registers, RxA and RxB, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

RxA acts in conjunction with the TxA pin and the register RxB

acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

TxC3, TxC2 and TxC1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger

condition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively latched into the

pending flags, TxPNDA and TxPNDB. The control flag Tx-

ENA allows the interrupt on TxA to be either enabled or

disabled. Setting the TxENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

TxA pin. Similarly, the flag TxENB controls the interrupts

from the TxB pin.

10131746

FIGURE 15. Timer in PWM Mode

In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB

control flag is set. The occurrence of a positive edge on the

TxB input pin is latched into the TxPNDB flag.

Figure 16 shows a block diagram of the timer in External

Event Counter mode.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the TxC0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the TxENA control flag. When a TxA interrupt

occurs in the Input Capture mode, the user must check both

the TxPNDA and TxC0 pending flags in order to determine

whether a TxA input capture or a timer underflow (or both)

caused the interrupt.

Note: The PWM output is not available in this mode since the TxA pin is being

used as the counter input clock.

Figure 17 shows a block diagram of the timer T1 in Input

Capture mode. Timer T2 and T3 are identical to T1.

10131747

FIGURE 16. Timer in External Event Counter Mode

6.2.3 Mode 3. Input Capture Mode

Each device can precisely measure external frequencies or

time external events by placing the timer block, Tx, in the

input capture mode. In this mode, the reload registers serve

as independent capture registers, capturing the contents of

the timer when an external event occurs (transition on the

timer input pin). The capture registers can be read while

maintaining count, a feature that lets the user measure

elapsed time and time between events. By saving the timer

10131748

FIGURE 17. Timer in Input Capture Mode

23

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TxPNDA Timer Interrupt Pending Flag

TxENA Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

6.0 Timers (Continued)

6.3 TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

0 = Timer Interrupt Disabled

TxC3

TxC2

TxC1

TxC0

Timer mode control

TxPNDB Timer Interrupt Pending Flag

TxENB Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

0 = Timer Interrupt Disabled

The timer mode control bits (TxC3, TxC2 and TxC1) are

detailed below:

Timer Underflow Interrupt Pending Flag in Mode

3 (Input Capture)

Interrupt A

Source

Interrupt B

Source

Timer

Mode

TxC3

TxC2

TxC1

Description

Counts On

1

0

1

0

PWM: TxA Toggle

PWM: No TxA

Toggle

Autoreload RA

Autoreload RB

t_C

1

t_C

0

1

0

1

0

External Event

Counter

Timer Underflow Pos. TxB Edge

Pos. TxA

Edge

2

External Event

Counter

Pos. TxA

Edge

Captures:

Pos. TxA Edge

or Timer

Pos. TxB Edge

t_C

TxA Pos. Edge

TxB Pos. Edge

Captures:

Underflow

1

0

1

0

1

Pos. TxA

Neg. TxB

Edge

t_C

TxA Pos. Edge

TxB Neg. Edge

Captures:

Edge or Timer

Underflow

3

Neg. TxA

Neg. TxB

Edge

TxA Neg. Edge

TxB Neg. Edge

Captures:

Edge or Timer

Underflow

Neg. TxA

Neg. TxB

Edge

TxA Neg. Edge

TxB Neg. Edge

Edge or Timer

Underflow

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24

On wakeup from G7 or Port L, the devices resume execution

from the HALT point. On wakeup from RESET execution will

resume from location PC=0 and all RESET conditions apply.

7.0 Power Saving Features

Today, the proliferation of battery-operated based applica-

tions has placed new demands on designers to drive power

consumption down. Battery-operated systems are not the

only type of applications demanding low power. The power

budget constraints are also imposed on those consumer/

industrial applications where well regulated and expensive

power supply costs cannot be tolerated. Such applications

rely on low cost and low power supply voltage derived di-

rectly from the “mains” by using voltage rectifier and passive

components. Low power is demanded even in automotive

applications, due to increased vehicle electronics content.

This is required to ease the burden from the car battery. Low

power 8-bit microcontrollers supply the smarts to control

battery-operated, consumer/industrial, and automotive appli-

cations.

If a crystal or ceramic resonator may be selected as the

oscillator, the Wakeup signal is not allowed to start the chip

running immediately since crystal oscillators and ceramic

resonators have a delayed start up time to reach full ampli-

tude and frequency stability. The IDLE timer is used to

generate a fixed delay to ensure that the oscillator has

indeed stabilized before allowing instruction execution. In

this case, upon detecting a valid Wakeup signal, only the

oscillator circuitry is enabled. The IDLE timer is loaded with

a value of 256 and is clocked with the t_Cinstruction cycle

clock. The t_Cclock is derived by dividing the oscillator clock

down by a factor of 9. The Schmitt trigger following the CKI

inverter on the chip ensures that the IDLE timer is clocked

only when the oscillator has a sufficiently large amplitude to

meet the Schmitt trigger specifications. This Schmitt trigger

is not part of the oscillator closed loop. The start-up time-out

from the IDLE timer enables the clock signals to be routed to

the rest of the chip.

Each device offers system designers a variety of low-power

consumption features that enable them to meet the demand-

ing requirements of today’s increasing range of low-power

applications. These features include low voltage operation,

low current drain, and power saving features such as HALT,

IDLE, and Multi-Input wakeup (MIWU).

If an R/C clock option is being used, the fixed delay is

introduced optionally. A control bit, CLKDLY, mapped as

configuration bit G7, controls whether the delay is to be

introduced or not. The delay is included if CLKDLY is set,

and excluded if CLKDLY is reset. The CLKDLY bit is cleared

on reset.

Each device offers the user two power save modes of op-

eration: HALT and IDLE. In the HALT mode, all microcontrol-

ler activities are stopped. In the IDLE mode, the on-board

oscillator circuitry and timer T0 are active but all other micro-

controller activities are stopped. In either mode, all on-board

RAM, registers, I/O states, and timers (with the exception of

T0) are unaltered.

Each device has two options associated with the HALT

mode. The first option enables the HALT mode feature, while

the second option disables the HALT mode selected through

bit 0 of the ECON register. With the HALT mode enable

option, the device will enter and exit the HALT mode as

described above. With the HALT disable option, the device

cannot be placed in the HALT mode (writing a “1” to the

HALT flag will have no effect, the HALT flag will remain “0”).

Clock Monitor, if enabled, can be active in both modes.

7.1 HALT MODE

Each device can be placed in the HALT mode by writing a “1”

to the HALT flag (G7 data bit). All microcontroller activities,

including the clock and timers, are stopped. The WATCH-

DOG logic on the devices are disabled during the HALT

mode. However, the clock monitor circuitry, if enabled, re-

mains active and will cause the WATCHDOG output pin

(WDOUT) to go low. If the HALT mode is used and the user

does not want to activate the WDOUT pin, the Clock Monitor

should be disabled after the devices come out of reset

(resetting the Clock Monitor control bit with the first write to

the WDSVR register). In the HALT mode, the power require-

ments of the devices are minimal and the applied voltage

(V_CC) may be decreased to V_r(V_r= 2.0V) without altering the

state of the machine.

The WATCHDOG detector circuit is inhibited during the

HALT mode. However, the clock monitor circuit if enabled

remains active during HALT mode in order to ensure a clock

monitor error if the device inadvertently enters the HALT

mode as a result of a runaway program or power glitch.

If the device is placed in the HALT mode, with the R/C

oscillator selected, the clock input pin (CKI) is forced to a

logic high internally. With the crystal or external oscillator the

CKI pin is TRI-STATE.

It is recommended that the user not halt the device by merely

stopping the clock in external oscillator mode. If this method

is used, there is a possibility of greater than specified HALT

current.

Each device supports three different ways of exiting the

HALT mode. The first method of exiting the HALT mode is

with the Multi-Input Wakeup feature on Port L. The second

method is with a low to high transition on the CKO (G7) pin.

This method precludes the use of the crystal clock configu-

ration (since CKO becomes a dedicated output), and so may

only be used with an R/C clock configuration. The third

method of exiting the HALT mode is by pulling the RESET

pin low.

If the user wishes to stop an external clock, it is recom-

mended that the CPU be halted by setting the Halt flag first

and the clock be stopped only after the CPU has halted.

25

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7.0 Power Saving Features (Continued)

10131725

FIGURE 18. Wakeup from HALT

7.2 IDLE MODE

The user can enter the IDLE mode with the Timer T0 inter-

rupt enabled. In this case, when the T0PND bit gets set, the

device will first execute the Timer T0 interrupt service routine

and then return to the instruction following the “Enter Idle

Mode” instruction.

The device is placed in the IDLE mode by writing a “1” to the

IDLE flag (G6 data bit). In this mode, all activities, except the

associated on-board oscillator circuitry and the IDLE Timer

T0, are stopped.

Alternatively, the user can enter the IDLE mode with the

IDLE Timer T0 interrupt disabled. In this case, the device will

resume normal operation with the instruction immediately

following the “Enter IDLE Mode” instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions

are necessary to allow clock resynchronization following the HALT or

IDLE modes.

As with the HALT mode, the device can be returned to

normal operation with a reset, or with a Multi-Input Wakeup

from the L Port. Alternately, the microcontroller resumes

normal operation from the IDLE mode when the twelfth bit

(representing 4.096 ms at internal clock frequency of

10 MHz, t_C= 1 µs) of the IDLE Timer toggles.

This toggle condition of the twelfth bit of the IDLE Timer T0 is

latched into the T0PND pending flag.

The user has the option of being interrupted with a transition

on the twelfth bit of the IDLE Timer T0. The interrupt can be

enabled or disabled via the T0EN control bit. Setting the

T0EN flag enables the interrupt and vice versa.

10131726

FIGURE 19. Wakeup from IDLE

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26

to negative (high going low) for L Port bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

7.0 Power Saving Features (Continued)

7.3 MULTI-INPUT WAKEUP

The Multi-Input Wakeup feature is used to return (wakeup)

the device from either the HALT or IDLE modes. Alternately

Multi-Input Wakeup/Interrupt feature may also be used to

generate up to 8 edge selectable external interrupts.

RBIT 5, WKEN

SBIT 5, WKEDG ; Change edge polarity

RBIT 5, WKPND ; Reset pending flag

; Disable MIWU

SBIT 5, WKEN

; Enable MIWU

Figure 20 shows the Multi-Input Wakeup logic.

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid wakeup condi-

tions. After the selected L port bits have been changed from

output to input but before the associated WKEN bits are

enabled, the associated edge select bits in WKEDG should

be set or reset for the desired edge selects, followed by the

associated WKPND bits being cleared.

The Multi-Input Wakeup feature utilizes the L Port. The user

selects which particular L port bit (or combination of L Port

bits) will cause the device to exit the HALT or IDLE modes.

The selection is done through the register WKEN. The reg-

ister WKEN is an 8-bit read/write register, which contains a

control bit for every L port bit. Setting a particular WKEN bit

enables a Wakeup from the associated L port pin.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The user can select whether the trigger condition on the

selected L Port pin is going to be either a positive edge (low

to high transition) or a negative edge (high to low transition).

This selection is made via the register WKEDG, which is an

8-bit control register with a bit assigned to each L Port pin.

Setting the control bit will select the trigger condition to be a

negative edge on that particular L Port pin. Resetting the bit

selects the trigger condition to be a positive edge. Changing

an edge select entails several steps in order to avoid a

Wakeup condition as a result of the edge change. First, the

associated WKEN bit should be reset, followed by the edge

select change in WKEDG. Next, the associated WKPND bit

should be cleared, followed by the associated WKEN bit

being re-enabled.

The occurrence of the selected trigger condition for Multi-

Input Wakeup is latched into a pending register called WK-

PND. The respective bits of the WKPND register will be set

on the occurrence of the selected trigger edge on the corre-

sponding Port L pin. The user has the responsibility of clear-

ing these pending flags. Since WKPND is a pending register

for the occurrence of selected wakeup conditions, the device

will not enter the HALT mode if any Wakeup bit is both

enabled and pending. Consequently, the user must clear the

pending flags before attempting to enter the HALT mode.

WKEN and WKEDG are all read/write registers, and are

cleared at reset. WKPND register contains random value

after reset.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

10131727

FIGURE 20. Multi-Input Wake Up Logic

27

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Other functions of the ENUR register include saving the

ninth bit received in the data frame, enabling or disabling the

USART’s attention mode of operation and providing addi-

tional receiver/transmitter status information via RCVG and

XMTG bits. The determination of an internal or external clock

source is done by the ENUI register, as well as selecting the

number of stop bits and enabling or disabling transmit and

receive interrupts. A control flag in this register can also

select the USART mode of operation: asynchronous or

synchronous.

8.0 USART

Each device contains a full-duplex software programmable

USART. The USART (Figure 21) consists of a transmit shift

register, a receive shift register and seven addressable reg-

isters, as follows: a transmit buffer register (TBUF), a re-

ceiver buffer register (RBUF), a USART control and status

register (ENU), a USART receive control and status register

(ENUR), a USART interrupt and clock source register

(ENUI), a prescaler select register (PSR) and baud (BAUD)

register. The ENU register contains flags for transmit and

receive functions; this register also determines the length of

the data frame (7, 8 or 9 bits), the value of the ninth bit in

transmission, and parity selection bits. The ENUR register

flags framing, data overrun and parity errors while the US-

ART is receiving.

10131739

FIGURE 21. USART Block Diagram

8.1 USART CONTROL AND STATUS REGISTERS

8.2 DESCRIPTION OF USART REGISTER BITS

The operation of the USART is programmed through three

registers: ENU, ENUR and ENUI.

ENU-USART Control and Status Register (Address at 0BA)

PEN PSEL1 XBIT9/ CHL1 CHL0

PSEL0

ERR

RBFL TBMT

Bit 7

Bit 0

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28

the last time the ENUR register was read.

Indicates the occurrence of a Parity Error.

8.0 USART (Continued)

PE = 1

PEN: This bit enables/disables Parity (7- and 8-bit modes

only). Read/Write, cleared on reset.

SPARE: Reserved for future use. Read/Write, cleared on

reset.

PEN = 0

PEN = 1

Parity disabled.

Parity enabled.

RBIT9: Contains the ninth data bit received when the US-

ART is operating with nine data bits per frame. Read only,

cleared on reset.

PSEL1, PSEL0: Parity select bits. Read/Write, cleared on

reset.

ATTN: ATTENTION Mode is enabled while this bit is set.

This bit is cleared automatically on receiving a character with

data bit nine set. Read/Write, cleared on reset.

PSEL1 = 0, PSEL0 = 0

PSEL1 = 0, PSEL0 = 1

PSEL1 = 1, PSEL0 = 0

PSEL1 = 1, PSEL0 = 1

Odd Parity (if Parity enabled)

Even Parity (if Parity enabled)

Mark(1) (if Parity enabled)

Space(0) (if Parity enabled)

XMTG: This bit is set to indicate that the USART is transmit-

ting. It gets reset at the end of the last frame (end of last Stop

bit). Read only, cleared on reset.

XBIT9/PSEL0: Programs the ninth bit for transmission when

the USART is operating with nine data bits per frame. For

seven or eight data bits per frame, this bit in conjunction with

PSEL1 selects parity. Read/Write, cleared on reset.

RCVG: This bit is set high whenever a framing error occurs

and goes low when RDX goes high. Read only, cleared on

reset.

ENUI-USART Interrupt and Clock Source Register

(Address at 0BC)

CHL1, CHL0: These bits select the character frame format.

Parity is not included and is generated/verified by hardware.

Read/Write, cleared on reset.

STP2 STP78 ETDX SSEL XRCLK XTCLK ERI

Bit 7

ETI

CHL1 = 0, CHL0 = 0

CHL1 = 0, CHL0 = 1

CHL1 = 1, CHL0 = 0

CHL1 = 1, CHL0 = 1

The frame contains eight data bits.

The frame contains seven data bits.

The frame contains nine data bits.

Bit 0

STP2: This bit programs the number of Stop bits to be

transmitted. Read/Write, cleared on reset.

Loopback Mode selected. Trans-

mitter output internally looped back

to receiver input. Nine bit framing

format is used.

STP2 = 0

STP2 = 1

One Stop bit transmitted.

Two Stop bits transmitted.

STP78: This bit is set to program the last Stop bit to be 7/8th

of a bit in length. Read/Write, cleared on reset.

ERR: This bit is a global USART error flag which gets set if

any or a combination of the errors (DOE, FE, PE) occur.

Read only; it cannot be written by software, cleared on reset.

ETDX: TDX (USART Transmit Pin) is the alternate function

assigned to Port L pin L2; it is selected by setting ETDX bit.

To simulate line break generation, software should reset

ETDX bit and output logic zero to TDX pin through Port L

data and configuration registers. Read/Write, cleared on

reset.

RBFL: This bit is set when the USART has received a

complete character and has copied it into the RBUF register.

It is automatically reset when software reads the character

from RBUF. Read only; it cannot be written by software,

cleared on reset.

SSEL: USART mode select. Read/Write, cleared on reset.

TBMT: This bit is set when the USART transfers a byte of

data from the TBUF register into the TSFT register for trans-

mission. It is automatically reset when software writes into

the TBUF register. Read only, bit is set to “one” on reset; it

cannot be written by software.

SSEL = 0

SSEL = 1

Asynchronous Mode.

Synchronous Mode.

XRCLK: This bit selects the clock source for the receiver

section. Read/Write, cleared on reset.

XRCLK = 0

The clock source is selected through the

PSR and BAUD registers.

ENUR-USART Receive Control and Status Register

(Address at 0BB)

XRCLK = 1

Signal on CKX (L1) pin is used as the clock.

DOE

FE

PE

Reserved RBIT9 ATTN XMTG RCVG

XTCLK: This bit selects the clock source for the transmitter

(Note 16)

section. Read/Write, cleared on reset.

Bit 7

Bit 0

XTCLK = 0

The clock source is selected through the PSR

and BAUD registers.

Note 16: Bit is reserved for future use. User must set to zero.

XTCLK = 1

Signal on CKX (L1) pin is used as the clock.

DOE: Flags a Data Overrun Error. Read only, cleared on

read, cleared on reset.

ERI: This bit enables/disables interrupt from the receiver

section. Read/Write, cleared on reset.

DOE = 0

Indicates no Data Overrun Error has been de-

tected since the last time the ENUR register

was read.

ERI = 0

ERI = 1

Interrupt from the receiver is disabled.

Interrupt from the receiver is enabled.

DOE = 1

Indicates the occurrence of a Data Overrun

Error.

ETI: This bit enables/disables interrupt from the transmitter

section. Read/Write, cleared on reset.

ETI = 0

ETI = 1

Interrupt from the transmitter is disabled.

Interrupt from the transmitter is enabled.

FE: Flags a Framing Error. Read only, cleared on read,

cleared on reset.

FE = 0

Indicates no Framing Error has been detected

since the last time the ENUR register was read.

FE = 1

Indicates the occurrence of a Framing Error.

PE: Flags a Parity Error. Read only, cleared on read, cleared

on reset.

PE = 0

Indicates no Parity Error has been detected since

29

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This mode is selected by setting SSEL bit in the ENUI

register. The input frequency to the USART is the same as

the baud rate.

8.0 USART (Continued)

8.3 Associated I/O Pins

Data is transmitted on the TDX pin and received on the RDX

pin. TDX is the alternate function assigned to Port L pin L2;

it is selected by setting ETDX (in the ENUI register) to one.

RDX is an inherent function of Port L pin L3, requiring no

setup.

When an external clock input is selected at the CKX pin, data

transmit and receive are performed synchronously with this

clock through TDX/RDX pins.

If data transmit and receive are selected with the CKX pin as

clock output, the device generates the synchronous clock

output at the CKX pin. The internal baud rate generator is

used to produce the synchronous clock. Data transmit and

receive are performed synchronously with this clock.

The baud rate clock for the USART can be generated on-

chip, or can be taken from an external source. Port L pin L1

(CKX) is the external clock I/O pin. The CKX pin can be

either an input or an output, as determined by Port L Con-

figuration and Data registers (Bit 1). As an input, it accepts a

clock signal which may be selected to drive the transmitter

and/or receiver. As an output, it presents the internal Baud

Rate Generator output.

8.5 FRAMING FORMATS

The USART supports several serial framing formats (Figure

22). The format is selected using control bits in the ENU,

ENUR and ENUI registers.

The first format (1, 1a, 1b, 1c) for data transmission (CHL0 =

1, CHL1 = 0) consists of Start bit, seven Data bits (excluding

parity) and 7/8, one or two Stop bits. In applications using

parity, the parity bit is generated and verified by hardware.

8.4 USART Operation

The USART has two modes of operation: asynchronous

mode and synchronous mode.

The second format (CHL0 = 0, CHL1 = 0) consists of one

Start bit, eight Data bits (excluding parity) and 7/8, one or

two Stop bits. Parity bit is generated and verified by hard-

ware.

8.4.1 ASYNCHRONOUS MODE

This mode is selected by resetting the SSEL (in the ENUI

register) bit to zero. The input frequency to the USART is 16

times the baud rate.

The third format for transmission (CHL0 = 0, CHL1 = 1)

consists of one Start bit, nine Data bits and 7/8, one or two

Stop bits. This format also supports the USART “ATTEN-

TION” feature. When operating in this format, all eight bits of

TBUF and RBUF are used for data. The ninth data bit is

transmitted and received using two bits in the ENU and

ENUR registers, called XBIT9 and RBIT9. RBIT9 is a read

only bit. Parity is not generated or verified in this mode.

The TSFT and TBUF registers double-buffer data for trans-

mission. While TSFT is shifting out the current character on

the TDX pin, the TBUF register may be loaded by software

with the next byte to be transmitted. When TSFT finishes

transmitting the current character the contents of TBUF are

transferred to the TSFT register and the Transmit Buffer

Empty Flag (TBMT in the ENU register) is set. The TBMT

flag is automatically reset by the USART when software

loads a new character into the TBUF register. There is also

the XMTG bit which is set to indicate that the USART is

transmitting. This bit gets reset at the end of the last frame

(end of last Stop bit). TBUF is a read/write register.

For any of the above framing formats, the last Stop bit can

be programmed to be 7/8th of a bit in length. If two Stop bits

are selected and the 7/8th bit is set (selected), the second

Stop bit will be 7/8th of a bit in length.

The parity is enabled/disabled by PEN bit located in the ENU

register. Parity is selected for 7- and 8-bit modes only. If

parity is enabled (PEN = 1), the parity selection is then

performed by PSEL0 and PSEL1 bits located in the ENU

register.

The RSFT and RBUF registers double-buffer data being

received. The USART receiver continually monitors the sig-

nal on the RDX pin for a low level to detect the beginning of

a Start bit. Upon sensing this low level, it waits for half a bit

time and samples again. If the RDX pin is still low, the

receiver considers this to be a valid Start bit, and the remain-

ing bits in the character frame are each sampled a single

time, at the mid-bit position. Serial data input on the RDX pin

is shifted into the RSFT register. Upon receiving the com-

plete character, the contents of the RSFT register are copied

into the RBUF register and the Received Buffer Full Flag

(RBFL) is set. RBFL is automatically reset when software

reads the character from the RBUF register. RBUF is a read

only register. There is also the RCVG bit which is set high

when a framing error occurs and goes low once RDX goes

high. TBMT, XMTG, RBFL and RCVG are read only bits.

Note that the XBIT9/PSEL0 bit located in the ENU register

serves two mutually exclusive functions. This bit programs

the ninth bit for transmission when the USART is operating

with nine data bits per frame. There is no parity selection in

this framing format. For other framing formats XBIT9 is not

needed and the bit is PSEL0 used in conjunction with PSEL1

to select parity.

The frame formats for the receiver differ from the transmitter

in the number of Stop bits required. The receiver only re-

quires one Stop bit in a frame, regardless of the setting of the

Stop bit selection bits in the control register. Note that an

implicit assumption is made for full duplex USART operation

that the framing formats are the same for the transmitter and

receiver.

8.4.2 SYNCHRONOUS MODE

In this mode data is transferred synchronously with the

clock. Data is transmitted on the rising edge and received on

the falling edge of the synchronous clock.

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30

8.0 USART (Continued)

10131740

FIGURE 22. Framing Formats

8.6 USART INTERRUPTS

source selected in the PSR and BAUD registers. Internally,

the basic baud clock is created from the oscillator frequency

through a two-stage divider chain consisting of a 1–16 (in-

crements of 0.5) prescaler and an 11-bit binary counter.

(Figure 23). The divide factors are specified through two

read/write registers shown in Figure 24. Note that the 11-bit

Baud Rate Divisor spills over into the Prescaler Select Reg-

ister (PSR). PSR is cleared upon reset.

The USART is capable of generating interrupts. Interrupts

are generated on Receive Buffer Full and Transmit Buffer

Empty. Both interrupts have individual interrupt vectors. Two

bytes of program memory space are reserved for each in-

terrupt vector. The two vectors are located at addresses

0xEC to 0xEF Hex in the program memory space. The

interrupts can be individually enabled or disabled using En-

able Transmit Interrupt (ETI) and Enable Receive Interrupt

(ERI) bits in the ENUI register.

As shown in Table 5, a Prescaler Factor of 0 corresponds to

NO CLOCK. This condition is the USART power down mode

where the USART clock is turned off for power saving pur-

pose. The user must also turn the USART clock off when a

different baud rate is chosen.

The interrupt from the Transmitter is set pending, and re-

mains pending, as long as both the TBMT and ETI bits are

set. To remove this interrupt, software must either clear the

ETI bit or write to the TBUF register (thus clearing the TBMT

bit).

The correspondences between the 5-bit Prescaler Select

and Prescaler factors are shown in Table 5. There are many

ways to calculate the two divisor factors, but one particularly

effective method would be to achieve a 1.8432 MHz fre-

quency coming out of the first stage. The 1.8432 MHz pres-

caler output is then used to drive the software programmable

baud rate counter to create a 16x clock for the following baud

rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600,

4800, 7200, 9600, 19200 and 38400 (Table 4). Other baud

The interrupt from the receiver is set pending, and remains

pending, as long as both the RBFL and ERI bits are set. To

remove this interrupt, software must either clear the ERI bit

or read from the RBUF register (thus clearing the RBFL bit).

8.7 Baud Clock Generation

The clock inputs to the transmitter and receiver sections of

the USART can be individually selected to come either from

an external source at the CKX pin (port L, pin L1) or from a

31

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8.0 USART (Continued)

rates may be created by using appropriate divisors. The 16x

clock is then divided by 16 to provide the rate for the serial

shift registers of the transmitter and receiver.

10131741

FIGURE 23. USART BAUD Clock Generation

10131742

FIGURE 24. USART BAUD Clock Divisor Registers

TABLE 4. Baud Rate Divisors

(1.8432 MHz Prescaler Output)

Prescaler

Select

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Prescaler

Factor

2.5

3

Baud

Rate

Baud Rate

Divisor − 1

(N-1)

3.5

4

110 (110.03)

134.5

(134.58)

150

1046

855

4.5

5

767

383

191

95

63

47

31

23

15

11

5.5

6

300

600

6.5

7

1200

1800

7.5

8

2400

3600

8.5

9

4800

7200

9.5

10

9600

19200

38400

5

10.5

11

2

Note: The entries in Table 4 assume a prescaler output of 1.8432 MHz. In the

11.5

12

asynchronous mode the baud rate could be as high as 987.5k.

12.5

13

TABLE 5. Prescaler Factors

Prescaler

Select

00000

Prescaler

13.5

14

Factor

NO CLOCK

14.5

15

00001

1

1.5

2

00010

15.5

16

00011

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32

because of the finite start up time requirement of the crystal

oscillator. The idle timer (T0) generates a fixed (256 t_c) delay

to ensure that the oscillator has indeed stabilized before

allowing the device to execute code. The user has to con-

sider this delay when data transfer is expected immediately

after exiting the HALT mode.

8.0 USART (Continued)

As an example, considering Asynchronous Mode and a CKI

clock of 4.608 MHz, the prescaler factor selected is:

4.608/1.8432 = 2.5

The 2.5 entry is available in Table 5. The 1.8432 MHz

prescaler output is then used with proper Baud Rate Divisor

(Table 4) to obtain different baud rates. For a baud rate of

19200 e.g., the entry in Table 4 is 5.

8.9 Diagnostic

Bits CHARL0 and CHARL1 in the ENU register provide a

loopback feature for diagnostic testing of the USART. When

these bits are set to one, the following occur: The receiver

input pin (RDX) is internally connected to the transmitter

output pin (TDX); the output of the Transmitter Shift Register

is “looped back” into the Receive Shift Register input. In this

mode, data that is transmitted is immediately received. This

feature allows the processor to verify the transmit and re-

ceive data paths of the USART.

N − 1 = 5 (N − 1 is the value from Table 4)

N = 6 (N is the Baud Rate Divisor)

Baud Rate = 1.8432 MHz/(16 x 6) = 19200

The divide by 16 is performed because in the asynchronous

mode, the input frequency to the USART is 16 times the

baud rate. The equation to calculate baud rates is given

below.

Note that the framing format for this mode is the nine bit

format; one Start bit, nine data bits, and 7/8, one or two Stop

bits. Parity is not generated or verified in this mode.

The actual Baud Rate may be found from:

BR = Fc/(16 x N x P)

Where:

BR is the Baud Rate

8.10 Attention Mode

Fc is the CKI frequency

N is the Baud Rate Divisor (Table 4).

The USART Receiver section supports an alternate mode of

operation, referred to as ATTENTION Mode. This mode of

operation is selected by the ATTN bit in the ENUR register.

The data format for transmission must also be selected as

having nine Data bits and either 7/8, one or two Stop bits.

P is the Prescaler Divide Factor selected by the value in the

Prescaler Select Register (Table 5)

Note: In the Synchronous Mode, the divisor 16 is replaced by two.

The ATTENTION mode of operation is intended for use in

networking the device with other processors. Typically in

such environments the messages consists of device ad-

dresses, indicating which of several destinations should re-

ceive them, and the actual data. This Mode supports a

scheme in which addresses are flagged by having the ninth

bit of the data field set to a 1. If the ninth bit is reset to a zero

the byte is a Data byte.

Example:

Asynchronous Mode:

Crystal Frequency = 5 MHz

Desired baud rate = 9600

Using the above equation N x P can be calculated first.

N x P = (5 x 10⁶)/(16 x 9600) = 32.552

Now 32.552 is divided by each Prescaler Factor (Table 5) to

obtain a value closest to an integer. This factor happens to

be 6.5 (P = 6.5).

While in ATTENTION mode, the USART monitors the com-

munication flow, but ignores all characters until an address

character is received. Upon receiving an address character,

the USART signals that the character is ready by setting the

RBFL flag, which in turn interrupts the processor if USART

Receiver interrupts are enabled. The ATTN bit is also cleared

automatically at this point, so that data characters as well as

address characters are recognized. Software examines the

contents of the RBUF and responds by deciding either to

accept the subsequent data stream (by leaving the ATTN bit

reset) or to wait until the next address character is seen (by

setting the ATTN bit again).

N = 32.552/6.5 = 5.008 (N = 5)

The programmed value (from Table 4) should be 4 (N − 1).

Using the above values calculated for N and P:

BR = (5 x 10⁶)/(16 x 5 x 6.5) = 9615.384

% error = (9615.385 − 9600)/9600 x 100 = 0.16%

8.8 Effect of HALT/IDLE

The USART logic is reinitialized when either the HALT or

IDLE modes are entered. This reinitialization sets the TBMT

flag and resets all read only bits in the USART control and

status registers. Read/Write bits remain unchanged. The

Transmit Buffer (TBUF) is not affected, but the Transmit Shift

register (TSFT) bits are set to one. The receiver registers

RBUF and RSFT are not affected.

Operation of the USART Transmitter is not affected by se-

lection of this Mode. The value of the ninth bit to be trans-

mitted is programmed by setting XBIT9 appropriately. The

value of the ninth bit received is obtained by reading RBIT9.

Since this bit is located in ENUR register where the error

flags reside, a bit operation on it will reset the error flags.

The device will exit from the HALT/IDLE modes when the

Start bit of a character is detected at the RDX (L3) pin. This

feature is obtained by using the Multi-Input Wakeup scheme

provided on the device.

9.0 Comparators

The device contains two differential comparators, each with

a pair of inputs (positive and negative) and an output. Ports

F1–F3 and F4–F6 are used for the comparators. The follow-

ing is the Port F assignment:

Before entering the HALT or IDLE modes the user program

must select the Wakeup source to be on the RDX pin. This

selection is done by setting bit 3 of WKEN (Wakeup Enable)

register. The Wakeup trigger condition is then selected to be

high to low transition. This is done via the WKEDG register

(Bit 3 is one.)

F6 Comparator2 output

F5 Comparator2 positive input

F4 Comparator2 negative input

F3 Comparator1 output

If the device is halted and crystal oscillator is used, the

Wakeup signal will not start the chip running immediately

F2 Comparator1 positive input

33

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will read as zero if the associated comparator is not enabled.

The Comparator Select Register is cleared with reset, result-

ing in the comparators being disabled. The comparators

should also be disabled before entering either the HALT or

IDLE modes in order to save power. The configuration of the

CMPSL register is as follows:

9.0 Comparators (Continued)

F1 Comparator1 negative input

A Comparator Select Register (CMPSL) is used to enable

the comparators, read the outputs of the comparators inter-

nally, and enable the outputs of the comparators to the pins.

Two control bits (enable and output enable) and one result

bit are associated with each comparator. The comparator

result bits (CMP1RD and CMP2RD) are read only bits which

CMPSL REGISTER (ADDRESS X’00B7)

Reserved

Bit 7

CMP20E

CMP2RD

CMP2EN

CMP10E

CMP1RD

CMP1EN

Reserved

Bit 0

Note: For compatibility with existing code and with existing Mask ROMMed

devices the bits of the CMPSL register will take precedence over the

associated Port F configuration and data output bits.

The CMPSL register contains the following bits:

Reserved These bits are reserved and must be zero

CMP20E Selects pin I6 as comparator 2 output provided

that CMP2EN is set to enable the comparator

10.0 Interrupts

CMP2RD Comparator 2 result (this is a read only bit, which

will read as 0 if the comparator is not enabled)

10.1 INTRODUCTION

CMP2EN Enable comparator 2

Each device supports thirteen vectored interrupts. Interrupt

sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L

Wakeup, Software Trap, MICROWIRE/PLUS, and External

Input.

CMP10E Selects pin I3 as comparator 1 output provided

that CMPIEN is set to enable the comparator

CMP1RD Comparator 1 result (this is a read only bit, which

will read as 0 if the comparator is not enabled)

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

CMP1EN Enable comparator 1

Note that the two unused bits of CMPSL may be used as

software flags.

The Software trap has the highest priority while the default

VIS has the lowest priority.

Note: If the user attempts to use the comparator output

immediately after enabling the comparator, an incorrect

value may be read. At least one instruction cycle should pass

between these operations. The use of a direct addressing

mode instruction for either of these two operations will guar-

antee this delay in the software.

Each of the 13 maskable inputs has a fixed arbitration rank-

ing and vector.

Figure 25 shows the Interrupt Block Diagram.

10131728

FIGURE 25. Interrupt Block Diagram

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34

interrupt, and jump to the interrupt handling routine corre-

sponding to the highest priority enabled and active interrupt.

Alternately, the user may choose to poll all interrupt pending

and enable bits to determine the source(s) of the interrupt. If

more than one interrupt is active, the user’s program must

decide which interrupt to service.

10.0 Interrupts (Continued)

10.2 MASKABLE INTERRUPTS

All interrupts other than the Software Trap are maskable.

Each maskable interrupt has an associated enable bit and

pending flag bit. The pending bit is set to 1 when the interrupt

condition occurs. The state of the interrupt enable bit, com-

bined with the GIE bit determines whether an active pending

flag actually triggers an interrupt. All of the maskable inter-

rupt pending and enable bits are contained in mapped con-

trol registers, and thus can be controlled by the software.

Within a specific interrupt service routine, the associated

pending bit should be cleared. This is typically done as early

as possible in the service routine in order to avoid missing

the next occurrence of the same type of interrupt event.

Thus, if the same event occurs a second time, even while the

first occurrence is still being serviced, the second occur-

rence will be serviced immediately upon return from the

current interrupt routine.

A maskable interrupt condition triggers an interrupt under the

following conditions:

1. The enable bit associated with that interrupt is set.

2. The GIE bit is set.

An interrupt service routine typically ends with an RETI

instruction. This instruction sets the GIE bit back to 1, pops

the address stored on the stack, and restores that address to

the program counter. Program execution then proceeds with

the next instruction that would have been executed had

there been no interrupt. If there are any valid interrupts

pending, the highest-priority interrupt is serviced immedi-

ately upon return from the previous interrupt.

3. The device is not processing a non-maskable interrupt.

(If

a non-maskable interrupt is being serviced, a

maskable interrupt must wait until that service routine is

completed.)

An interrupt is triggered only when all of these conditions are

met at the beginning of an instruction. If different maskable

interrupts meet these conditions simultaneously, the highest

priority interrupt will be serviced first, and the other pending

interrupts must wait.

10.3 VIS INSTRUCTION

The general interrupt service routine, which starts at address

00FF Hex, must be capable of handling all types of inter-

rupts. The VIS instruction, together with an interrupt vector

table, directs the device to the specific interrupt handling

routine based on the cause of the interrupt.

Upon Reset, all pending bits, individual enable bits, and the

GIE bit are reset to zero. Thus, a maskable interrupt condi-

tion cannot trigger an interrupt until the program enables it by

setting both the GIE bit and the individual enable bit. When

enabling an interrupt, the user should consider whether or

not a previously activated (set) pending bit should be ac-

knowledged. If, at the time an interrupt is enabled, any

previous occurrences of the interrupt should be ignored, the

associated pending bit must be reset to zero prior to en-

abling the interrupt. Otherwise, the interrupt may be simply

enabled; if the pending bit is already set, it will immediately

trigger an interrupt. A maskable interrupt is active if its asso-

ciated enable and pending bits are set.

VIS is a single-byte instruction, typically used at the very

beginning of the general interrupt service routine at address

00FF Hex, or shortly after that point, just after the code used

for context switching. The VIS instruction determines which

enabled and pending interrupt has the highest priority, and

causes an indirect jump to the address corresponding to that

interrupt source. The jump addresses (vectors) for all pos-

sible interrupts sources are stored in a vector table.

The vector table may be as long as 32 bytes (maximum of 16

vectors) and resides at the top of the 256-byte block con-

taining the VIS instruction. However, if the VIS instruction is

at the very top of a 256-byte block (such as at 00FF Hex),

the vector table resides at the top of the next 256-byte block.

Thus, if the VIS instruction is located somewhere between

00FF and 01DF Hex (the usual case), the vector table is

located between addresses 01E0 and 01FF Hex. If the VIS

instruction is located between 01FF and 02DF Hex, then the

vector table is located between addresses 02E0 and 02FF

Hex, and so on.

An interrupt is an asychronous event which may occur be-

fore, during, or after an instruction cycle. Any interrupt which

occurs during the execution of an instruction is not acknowl-

edged until the start of the next normally executed instruction

is to be skipped, the skip is performed before the pending

interrupt is acknowledged.

At the start of interrupt acknowledgment, the following ac-

tions occur:

1. The GIE bit is automatically reset to zero, preventing any

subsequent maskable interrupt from interrupting the cur-

rent service routine. This feature prevents one maskable

interrupt from interrupting another one being serviced.

Each vector is 15 bits long and points to the beginning of a

specific interrupt service routine somewhere in the 32 kbyte

memory space. Each vector occupies two bytes of the vector

table, with the higher-order byte at the lower address. The

vectors are arranged in order of interrupt priority. The vector

of the maskable interrupt with the lowest rank is located to

0yE0 (higher-order byte) and 0yE1 (lower-order byte). The

next priority interrupt is located at 0yE2 and 0yE3, and so

forth in increasing rank. The Software Trap has the highest

rank and its vector is always located at 0yFE and 0yFF. The

number of interrupts which can become active defines the

size of the table.

2. The address of the instruction about to be executed is

pushed onto the stack.

3. The program counter (PC) is loaded with 00FF Hex,

causing a jump to that program memory location.

The device requires seven instruction cycles to perform the

actions listed above.

If the user wishes to allow nested interrupts, the interrupts

service routine may set the GIE bit to 1 by writing to the PSW

register, and thus allow other maskable interrupts to interrupt

the current service routine. If nested interrupts are allowed,

caution must be exercised. The user must write the program

in such a way as to prevent stack overflow, loss of saved

context information, and other unwanted conditions.

Table 6 shows the types of interrupts, the interrupt arbitration

ranking, and the locations of the corresponding vectors in

the vector table.

The vector table should be filled by the user with the memory

locations of the specific interrupt service routines. For ex-

The interrupt service routine stored at location 00FF Hex

should use the VIS instruction to determine the cause of the

35

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gram context (A, B, X, etc.) and executing the RETI instruc-

tion, an interrupt service routine can be terminated by return-

ing to the VIS instruction. In this case, interrupts will be

serviced in turn until no further interrupts are pending and

the default VIS routine is started. After testing the GIE bit to

ensure that execution is not erroneous, the routine should

restore the program context and execute the RETI to return

to the interrupted program.

10.0 Interrupts (Continued)

ample, if the Software Trap routine is located at 0310 Hex,

then the vector location 0yFE and -0yFF should contain the

data 03 and 10 Hex, respectively. When a Software Trap

interrupt occurs and the VIS instruction is executed, the

program jumps to the address specified in the vector table.

The interrupt sources in the vector table are listed in order of

rank, from highest to lowest priority. If two or more enabled

and pending interrupts are detected at the same time, the

one with the highest priority is serviced first. Upon return

from the interrupt service routine, the next highest-level

pending interrupt is serviced.

This technique can save up to fifty instruction cycles (t

_c), or

more, (50µs at 10 MHz oscillator) of latency for pending

interrupts with a penalty of fewer than ten instruction cycles

if no further interrupts are pending.

To ensure reliable operation, the user should always use the

VIS instruction to determine the source of an interrupt. Al-

though it is possible to poll the pending bits to detect the

source of an interrupt, this practice is not recommended. The

use of polling allows the standard arbitration ranking to be

altered, but the reliability of the interrupt system is compro-

mised. The polling routine must individually test the enable

and pending bits of each maskable interrupt. If a Software

Trap interrupt should occur, it will be serviced last, even

though it should have the highest priority. Under certain

conditions, a Software Trap could be triggered but not ser-

viced, resulting in an inadvertent “locking out” of all

maskable interrupts by the Software Trap pending flag.

Problems such as this can be avoided by using VIS

instruction.

If the VIS instruction is executed, but no interrupts are en-

abled and pending, the lowest-priority interrupt vector is

used, and a jump is made to the corresponding address in

the vector table. This is an unusual occurrence, and may be

the result of an error. It can legitimately result from a change

in the enable bits or pending flags prior to the execution of

the VIS instruction, such as executing a single cycle instruc-

tion which clears an enable flag at the same time that the

pending flag is set. It can also result, however, from inad-

vertent execution of the VIS command outside of the context

of an interrupt.

The default VIS interrupt vector can be useful for applica-

tions in which time critical interrupts can occur during the

servicing of another interrupt. Rather than restoring the pro-

TABLE 6. Interrupt Vector Table

Description

INTR Instruction

Vector Address (Note 17)

Arbitration Ranking

Source

(Hi-Low Byte)

(1) Highest

(2)

Software

Reserved

External

Timer T0

Timer T1

0yFE–0yFF

0yFC–0yFD

0yFA–0yFB

0yF8–0yF9

0yF6–0yF7

0yF4–0yF5

0yF2–0yF3

0yF0–0yF1

0yEE–0yEF

0yEC–0yED

0yEA–0yEB

0yE8–0yE9

0yE6–0yE7

0yE4–0yE5

0yE2–0yE3

0yE0–0yE1

(3)

G0

(4)

Underflow

T1A/Underflow

T1B

(5)

(6)

(7)

MICROWIRE/PLUS

Reserved

BUSY Low

(8)

(9)

USART

Receive

(10)

(11)

USART

Transmit

Timer T2

T2A/Underflow

T2B

(12)

(13)

(14)

(15)

(16) Lowest

Timer T2

Timer T3

T2A/Underflow

T3B

Timer T3

Port L/Wakeup

Default VIS

Port L Edge

Reserved

Note 17: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last

address of a block. In this case, the table must be in the next block.

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36

remains unchanged. The new PC is therefore pointing to the

vector of the active interrupt with the highest arbitration

ranking. This vector is read from program memory and

placed into the PC which is now pointed to the 1st instruction

of the service routine of the active interrupt with the highest

arbitration ranking.

10.0 Interrupts (Continued)

10.3.1 VIS Execution

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc...) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FA is generated and so forth. If the only active

interrupt is software trap, than E0 is generated. This number

replaces the lower byte of the PC. The upper byte of the PC

Figure 26 illustrates the different steps performed by the VIS

instruction. Figure 27 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

10131729

FIGURE 26. VIS Operation

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10.0 Interrupts (Continued)

10131730

FIGURE 27. VIS Flowchart

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38

10.0 Interrupts (Continued)

Programming Example: External Interrupt

PSW

CNTRL

RBIT

SBIT

JP

=00EF

=00EE

0,PORTGC

0,PORTGD

IEDG, CNTRL

EXEN, PSW

GIE, PSW

WAIT

; G0 pin configured Hi-Z

; Ext interrupt polarity; falling edge

; Enable the external interrupt

; Set the GIE bit

WAIT:

; Wait for external interrupt

.

.=0FF

VIS

; The interrupt causes a

; branch to address 0FF

; The VIS causes a branch to

;interrupt vector table

.

.=01FA

.ADDRW SERVICE

; Vector table (within 256 byte

; of VIS inst.) containing the ext

; interrupt service routine

.

INT_EXIT:

SERVICE:

RETI

.

RBIT

EXPND, PSW

; Interrupt Service Routine

; Reset ext interrupt pend. bit

.

JP

INT_EXIT

; Return, set the GIE bit

39

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flag; upon return to the first Software Trap routine, the

STPND flag will have the wrong state. This will allow

maskable interrupts to be acknowledged during the servicing

of the first Software Trap. To avoid problems such as this, the

user program should contain the Software Trap routine to

perform a recovery procedure rather than a return to normal

execution.

10.0 Interrupts (Continued)

10.4 NON-MASKABLE INTERRUPT

10.4.1 Pending Flag

There is a pending flag bit associated with the non-maskable

interrupt, called STPND. This pending flag is not memory-

mapped and cannot be accessed directly by the software.

Under normal conditions, the STPND flag is reset by a

RPND instruction in the Software Trap service routine. If a

programming error or hardware condition (brownout, power

supply glitch, etc.) sets the STPND flag without providing a

way for it to be cleared, all other interrupts will be locked out.

To alleviate this condition, the user can use extra RPND

instructions in the main program and in the WATCHDOG

service routine (if present). There is no harm in executing

extra RPND instructions in these parts of the program.

The pending flag is reset to zero when a device Reset

occurs. When the non-maskable interrupt occurs, the asso-

ciated pending bit is set to 1. The interrupt service routine

should contain an RPND instruction to reset the pending flag

to zero. The RPND instruction always resets the STPND

flag.

10.4.2 Software Trap

The Software Trap is a special kind of non-maskable inter-

rupt which occurs when the INTR instruction (used to ac-

knowledge interrupts) is fetched from program memory and

placed in the instruction register. This can happen in a

variety of ways, usually because of an error condition. Some

examples of causes are listed below.

10.5 PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up

circuitry. The register WKEN allows interrupts from Port L to

be individually enabled or disabled. The register WKEDG

specifies the trigger condition to be either a positive or a

negative edge. Finally, the register WKPND latches in the

pending trigger conditions.

If the program counter incorrectly points to a memory loca-

tion beyond the available program memory space, the non-

existent or unused memory location returns zeroes which is

interpreted as the INTR instruction.

If the stack is popped beyond the allowed limit (address 06F

Hex), a 7FFF will be loaded into the PC, if this last location in

program memory is unprogrammed or unavailable, a Soft-

ware Trap will be triggered.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

A Software Trap can be triggered by a temporary hardware

condition such as a brownout or power supply glitch.

The Software Trap has the highest priority of all interrupts.

When a Software Trap occurs, the STPND bit is set. The GIE

bit is not affected and the pending bit (not accessible by the

user) is used to inhibit other interrupts and to direct the

program to the ST service routine with the VIS instruction.

Nothing can interrupt a Software Trap service routine except

for another Software Trap. The STPND can be reset only by

the RPND instruction or a chip Reset.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart

execution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the

interrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

The Software Trap indicates an unusual or unknown error

condition. Generally, returning to normal execution at the

point where the Software Trap occurred cannot be done

reliably. Therefore, the Software Trap service routine should

reinitialize the stack pointer and perform a recovery proce-

dure that restarts the software at some known point, similar

to a device Reset, but not necessarily performing all the

same functions as a device Reset. The routine must also

execute the RPND instruction to reset the STPND flag.

Otherwise, all other interrupts will be locked out. To the

extent possible, the interrupt routine should record or indi-

cate the context of the device so that the cause of the

Software Trap can be determined.

10.6 INTERRUPT SUMMARY

The device uses the following types of interrupts, listed

below in order of priority:

1. The Software Trap non-maskable interrupt, triggered by

the INTR (00 opcode) instruction. The Software Trap is

acknowledged immediately. This interrupt service rou-

tine can be interrupted only by another Software Trap.

The Software Trap should end with two RPND instruc-

tions followed by a restart procedure.

2. Maskable interrupts, triggered by an on-chip peripheral

block or an external device connected to the device.

Under ordinary conditions, a maskable interrupt will not

interrupt any other interrupt routine in progress. A

maskable interrupt routine in progress can be inter-

If the user wishes to return to normal execution from the

point at which the Software Trap was triggered, the user

must first execute RPND, followed by RETSK rather than

RETI or RET. This is because the return address stored on

the stack is the address of the INTR instruction that triggered

the interrupt. The program must skip that instruction in order

to proceed with the next one. Otherwise, an infinite loop of

Software Traps and returns will occur.

rupted by the non-maskable interrupt request.

A

maskable interrupt routine should end with an RETI

instruction or, prior to restoring context, should return to

execute the VIS instruction. This is particularly useful

when exiting long interrupt service routiness if the time

between interrupts is short. In this case the RETI instruc-

tion would only be executed when the default VIS rou-

tine is reached.

Programming a return to normal execution requires careful

consideration. If the Software Trap routine is interrupted by

another Software Trap, the RPND instruction in the service

routine for the second Software Trap will reset the STPND

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40

11.2 WATCHDOG/CLOCK MONITOR OPERATION

11.0 WATCHDOG/Clock Monitor

The WATCHDOG is enabled by bit 2 of the ECON register.

When this ECON bit is 0, the WATCHDOG is enabled and

pin G1 becomes the WATCHDOG output with a weak pullup.

Each device contains a user selectable WATCHDOG and

clock monitor. The following section is applicable only if

WATCHDOG feature has been selected in the ECON regis-

ter. The WATCHDOG is designed to detect the user program

getting stuck in infinite loops resulting in loss of program

control or “runaway” programs.

The WATCHDOG and Clock Monitor are disabled during

reset. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select bits (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

The WATCHDOG logic contains two separate service win-

dows. While the user programmable upper window selects

the WATCHDOG service time, the lower window provides

protection against an infinite program loop that contains the

WATCHDOG service instruction.

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR

register involves two irrevocable choices: (i) the selection of

the WATCHDOG service window (ii) enabling or disabling of

the Clock Monitor. Hence, the first write to WDSVR Register

involves selecting or deselecting the Clock Monitor, select

the WATCHDOG service window and match the WATCH-

DOG key data. Subsequent writes to the WDSVR register

will compare the value being written by the user to the

WATCHDOG service window value and the key data (bits 7

through 1) in the WDSVR Register. Table 9 shows the se-

quence of events that can occur.

The Clock Monitor is used to detect the absence of a clock or

a very slow clock below a specified rate on the CKI pin.

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 7 shows the WDSVR register.

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The WATCH-

DOG may not be serviced more than once in every lower

limit of the service window.

TABLE 7. WATCHDOG Service Register (WDSVR)

Window

Select

Clock

Key Data

Monitor

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the port G. WDOUT is active

low and must be externally connected to the RESET pin or to

some other external logic which handles WATCHDOG event.

The WDOUT pin has a weak pullup in the inactive state. This

pull-up is sufficient to serve as the connection to V_CCfor

systems which use the internal Power On Reset. Upon

triggering the WATCHDOG, the logic will pull the WDOUT

(G1) pin low for an additional 16 t_C–32 t_Ccycles after the

signal level on WDOUT pin goes below the lower Schmitt

trigger threshold. After this delay, the device will stop forcing

the WDOUT output low. The WATCHDOG service window

will restart when the WDOUT pin goes high.

X

7

X

6

0

5

1

4

1

3

0

2

0

1

Y

0

The lower limit of the service window is fixed at 2048 instruc-

tion cycles. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 8 shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

A WATCHDOG service while the WDOUT signal is active will

be ignored. The state of the WDOUT pin is not guaranteed

on reset, but if it powers up low then the WATCHDOG will

time out and WDOUT will go high.

TABLE 8. WATCHDOG Service Window Select

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error. The Clock Monitor error will continue

until the clock frequency has reached the minimum specified

value, after which the G1 output will go high following 16

t_C–32 t_Cclock cycles. The Clock Monitor generates a con-

tinual Clock Monitor error if the oscillator fails to start, or fails

to reach the minimum specified frequency. The specification

for the Clock Monitor is as follows:

WDSVR WDSVR Clock

Service Window

(Lower-Upper Limits)

2048–8k t_CCycles

Bit 7

Bit 6

Monitor

0

1

x

0

1

0

1

x

0

1

2048–16k t_CCycles

2048–32k t_CCycles

2048–64k t_CCycles

Clock Monitor Disabled

Clock Monitor Enabled

>

1/t_C10 kHz—No clock rejection.

<

1/t_C10 Hz—Guaranteed clock rejection.

11.1 CLOCK MONITOR

The Clock Monitor aboard the device can be selected or

deselected under program control. The Clock Monitor is

guaranteed not to reject the clock if the instruction cycle

clock (1/t_C) is greater or equal to 10 kHz. This equates to a

clock input rate on CKI of greater or equal to 100 kHz.

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11.0 WATCHDOG/Clock Monitor (Continued)

TABLE 9. WATCHDOG Service Actions

Window Clock Action

Key

Data

Monitor

Match

Valid Service: Restart Service Window

Don’t Care

Mismatch

Don’t Care

Mismatch

Don’t Care

Don’t Care Error: Generate WATCHDOG Output

Mismatch

Error: Generate WATCHDOG Output

11.3 WATCHDOG AND CLOCK MONITOR SUMMARY

•

Following RESET, the initial WATCHDOG service (where

the service window and the CLOCK MONITOR enable/

disable must be selected) may be programmed any-

where within the maximum service window (65,536 in-

struction cycles) initialized by RESET. Note that this initial

WATCHDOG service may be programmed within the ini-

tial 2048 instruction cycles without causing a WATCH-

DOG error.

The following salient points regarding the WATCHDOG and

CLOCK MONITOR should be noted:

•

Both the WATCHDOG and CLOCK MONITOR detector

circuits are inhibited during RESET.

•

Following RESET, the WATCHDOG and CLOCK MONI-

TOR are both enabled, with the WATCHDOG having the

maximum service window selected.

•

The WATCHDOG service window and CLOCK MONI-

TOR enable/disable option can only be changed once,

during the initial WATCHDOG service following RESET.

11.4 DETECTION OF ILLEGAL CONDITIONS

The device can detect various illegal conditions resulting

from coding errors, transient noise, power supply voltage

drops, runaway programs, etc.

The initial WATCHDOG service must match the key data

value in the WATCHDOG Service register WDSVR in

order to avoid a WATCHDOG error.

Reading of undefined ROM gets zeroes. The opcode for

software interrupt is 00. If the program fetches instructions

from undefined ROM, this will force a software interrupt, thus

signaling that an illegal condition has occurred.

Subsequent WATCHDOG services must match all three

data fields in WDSVR in order to avoid WATCHDOG

errors.

The subroutine stack grows down for each call (jump to

subroutine), interrupt, or PUSH, and grows up for each

return or POP. The stack pointer is initialized to RAM location

06F Hex during reset. Consequently, if there are more re-

turns than calls, the stack pointer will point to addresses 070

and 071 Hex (which are undefined RAM). Undefined RAM

from addresses 070 to 07F (Segment 0), and all other seg-

ments (i.e., Segments 4 … etc.) is read as all 1’s, which in

turn will cause the program to return to address 7FFF Hex. It

is recommended that the user either leave this location

unprogrammed or place an INTR instruction (all 0’s) in this

location to generate a software interrupt signaling an illegal

condition.

The correct key data value cannot be read from the

WATCHDOG Service register WDSVR. Any attempt to

read this key data value of 01100 from WDSVR will read

as key data value of all 0’s.

•

The WATCHDOG detector circuit is inhibited during both

the HALT and IDLE modes.

The CLOCK MONITOR detector circuit is active during

both the HALT and IDLE modes. Consequently, the de-

vice inadvertently entering the HALT mode will be de-

tected as a CLOCK MONITOR error (provided that the

CLOCK MONITOR enable option has been selected by

the program).

Thus, the chip can detect the following illegal conditions:

1. Executing from undefined ROM.

•

With the single-pin R/C oscillator option selected and the

CLKDLY bit reset, the WATCHDOG service window will

resume following HALT mode from where it left off before

entering the HALT mode.

2. Over “POP”ing the stack by having more returns than

calls.

With the crystal oscillator option selected, or with the

single-pin R/C oscillator option selected and the CLKDLY

bit set, the WATCHDOG service window will be set to its

selected value from WDSVR following HALT. Conse-

quently, the WATCHDOG should not be serviced for at

least 2048 instruction cycles following HALT, but must be

serviced within the selected window to avoid a WATCH-

DOG error.

When the software interrupt occurs, the user can re-initialize

the stack pointer and do a recovery procedure before restart-

ing (this recovery program is probably similar to that follow-

ing reset, but might not contain the same program initializa-

tion procedures). The recovery program should reset the

software interrupt pending bit using the RPND instruction.

12.0 MICROWIRE/PLUS

•

The IDLE timer T0 is not initialized with external RESET.

MICROWIRE/PLUS is a serial SPI compatible synchronous

communications interface. The MICROWIRE/PLUS capabil-

ity enables the device to interface with MICROWIRE/PLUS

or SPI peripherals (i.e. A/D converters, display drivers, EE-

PROMs etc.) and with other microcontrollers which support

the MICROWIRE/PLUS or SPI interface. It consists of an

8-bit serial shift register (SIO) with serial data input (SI),

serial data output (SO) and serial shift clock (SK). Figure 28

shows a block diagram of the MICROWIRE/PLUS logic.

The user can sync in to the IDLE counter cycle with an

IDLE counter (T0) interrupt or by monitoring the T0PND

flag. The T0PND flag is set whenever the twelfth bit of the

IDLE counter toggles (every 4096 instruction cycles). The

user is responsible for resetting the T0PND flag.

•

A hardware WATCHDOG service occurs just as the de-

vice exits the IDLE mode. Consequently, the WATCH-

DOG should not be serviced for at least 2048 instruction

cycles following IDLE, but must be serviced within the

selected window to avoid a WATCHDOG error.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS

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42

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave. Figure 28 shows how

two microcontroller devices and several peripherals may be

interconnected using the MICROWIRE/PLUS arrangements.

12.0 MICROWIRE/PLUS (Continued)

arrangement with the internal clock source is called the

Master mode of operation. Similarly, operating the

MICROWIRE/PLUS arrangement with an external shift clock

is called the Slave mode of operation.

WARNING

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the

master mode, the SK clock rate is selected by the two bits,

SL0 and SL1, in the CNTRL register. Table 10 details the

different clock rates that may be selected.

The SIO register should only be loaded when the SK clock is

in the idle phase. Loading the SIO register while the SK clock

is in the active phase, will result in undefined data in the SIO

register.

Setting the BUSY flag when the input SK clock is in the

active phase while in the MICROWIRE/PLUS is in the slave

mode may cause the current SK clock for the SIO shift

register to be narrow. For safety, the BUSY flag should only

be set when the input SK clock is in the idle phase.

TABLE 10. MICROWIRE/PLUS

Master Mode Clock Select

SL1

0

SL0

SK Period

2 x t_C

12.1.1 MICROWIRE/PLUS Master Mode Operation

0

1

x

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE

Master always initiates all data exchanges. The MSEL bit in

the CNTRL register must be set to enable the SO and SK

functions onto the G Port. The SO and SK pins must also be

selected as outputs by setting appropriate bits in the Port G

configuration register. In the slave mode, the shift clock

stops after 8 clock pulses. Table 11 summarizes the bit

settings required for Master mode of operation.

0

4 x t_C

1

8 x t_C

Where t is the instruction cycle clock

C

12.1 MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

10131732

FIGURE 28. MICROWIRE/PLUS Application

43

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The user must set the BUSY flag immediately upon entering

the Slave mode. This ensures that all data bits sent by the

Master is shifted properly. After eight clock pulses the BUSY

flag is clear, the shift clock is stopped, and the sequence

may be repeated.

12.0 MICROWIRE/PLUS (Continued)

12.1.2 MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and

resetting the appropriate bits in the Port G configuration

register. Table 11 summarizes the settings required to enter

the Slave mode of operation.

12.1.3 Alternate SK Phase Operation and SK Idle P

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK idle polarity can be either high or low.

The polarity is selected by bit 5 of Port G data register. In the

normal mode data is shifted in on the rising edge of the SK

clock and the data is shifted out on the falling edge of the SK

clock. In the alternate SK phase operation, data is shifted in

on the falling edge of the SK clock and shifted out on the

rising edge of the SK clock. Bit 6 of Port G configuration

register selects the SK edge.

TABLE 11. MICROWIRE/PLUS Mode Settings

This table assumes that the control flag MSEL is set.

G4 (SO)

G5 (SK)

G4

Fun.

SO

G5

Operation

Config. Bit Config. Bit

Fun.

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configu-

ration bit. The SKSEL flag will power up in the reset condi-

tion, selecting the normal SK signal.

1

0

1

0

1

0

Int. MICROWIRE/PLUS

SK Master

TRI-

STATE

SO

Int. MICROWIRE/PLUS

SK Master

Ext. MICROWIRE/PLUS

SK Slave

TRI-

Ext. MICROWIRE/PLUS

SK Slave

STATE

TABLE 12. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase

Port G

SK Phase

G6 (SKSEL)

G5 Data

SO Clocked Out On:

SI Sampled On:

SK Idle

Phase

Low

Config. Bit

Bit

0

Normal

Alternate

Normal

0

1

0

1

SK Falling Edge

SK Rising Edge

SK Falling Edge

SK Rising Edge

SK Falling Edge

SK Rising Edge

0

Low

1

High

1

High

10131733

FIGURE 29. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low

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44

12.0 MICROWIRE/PLUS (Continued)

10131734

FIGURE 30. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low

10131735

FIGURE 31. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High

10131731

FIGURE 32. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High

45

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13.0 Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

S/ADD REG

xxC9

Contents

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

xxCA

Address

Contents

xxCB to xxCF Reserved

S/ADD REG

xxD0

xxD1

xxD2

xxD3

xxD4

xxD5

xxD6

xxD7

Port L Data Register

0000 to 006F On-Chip RAM bytes (112 bytes)

0070 to 007F Unused RAM Address Space (Reads As

All Ones)

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

xx80 to xx93

Unused RAM Address Space (Reads

Undefined Data)

Port G Data Register

xx94

xx95

xx96

Port F data register, PORTFD

Port F configuration register, PORTFC

Port F input pins (read only), PORTFP

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only) (Actually

reads Port F input pins)

Port C Data Register

xx97 to xxAF Unused address space (Reads Undefined

Data)

xxD8

xxD9

xxDA

xxDB

xxDC

xxB0

xxB1

xxB2

Timer T3 Lower Byte

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

Timer T3 Upper Byte

Timer T3 Autoload Register T3RA Lower

Byte

Port D

xxB3

xxB4

xxB5

Timer T3 Autoload Register T3RA Upper

Byte

xxDD to xxDF Reserved for Port D

xxE0 to xxE5 Reserved for EE Control Registers

Timer T3 Autoload Register T3RB Lower

Byte

xxE6

Timer T1 Autoload Register T1RB Lower

Byte

Timer T3 Autoload Register T3RB Upper

Byte

xxE7

Timer T1 Autoload Register T1RB Upper

Byte

xxB6

xxB7

xxB8

xxB9

xxBA

Timer T3 Control Register

Comparator Select Register (Reg:CMPSL)

UART Transmit Buffer (Reg:TBUF)

UART Receive Buffer (Reg:RBUF)

UART Control and Status Register

(Reg:ENU)

xxE8

xxE9

xxEA

xxEB

xxEC

ICNTRL Register

MICROWIRE/PLUS Shift Register

Timer T1 Lower Byte

Timer T1 Upper Byte

Timer T1 Autoload Register T1RA Lower

Byte

xxBB

xxBC

UART Receive Control and Status

Register (Reg:ENUR)

xxED

Timer T1 Autoload Register T1RA Upper

Byte

UART Interrupt and Clock Source Register

(Reg:ENUI)

xxEE

CNTRL Control Register

PSW Register

xxEF

xxBD

xxBE

xxBF

xxC0

xxC1

xxC2

UART Baud Register (Reg:BAUD)

UART Prescale Select Register (Reg:PSR)

Reserved for UART

xxF0 to FB

xxFC

On-Chip RAM Mapped as Registers

X Register

xxFD

SP Register

Timer T2 Lower Byte

xxFE

B Register

Timer T2 Upper Byte

xxFF

S Register

Timer T2 Autoload Register T2RA Lower

Byte

0100–017F

0200–027F

On-Chip 128 RAM Bytes

On-Chip 128 RAM Bytes (Reads as

undefined data on COP8SGE)

On-Chip 128 RAM Bytes (Reads as

undefined data on COP8SGE)

xxC3

xxC4

xxC5

Timer T2 Autoload Register T2RA Upper

Byte

0300–037F

Timer T2 Autoload Register T2RB Lower

Byte

Note: Reading memory locations 0070H–007FH (Segment 0) will return all

ones. Reading unused memory locations 0080H–0093H (Segment 0)

will return undefined data. Reading memory locations from other Seg-

ments (i.e., Segment 4, Segment 5, … etc.) will return undefined data.

Timer T2 Autoload Register T2RB Upper

Byte

xxC6

xxC7

Timer T2 Control Register

WATCHDOG Service Register

(Reg:WDSVR)

xxC8

MIWU Edge Select Register

(Reg:WKEDG)

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46

The available addressing modes are:

14.0 Instruction Set

•

Direct

14.1 INTRODUCTION

Register B or X Indirect

This section defines the instruction set of the COP8 Family

members. It contains information about the instruction set

features, addressing modes and types.

Register

B or X Indirect with Post-Incrementing/

Decrementing

•

Immediate

Immediate Short

Indirect from Program Memory

14.2 INSTRUCTION FEATURES

The strength of the instruction set is based on the following

features:

The addressing modes are described below. Each descrip-

tion includes an example of an assembly language instruc-

tion using the described addressing mode.

•

Mostly single-byte opcode instructions minimize program

size.

Direct. The memory address is specified directly as a byte in

the instruction. In assembly language, the direct address is

written as a numerical value (or a label that has been defined

elsewhere in the program as a numerical value).

One instruction cycle for the majority of single-byte in-

structions to minimize program execution time.

Many single-byte, multiple function instructions such as

DRSZ.

Example: Load Accumulator Memory Direct

LD A,05

Three memory mapped pointers: two for register indirect

addressing, and one for the software stack.

Reg/Data

Memory

Contents

Before

Contents

After

Sixteen memory mapped registers that allow an opti-

mized implementation of certain instructions.

Ability to set, reset, and test any individual bit in data

memory address space, including the memory-mapped

I/O ports and registers.

Accumulator

Memory Location

0005 Hex

XX Hex

A6 Hex

•

Register-Indirect LOAD and EXCHANGE instructions

with optional automatic post-incrementing or decrement-

ing of the register pointer. This allows for greater effi-

ciency (both in cycle time and program code) in loading,

walking across and processing fields in data memory.

Register B or X Indirect. The memory address is specified

by the contents of the B Register or X register (pointer

register). In assembly language, the notation [B] or [X] speci-

fies which register serves as the pointer.

Unique instructions to optimize program size and

throughput efficiency. Some of these instructions are

DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.

Example: Exchange Memory with Accumulator, B Indirect

X A,[B]

Reg/Data

Memory

Contents

Before

Contents

After

14.3 ADDRESSING MODES

The instruction set offers a variety of methods for specifying

memory addresses. Each method is called an addressing

mode. These modes are classified into two categories: op-

erand addressing modes and transfer-of-control addressing

modes. Operand addressing modes are the various meth-

ods of specifying an address for accessing (reading or writ-

ing) data. Transfer-of-control addressing modes are used in

conjunction with jump instructions to control the execution

sequence of the software program.

Accumulator

Memory Location

0005 Hex

01 Hex

87 Hex

01 Hex

B Pointer

05 Hex

Register

B or X Indirect with Post-Incrementing/

Decrementing. The relevant memory address is specified

by the contents of the B Register or X register (pointer

register). The pointer register is automatically incremented

or decremented after execution, allowing easy manipulation

of memory blocks with software loops. In assembly lan-

guage, the notation [B+], [B−], [X+], or [X−] specifies which

register serves as the pointer, and whether the pointer is to

be incremented or decremented.

14.3.1 Operand Addressing Modes

The operand of an instruction specifies what memory loca-

tion is to be affected by that instruction. Several different

operand addressing modes are available, allowing memory

locations to be specified in a variety of ways. An instruction

can specify an address directly by supplying the specific

address, or indirectly by specifying a register pointer. The

contents of the register (or in some cases, two registers)

point to the desired memory location. In the immediate

mode, the data byte to be used is contained in the instruction

itself.

Example: Exchange Memory with Accumulator, B Indirect

with Post-Increment

X A,[B+]

Reg/Data

Memory

Contents

Before

Contents

After

Each addressing mode has its own advantages and disad-

vantages with respect to flexibility, execution speed, and

program compactness. Not all modes are available with all

instructions. The Load (LD) instruction offers the largest

number of addressing modes.

Accumulator

Memory Location

0005 Hex

03 Hex

62 Hex

03 Hex

B Pointer

05 Hex

06 Hex

Intermediate. The data for the operation follows the instruc-

tion opcode in program memory. In assembly language, the

number sign character (#) indicates an immediate operand.

47

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•

Jump Indirect

14.0 Instruction Set (Continued)

The transfer-of-control addressing modes are described be-

low. Each description includes an example of a Jump in-

struction using a particular addressing mode, and the effect

on the Program Counter bytes of executing that instruction.

Example: Load Accumulator Immediate

#

LD A, 05

Reg/Data

Memory

Contents

Before

Contents

After

Jump Relative. In this 1-byte instruction, six bits of the

instruction opcode specify the distance of the jump from the

current program memory location. The distance of the jump

can range from −31 to +32. A JP+1 instruction is not allowed.

The programmer should use a NOP instead.

Accumulator

XX Hex

05 Hex

Immediate Short. This is a special case of an immediate

instruction. In the “Load B immediate” instruction, the 4-bit

immediate value in the instruction is loaded into the lower

nibble of the B register. The upper nibble of the B register is

reset to 0000 binary.

Example: Jump Relative

JP 0A

Reg

Contents

Before

Contents

After

Example: Load B Register Immediate Short

LD B,#7

PCU

PCL

02 Hex

05 Hex

02 Hex

0F Hex

Reg/Data

Memory

B Pointer

Contents

Before

Contents

After

Jump Absolute. In this 2-byte instruction, 12 bits of the

instruction opcode specify the new contents of the Program

Counter. The upper three bits of the Program Counter re-

main unchanged, restricting the new Program Counter ad-

dress to the same 4 kbyte address space as the current

instruction.

12 Hex

07 Hex

Indirect from Program Memory. This is a special case of

an indirect instruction that allows access to data tables

stored in program memory. In the “Load Accumulator Indi-

rect” (LAID) instruction, the upper and lower bytes of the

Program Counter (PCU and PCL) are used temporarily as a

pointer to program memory. For purposes of accessing pro-

gram memory, the contents of the Accumulator and PCL are

exchanged. The data pointed to by the Program Counter is

loaded into the Accumulator, and simultaneously, the original

contents of PCL are restored so that the program can re-

sume normal execution.

(This restriction is relevant only in devices using more than

one 4 kbyte program memory space.)

Example: Jump Absolute

JMP 0125

Reg

Contents

Before

Contents

After

Example: Load Accumulator Indirect

LAID

PCU

PCL

0C Hex

77 Hex

01 Hex

25 Hex

Reg/Data

Memory

Contents

Before

04 Hex

35 Hex

1F Hex

25 Hex

Contents

After

Jump Absolute Long. In this 3-byte instruction, 15 bits of

the instruction opcode specify the new contents of the Pro-

gram Counter.

PCU

04 Hex

36 Hex

25 Hex

Example: Jump Absolute Long

JMP 03625

PCL

Accumulator

Memory Location

041F Hex

Reg/

Memory

PCU

Contents

Before

Contents

After

42 Hex

36 Hex

25 Hex

14.3.2 Tranfer-of-Control Addressing Modes

PCL

Program instructions are usually executed in sequential or-

der. However, Jump instructions can be used to change the

normal execution sequence. Several transfer-of-control ad-

dressing modes are available to specify jump addresses.

Jump Indirect. In this 1-byte instruction, the lower byte of

the jump address is obtained from a table stored in program

memory, with the Accumulator serving as the low order byte

of a pointer into program memory. For purposes of access-

ing program memory, the contents of the Accumulator are

written to PCL (temporarily). The data pointed to by the

Program Counter (PCH/PCL) is loaded into PCL, while PCH

remains unchanged.

A change in program flow requires a non-incremental

change in the Program Counter contents. The Program

Counter consists of two bytes, designated the upper byte

(PCU) and lower byte (PCL). The most significant bit of PCU

is not used, leaving 15 bits to address the program memory.

Example: Jump Indirect

JID

Different addressing modes are used to specify the new

address for the Program Counter. The choice of addressing

mode depends primarily on the distance of the jump. Farther

jumps sometimes require more instruction bytes in order to

completely specify the new Program Counter contents.

Reg/

Memory

PCU

Contents

Before

01 Hex

C4 Hex

26 Hex

Contents

After

01 Hex

32 Hex

26 Hex

The available transfer-of-control addressing modes are:

PCL

•

Jump Relative

Accumulator

Memory

Jump Absolute

Jump Absolute Long

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48

14.4.3 Load and Exchange Instructions

14.0 Instruction Set (Continued)

The load and exchange instructions write byte values in

registers or memory. The addressing mode determines the

source of the data.

Reg/

Contents

Before

Contents

After

Memory

Location

0126 Hex

Load (LD)

32 Hex

Load Accumulator Indirect (LAID)

Exchange (X)

The VIS instruction is a special case of the Indirect Transfer

of Control addressing mode, where the double-byte vector

associated with the interrupt is transferred from adjacent

addresses in program memory into the Program Counter in

order to jump to the associated interrupt service routine.

14.4.4 Logical Instructions

The logical instructions perform the operations AND, OR,

and XOR (Exclusive OR). Other logical operations can be

performed by combining these basic operations. For ex-

ample, complementing is accomplished by exclusiveORing

the Accumulator with FF Hex.

14.4 INSTRUCTION TYPES

The instruction set contains a wide variety of instructions.

The available instructions are listed below, organized into

related groups.

Logical AND (AND)

Logical OR (OR)

Exclusive OR (XOR)

Some instructions test a condition and skip the next instruc-

tion if the condition is not true. Skipped instructions are

executed as no-operation (NOP) instructions.

14.4.5 Accumulator Bit Manipulation Instructions

The Accumulator bit manipulation instructions allow the user

to shift the Accumulator bits and to swap its two nibbles.

14.4.1 Arithmetic Instructions

Rotate Right Through Carry (RRC)

Rotate Left Through Carry (RLC)

Swap Nibbles of Accumulator (SWAP)

The arithmetic instructions perform binary arithmetic such as

addition and subtraction, with or without the Carry bit.

Add (ADD)

Add with Carry (ADC)

Subtract (SUB)

14.4.6 Stack Control Instructions

Push Data onto Stack (PUSH)

Pop Data off of Stack (POP)

Subtract with Carry (SUBC)

Increment (INC)

Decrement (DEC)

Decimal Correct (DCOR)

Clear Accumulator (CLR)

Set Carry (SC)

14.4.7 Memory Bit Manipulation Instructions

The memory bit manipulation instructions allow the user to

set and reset individual bits in memory.

Set Bit (SBIT)

Reset Bit (RBIT)

Reset Carry (RC)

Reset Pending Bit (RPND)

14.4.2 Transfer-of-Control Instructions

14.4.8 Conditional Instructions

The transfer-of-control instructions change the usual se-

quential program flow by altering the contents of the Pro-

gram Counter. The Jump to Subroutine instructions save the

Program Counter contents on the stack before jumping; the

Return instructions pop the top of the stack back into the

Program Counter.

The conditional instruction test a condition. If the condition is

true, the next instruction is executed in the normal manner; if

the condition is false, the next instruction is skipped.

If Equal (IFEQ)

If Not Equal (IFNE)

Jump Relative (JP)

If Greater Than (IFGT)

If Carry (IFC)

Jump Absolute (JMP)

Jump Absolute Long (JMPL)

Jump Indirect (JID)

If Not Carry (IFNC)

If Bit (IFBIT)

Jump to Subroutine (JSR)

Jump to Subroutine Long (JSRL)

Return from Subroutine (RET)

Return from Subroutine and Skip (RETSK)

Return from Interrupt (RETI)

Software Trap Interrupt (INTR)

Vector Interrupt Select (VIS)

If B Pointer Not Equal (IFBNE)

And Skip if Zero (ANDSZ)

Decrement Register and Skip if Zero (DRSZ)

14.4.9 No-Operation Instruction

The no-operation instruction does nothing, except to occupy

space in the program memory and time in execution.

No-Operation (NOP)

Note: The VIS is a special case of the Indirect Transfer of Control addressing

mode, where the double byte vector associated with the interrupt is

transferred from adjacent addresses in the program memory into the

program counter (PC) in order to jump to the associated interrupt

service routine.

49

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14.0 Instruction Set (Continued)

Registers

VU

VL

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

14.5 REGISTER AND SYMBOL DEFINITION

The following abbreviations represent the nomenclature

used in the instruction description and the COP8

cross-assembler.

Symbols

[B]

Memory Indirectly Addressed by B Register

Memory Indirectly Addressed by X Register

Direct Addressed Memory

Direct Addressed Memory or [B]

Direct Addressed Memory or [B] or

Immediate Data

Registers

[X]

A

8-Bit Accumulator Register

8-Bit Address Register

MD

B

Mem

Meml

X

8-Bit Address Register

SP

PC

PU

PL

C

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

Imm

Reg

8-Bit Immediate Data

Register Memory: Addresses F0 to FF

(Includes B, X and SP)

Lower 8 Bits of PC

1 Bit of PSW Register for Carry

1 Bit of PSW Register for Half Carry

1 Bit of PSW Register for Global Interrupt

Enable

Bit

←

↔

Bit Number (0 to 7)

HC

GIE

Loaded with

Exchanged with

14.6 INSTRUCTION SET SUMMARY

←

A + Meml

ADD

ADC

A,Meml

ADD

A

←

A + Meml + C, C Carry,

ADD with Carry

←

HC Half Carry

← ←

A − MemI + C, C Carry,

SUBC

AND

A,Meml

Subtract with Carry

A

←

HC Half Carry

←

Logical AND

A

A and Meml

ANDSZ A,Imm

Logical AND Immed., Skip if Zero

Logical OR

Skip next if (A and Imm) = 0

←

OR

A,Meml

MD,Imm

A,Meml

#

A

A or Meml

XOR

IFEQ

IFNE

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

RPND

X

Logical EXclusive OR

IF EQual

A xor Meml

Compare MD and Imm, Do next if MD = Imm

Compare A and Meml, Do next if A = Meml

IF EQual

≠

Compare A and Meml, Do next if A Meml

IF Not Equal

>

IF Greater Than

Compare A and Meml, Do next if A Meml

≠

If B Not Equal

Do next if lower 4 bits of B Imm

←

Reg

Decrement Reg., Skip if Zero

Set BIT

Reg Reg − 1, Skip if Reg = 0

#

,Mem

1 to bit, Mem (bit = 0 to 7 immediate)

0 to bit, Mem

Reset BIT

#

IF BIT

If bit , A or Mem is true do next instruction

Reset PeNDing Flag

EXchange A with Memory

EXchange A with Memory [X]

LoaD A with Memory

LoaD A with Memory [X]

LoaD B with Immed.

LoaD Memory Immed.

LoaD Register Memory Immed.

EXchange A with Memory [B]

EXchange A with Memory [X]

LoaD A with Memory [B]

LoaD A with Memory [X]

LoaD Memory [B] Immed.

CLeaR A

Reset Software Interrupt Pending Flag

↔

←

A,Mem

A,[X]

A

B

Mem

[X]

X

LD

A,Meml

A,[X]

Meml

[X]

LD

B,Imm

Imm

←

Mem Imm

LD

Mem,Imm

Reg,Imm

←

Reg Imm

LD

↔

←

±

X

A, [B

A, [X

]

A

[B], (B

[X], (X

B

X

B

1)

←

X

←

±

LD

A, [B ]

[B], (B

←

±

LD

A, [X ]

[X], (X X 1)

←

±

LD

[B ],Imm

[B] Imm, (B B 1)

←

0

CLR

A

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50

14.0 Instruction Set (Continued)

←

→

←

INC

A

INCrement A

A

C

A + 1

DEC

LAID

DCOR

RRC

RLC

SWAP

SC

DECrement A

A − 1

Load A InDirect from ROM

Decimal CORrect A

Rotate A Right thru C

Rotate A Left thru C

SWAP nibbles of A

Set C

ROM (PU,A)

A

BCD correction of A (follows ADC, SUBC)

→

←

→

←

→

A0 C

A7

…

←

A0 C, HC A0

↔

A7…A4 A3…A0

←

C

1, HC

0, HC

1

0

RC

Reset C

IFC

IF C

IF C is true, do next instruction

IFNC

POP

PUSH

VIS

IF Not C

If C is not true, do next instruction

← ←

SP SP + 1, A [SP]

A

POP the stack into A

PUSH A onto the stack

Vector to Interrupt Service Routine

Jump absolute Long

Jump absolute

←

[SP] A, SP SP − 1

←

PU [VU], PL [VL]

←

PC ii (ii = 15 bits, 0 to 32k)

JMPL

JMP

JP

Addr.

Disp.

Addr.

←

PC9…0 i (i = 12 bits)

←

PC PC + r (r is −31 to +32, except 1)

Jump relative short

Jump SubRoutine Long

Jump SubRoutine

Jump InDirect

← ← ←

[SP] PL, [SP−1] PU,SP−2, PC ii

JSRL

JSR

←

[SP] PL, [SP−1] PU,SP−2, PC9…0 i

←

PL ROM (PU,A)

JID

← ←

SP + 2, PL [SP], PU [SP−1]

RET

RETSK

RETurn from subroutine

RETurn and SKip

←

SP + 2, PL [SP],PU [SP−1],

skip next instruction

←

RETI

INTR

NOP

RETurn from Interrupt

Generate an Interrupt

No OPeration

SP + 2, PL [SP],PU [SP−1],GIE 1

←

[SP] PL, [SP−1] PU, SP−2, PC 0FF

←

PC PC + 1

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Instructions Using A & C

14.0 Instruction Set (Continued)

CLRA

1/1

1/3

1/1

1/3

2/2

14.7 INSTRUCTION EXECUTION TIME

INCA

Most instructions are single byte (with immediate addressing

mode instructions taking two bytes).

DECA

Most single byte instructions take one cycle time to execute.

LAID

Skipped instructions require x number of cycles to be

skipped, where x equals the number of bytes in the skipped

instruction opcode.

DCORA

RRCA

RLCA

See the BYTES and CYCLES per INSTRUCTION table for

details.

SWAPA

SC

Bytes and Cycles per Instruction

RC

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

IFC

Arithmetic and Logic Instructions

IFNC

PUSHA

POPA

[B]

1/1

Direct

3/4

Immed.

2/2

ADD

ADC

SUBC

AND

OR

ANDSZ

3/4

2/2

Transfer of Control Instructions

3/4

2/2

3/4

2/2

JMPL

JMP

JP

3/4

2/3

1/3

3/5

2/5

1/3

1/5

1/7

1/1

3/4

2/2

XOR

IFEQ

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

3/4

2/2

3/4

2/2

JSRL

JSR

3/4

2/2

JID

1/3

3/4

VIS

1/1

RET

RETSK

RETI

INTR

NOP

RPND

1/1

Memory Transfer Instructions

Register

Indirect

Direct Immed.

Register Indirect

Auto Incr. & Decr.

[B]

[X]

1/3

[B+, B−]

1/2

[X+, X−]

1/3

X A, (Note 18)

LD A, (Note 18)

LD B, Imm

1/1

2/3

2/2

1/1

2/2

1/2

1/3

<

(If B 16)

>

(If B 15)

LD B, Imm

LD Mem, Imm

LD Reg, Imm

IFEQ MD, Imm

2/2

3/3

2/3

3/3

2/2

>

Memory location addressed by B or X or directly.

Note 18:

=

www.national.com

52

N i b b l e L o w e r

53

www.national.com

54

•

EWCOP8, EWCOP8-M, EWCOP8-BL: IAR - ANSI

15.0 Mask Options

C-Compiler and Embedded Workbench. (M version in-

cludes MetaLink debugger support) (BL version: 4k code

limit; no FP). A fully integrated Win32 IDE, ANSI

C-Compiler, macro assembler, editor, linker, librarian,

and C-Spy high-level simulator/debugger.

See Section 5.5 ECON (CONFIGURATION) REGISTER.

16.0 COP8 Tools Overview

National is engaged with an international community of in-

dependent 3rd party vendors who provide hardware and

software development tool support. Through National’s inter-

action and guidance, these tools cooperate to form a choice

of tools that fits each developer’s needs.

COP8 Development Productivity Tools

•

DriveWay-COP8: Aisys Corporation - COP8 Peripherals

Code Generation tool. Automatically generates tested

and documented C or Assembly source code modules

containing I/O drivers and interrupt handlers for each

on-chip peripheral. Application specific code can be in-

serted for customization using the integrated editor.

This section provides a summary of the tool and develop-

ment kits currently available. Up-to-date information, selec-

tion guides, free tools, demos, updates, and purchase infor-

mation can be obtained at our web site at:

www.national.com/cop8.

•

COP8-UTILS: COP8 assembly code examples, device

drivers, and utilities to speed up code development. (In-

cluded with COP8-NSDEV and COP8-NSEVAL.)

16.1 SUMMARY OF TOOLS

COP8 Hardware Debug Tools

COP8 Evaluation Software and Reference Designs

•

COP8-EM-xx: Metalink COP8 Emulation Module for

OTP/ROM COP8 Families. Windows based development

and real-time in-circuit emulation tool, with 100 frame

trace, 32k s/w breaks, Enhanced User Interface, Met-

aLink Debugger. Includes COP8-NSDEV, power supply,

DIP emulation cables.

•

COP8–NSEVAL: Software Evaluation package for Win-

dows. A fully integrated evaluation environment for

COP8. Includes WCOP8 IDE evaluation version (Inte-

grated Development Environment), COP8-NSASM (Full

COP8 Assembler), COP8-MLSIM (COP8 Instruction

™

Level Simulator), COP8C Compiler Demo, DriveWay

COP8 Device-Driver-Builder Demo, Manuals, Applica-

tions Software, and other COP8 technical information.

•

COP8-DM-xx: Metalink COP8 Debug Module for

OTP/ROM COP8 Families. Windows based development

and real-time in-circuit emulation tool, with 100 frame

trace, 32k s/w breaks, Basic User Interface, MetaLink

Debugger, and COP8 OTP Programmer with sockets.

Includes COP8-NSDEV, power supply, DIP and/or SMD

emulation cables and adapters.

COP8-IM: MetaLink iceMASTER^®for OTP/ROM COP8

devices. Windows based, full featured real-time in-circuit

emulator, with 4k trace, 32k s/w breaks, and MetaLink

Windows Debugger. Includes COP8-NSDEV and power

supply. Package-specific probes and surface mount

adaptors are ordered separately. (Add COP8-PM and

adapters for OTP programming.)

•

COP8–REF-xx: Reference Designs for COP8 Families.

Realtime hardware environment with a variety of func-

tions for demonstrating the various capabilities and fea-

tures of specific COP8 device families. Run Win 95 demo

reference software and exercise specific device capabili-

ties.

•

COP8 Starter Kits and Hardware Target Solutions

•

COP8-EVAL-xxx: A variety of Multifunction Evaluation,

Design Test, and Target Boards for COP8 Families. Re-

altime target design environments with a selection of

peripherals and features including multi I/O, LCD display,

keyboard, A/D, D/A, EEPROM, USART, LEDs, and

bread-board area. Quickly design, test, and implement a

custom target system (some target boards are stand-

alone, and ready for mounting into a standard enclosure),

or just evaluate and test your code.

COP8 Development and OTP Programming Tools

•

COP8-PM: COP8 Development Programming Module.

Windows programming tool for COP8 OTP/Flash Fami-

lies. Includes 40 DIP programming socket, control soft-

ware, RS232 cable, and power supply. (Programming

adapters are extra.)

COP8 Software Development Languages and Integrated

Environments

•

Development: Metalink’s Debug Module includes devel-

opment device programming capability for COP8 de-

vices. Many other third-party programmers are approved

for development and engineering use.

•

COP8-NSDEV: National’s COP8 Software Development

package for Windows on CD. A fully Integrated Develop-

ment Environment for COP8. Includes a fully licensed

WCOP8 IDE, COP8-NSASM. Plus Manuals, Applications

Software, and other COP8 technical information.

•

Production: Third-party programmers and automatic

handling equipment cover needs from engineering proto-

type and pilot production, to full production environments.

•

COP8C: ByteCraft - C Cross-Compiler and Code Devel-

opment System. Includes BCLIDE (Integrated Develop-

ment Environment) for Win32, editor, optimizing C Cross-

Compiler, macro cross assembler, BC-Linker, and

MetaLinktools support. (DOS/SUN versions available.

Factory Programming: Factory programming available

for high-volume requirements.

55

www.national.com

16.0 COP8 Tools Overview (Continued)

16.2 TOOLS ORDERING NUMBERS FOR THE COP8SGx FAMILY DEVICES

The COP8-IM/400 ICE can be used for emulation with the limitation of 10 MHz emulation speed maximum. For full speed

COP8SGx emulation, use the 15 MHz COP8-DM-SG or COP8-EM-SG.

Note: The following order numbers apply to the COP8 devices in this datasheet only.

Vendor

Tools

COP8-NSEVAL

COP8-REF

Order Number

COP8-NSEVAL

Cost

VL

Notes

Order from web site.

Order from web site

COP8-REF-SG

COP8-EVAL-COB1

COP8-NSDEV

COP8-EM-SG

VL

M

COP8-EVAL

COP8-NSDEV

COP8-EM

Included in EM. Order CD from web site

Included p/s, 28/40 pin DIP target cable, manuals,

software

EM Target Cables COP8-EMC-44P

VL

L

44 PLCC Target Cable

and Converters

COP8-EMC-28CSP

COP8-EMA-xxSO

28 CSP Target Cable

L

DIP to SOIC Cable Converter

44 pin PLCC to 44 QFP Cable Converter

32k or 8k Eraseable/OTP devices

COP8-EMA-44QFP

COP8SGR7, COP8SGE7

L

Development

Devices

VL

COP8-PM

COP8-PM-00

L

Included p/s, manuals, software, 16/20/28/40 DIP/SO

and 44 PLCC programming socket; add OTP adapter

or target adapter (if needed)

OTP Programming COP8-PGMA-44QFP

L

For programming 44 QFP on any programmer

For programming 28 CSP on any programmer

For programming 44 CSP on any programmer

For programming 16/20/28 SOIC on any programmer

Included p/s (PS-10), target cables (DIP and PLCC),

16/20/28/40 DIP/SO and 44 PLCC programming

sockets. Add OTP adapter (if needed) and target

adapter (if needed)

Adapters

COP8-PGMA-28CSP

COP8-PGMA-44CSP

COP8-PGMA-28SO

DM5-KCOP8-SG

L

VL

M

MetaLink COP8-DM

DM Target

Adapters

MHW-CNVxx (xx = 33, 34

etc.)

L

DM target converters for

16DIP/20SO/28SO/44QFP/28CSP; (i.e. MHW-CNV38

for 20 pin DIP to SO package converter)

For programming 16/20/28 SOIC and 44 PLCC on the

EPU

OTP Programming MHW-COP8-PGMA-DS

Adapters

MHW-COP8-PGMA-44QFP L

MHW-COP8-PGMA-28CSP L

For programming 44 QFP on any programmer

For programming 28 CSP on any programmer

Base unit 10 MHz; -220 = 220V; add probe card

(required) and target adapter (if needed); included

software and manuals

COP8-IM

IM-COP8-AD-464 (-220)

(10 MHz maximum)

H

IM Probe Card

PC-COP8SG44PW-AD-10

PC-COP8SG40DW-AD-10

M

10 MHz 44 PLCC probe card; 2.5V to 6.0V

10 MHz 40 DIP probe card; 2.5V to 6.0V

16 or 20 or 28 pin SOIC adapter for probe card

IM Probe Target

Adapters

MHW-SOICxx (xx = 16, 20, L

28)

MHW-CONV33

L

44 pin QFP adapter for 44 PLCC probe card

Included in DM and EM

KKD

IAR

WCOP8-IDE

EWCOP8-xx

COP8C

WCOP8-IDE

VL

See summary above

COP8C COP8CWIN

L - H Included all software and manuals

Byte

Craft

M

Included all software and manuals

Aisys DriveWay COP8

DriveWay COP8

Go to:

L

Included all software and manuals

L - H A wide variety world-wide

OTP Programmers

www.national.com/cop8

<

Cost: Free; VL = $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k

www.national.com

56

16.0 COP8 Tools Overview (Continued)

16.3 WHERE TO GET TOOLS

Tools can be ordered directly from National, National’s e-store, a National Distributor, or from the tool vendor. Go to the vendor’s

web site for current listings of distributors.

Vendor

Home Office

421 King Street North

Waterloo, Ontario

Canada N2J 4E4

Tel: 1-(519) 888-6911

Fax: (519) 746-6751

PO Box 23051

Electronic Sites

www.bytecraft.com

Other Main Offices

Byte Craft Limited

Distributors Worldwide

@

info bytecraft.com

IAR Systems AB

www.iar.se

USA:: San Francisco

Tel: +1-415-765-5500

Fax: +1-415-765-5503

UK: London

@

info iar.se

S-750 23 Uppsala

Sweden

@

info iar.com

@

info iarsys.co.uk

Tel: +46 18 16 78 00

Fax +46 18 16 78 38

@

info iar.de

Tel: +44 171 924 33 34

Fax: +44 171 924 53 41

Germany: Munich

Tel: +49 89 470 6022

Fax: +49 89 470 956

USA:

KANDA Systems

LTD.

Unit 17 -18

www.kanda.com

@

Glanyrafon Enterprise Park,

Aberystwyth, Ceredigion,

SY23 3JQ, UK

support kanda.com

Tel: 800-331-7766

Fax: 303-456-2404

@

usasupport kanda.com

@

K and K

Kaergaardsvej 42 DK-8355

Solbjerg Denmark Fax:

+45-8692-8500

www.kkd.dk kkd kkd.dk

Development ApS

National

2900 Semiconductor Dr.

Santa Clara, CA 95051

USA

www.national.com/cop8

Europe:

@

Semiconductor

support nsc.com

Tel: 49(0) 180 530 8585

Fax: 49(0) 180 530 8586

Hong Kong:

@

europe.support nsc.com

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Distributors Worldwide

The following companies have approved COP8 programmers in a variety of configurations. Contact your vendor’s local office or

distributor and request a COP8FLASH update. You can link to their web sites and get the latest listing of approved programmers

at: www.national.com/cop8.

Advantech; American Reliance; BP Microsystems; Data I/O; Dataman; EE Tools, Hi-Lo Systems; ICE Technology; KANDA, Lloyd

Research; Logical Devices; Minato; MQP; Needhams; Phyton; SMS(Data I/O); Stag Programmers; System General; and Tribal

Microsystems.

17.0 REVISION HISTORY

Date

Section

Summary of Changes

Added spec. for comparator enable time.

October 2001

Electrical Characteristics

Changed comparator response time to 600 ns.

Added note regarding comparator enable time.

Comparators

57

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

Chip Scale Package CSP

Order Number COP8SGR7HLQ8

NS Package Number LQA44A

Molded SO Wide Body Package (WM)

Order Number COP8SGx528Mx,

NS Package Number M28B

www.national.com

58

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number COP8SGx728Nx

NS Package Number N28B

Molded Dual-In-Line Package (N)

Order Number COP8SGx540Nx

NS Package Number N40A

59

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

44-Lead EPROM Leaded Chip Carrier (EL)

Order Number COP8SGR744J3

NS Package Number EL44C

www.national.com

60

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number COP8SGx544Vx

NS Package Number V44A

61

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Plastic Quad Flat Package (VEJ)

Order Number COP8SGx544VEJx

NS Package Number VEJ44A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: support@nsc.com

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	COP8SGF828V9
厂家：	National Semiconductor
描述：	8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART 8位CMOS基于ROM和OTP微控制器具有8K到32K的内存，两个比较器和USART 比较器微控制器
文件：	总62页 (文件大小：910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

COP8SGF828V9 [NSC]

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