COP8TAB9EMW8_技术文档

February 2005

COP8TAB9/TAC9

8-Bit CMOS Flash Microcontroller with 2k Byte or 4k

Byte Memory

System Programming and reprogrammability. The ROM de-

vice is supported, in emulation, by this device.

1.0 General Description

The COP8TAB9/TAC9 Flash microcontrollers are highly in-

The lack of the Boot ROM and Flash Memory in the ROM

™

tegrated COP8 Feature core devices, with 2k or 4k Flash

device, prompts us to caution the user, utilizing the

COP8TAx9 Flash based devices during development for

applications to be produced using the COP8TAx5 ROM de-

vices, to ensure that code contains NO calls to Boot ROM

functions prior to submission for ROM generation. Instances

of the JSRB instruction in ROM based devices will be ex-

ecuted as a JSR instruction to a location in the first 256 bytes

of Program Memory.

memory and advanced features. These single-chip CMOS

devices are suited for applications requiring a full featured,

in-system reprogrammable controller with moderate memory

and low EMI. The same device is used for development,

pre-production and volume production with a range of COP8

software and hardware development tools.

A Masked ROM device (COP8TAB5/TAC5) has been devel-

oped and provides identical features except for the Boot

ROM and Flash Memory and related features such as In-

Device included in this datasheet:

Flash Program

Memory (kbytes)

RAM

(bytes)

128

I/O

Pins

Device

Packages

Temperature

COP8TAB9

COP8TAC9

2

4

16, 24 or 40

20 and 28 SOIC WIDE,

44 LLP

−40˚C to +85˚C

128

n ACCESS.Bus Synchronous Serial Interface (compatible

2.0 Features

™

with I2C and SMBus

)

KEY FEATURES

— Master Mode and Slave Mode

— Full Master Mode Capability

n 2k bytes or 4k bytes Flash Program Memory, with

Security Feature, organized in 512 byte pages that can

be erased or written individually

— Bus Speed Up To 400KBits/Sec

— Low Power Mode With Wake-Up Detection

— Optional 1.8V ACCESS.Bus Compatibility

n Eight multi-source vectored interrupts servicing:

— External Interrupt

n 128 bytes volatile RAM

n 2.25V – 2.75V In-System Programmability of Flash

n High endurance - 20k Erase/Write Cycles

n Superior Data Retention - 100 years

n Crystal Oscillator at 15 MHz or Integrated RC Oscillator

at 10MHz

n Clock Prescaler For Adjusting Power Dissipation to

Processing Requirements

n Power-On Reset

n HALT/IDLE Power Save Modes

n One 16-bit timer:

— Processor Independent PWM mode

— External Event counter mode

— Idle Timer T0

— One Timers (with 2 interrupts)

— MICROWIRE/PLUS Serial peripheral interface

— ACCESS.Bus/I²C/SMBus compatible Synchronous

Serial Interface

— Multi-Input Wake-Up

— Software Trap

n Idle Timer with programmable interrupt interval

n 8-bit Stack Pointer SP (stack in RAM)

n Two 8-bit Register Indirect Data Memory Pointers

n True bit manipulation

— Input Capture mode

n WATCHDOG and Clock Monitor logic

n Software selectable I/O options

— TRI-STATE Output/High Impedance Input

— Push-Pull Output

n High Current I/Os

@

— 10 mA 0.4V

OTHER FEATURES

n Single supply operation:

— Weak Pull Up Input

— 2.25V–2.75V (−40˚C to +85˚C)

n Quiet Design (low radiated emissions)

n Multi-Input Wake-Up with optional interrupts

n MICROWIRE/PLUS (Serial Peripheral Interface

Compatible)

n Schmitt trigger inputs on I/O ports

n Temperature range: –40˚C to +85˚C

n Packaging: 20 and 28 SOIC and 44 LLP

COP8^®is a registered trademark of National Semiconductor Corporation.

2

I

C^®is a registered trademark of Phillips Corporation.

SMBus is a trademark of Intel Corporation.

DS200475

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3.0 Block Diagram

20047501

4.0 Ordering Information

Part Numbering Scheme

COP8

TA

C

9

H

LQ

8

Family and

Feature Set

Indicator

Program

Memory

Size

Program

Memory

Type

Package

Type

No. Of Pins

Temperature

B = 2k

C = 4k

5 = Masked ROM C = 20 Pin

LQ = LLP

MW = SOIC WIDE

8 = -40 to +85˚C

9 = Flash

E = 28 Pin

H = 44 Pin

Note: The user, utilizing the COP8TAx9 Flash based devices during devel-

opment for applications to be produced using the COP8TAx5 ROM

devices, is cautioned to ensure that code contains NO calls to Boot

ROM functions prior to submission for ROM generation. Instances of

the JSRB instruction in ROM based devices will be executed as a JSR

instruction to a location in the first 256 bytes of Program Memory.

Flash and ROM devices are not 100% identical. The execution of the

JSRB instruction is an example of the potential differences between

the devices. For this reason, the user is strongly advised to obtain a

masked ROM prototype devices before committing to production

quantities. This will allow the user to ensure there are no unexpected

differences between Flash an ROM devices within the application.

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Table of Contents

1.0 General Description ..................................................................................................................................... 1

2.0 Features ....................................................................................................................................................... 1

3.0 Block Diagram .............................................................................................................................................. 2

4.0 Ordering Information .................................................................................................................................... 2

5.0 Connection Diagrams ................................................................................................................................... 6

6.0 Architectural Overview ................................................................................................................................. 8

6.1 EMI REDUCTION ...................................................................................................................................... 8

6.2 IN-SYSTEM PROGRAMMING .................................................................................................................. 8

6.3 TRUE IN-SYSTEM EMULATION .............................................................................................................. 8

6.4 ARCHITECTURE ..................................................................................................................................... 8

6.5 INSTRUCTION SET ................................................................................................................................. 8

6.5.1 Key Instruction Set Features ............................................................................................................... 8

6.5.2 Single Byte/Single Cycle Code Execution ......................................................................................... 8

6.5.3 Many Single-Byte, Multi-Function Instructions .................................................................................... 8

6.5.4 Bit-Level Control .................................................................................................................................. 8

6.5.5 Register Set ......................................................................................................................................... 9

6.6 PACKAGING/PIN EFFICIENCY ................................................................................................................ 9

7.0 Absolute Maximum Ratings ....................................................................................................................... 10

8.0 Electrical Characteristics ............................................................................................................................ 10

9.0 Pin Descriptions ......................................................................................................................................... 13

9.1 EMULATION CONNECTION ................................................................................................................... 15

10.0 Functional Description .............................................................................................................................. 15

10.1 CPU REGISTERS ................................................................................................................................. 15

10.2 PROGRAM MEMORY ........................................................................................................................... 16

10.3 DATA MEMORY .................................................................................................................................... 16

10.4 OPTION REGISTER ............................................................................................................................. 16

10.5 SECURITY ............................................................................................................................................ 17

10.6 RESET ................................................................................................................................................... 17

10.6.1 External Reset ................................................................................................................................. 18

10.6.2 On-Chip Power-On Reset ................................................................................................................ 18

10.7 OSCILLATOR CIRCUITS ...................................................................................................................... 18

10.7.1 R/C Oscillator ................................................................................................................................... 19

10.7.2 Crystal Oscillator .............................................................................................................................. 20

10.7.3 External Oscillator ............................................................................................................................ 20

10.7.4 Clock Prescaler ................................................................................................................................ 20

10.8 CONTROL REGISTERS ....................................................................................................................... 20

10.8.1 CNTRL Register (Address X'00EE) ................................................................................................. 20

10.8.2 PSW Register (Address X'00EF) ..................................................................................................... 20

10.8.3 ICNTRL Register (Address X'00E8) ................................................................................................ 21

10.8.4 ITMR Register (Address X'00CF) .................................................................................................... 21

11.0 In-System Programming ........................................................................................................................... 21

11.1 INTRODUCTION ................................................................................................................................... 21

11.2 FUNCTIONAL DESCRIPTION .............................................................................................................. 21

11.3 REGISTERS .......................................................................................................................................... 21

11.3.1 ISP Address Registers ..................................................................................................................... 21

11.3.2 ISP Read Data Register .................................................................................................................. 22

11.3.3 ISP Write Data Register ................................................................................................................... 22

11.3.4 ISP Write Timing Register ................................................................................................................ 22

11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM ..................... 23

11.5 FORCED EXECUTION FROM BOOT ROM ......................................................................................... 23

11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET ....................................................... 23

11.7 MICROWIRE/PLUS ISP ........................................................................................................................ 23

12.0 Timers ....................................................................................................................................................... 25

12.1 TIMER T0 (IDLE TIMER) ...................................................................................................................... 25

12.1.1 ITMR Register .................................................................................................................................. 25

12.2 TIMER T1 .............................................................................................................................................. 26

12.3 MODE 1. PROCESSOR INDEPENDENT PWM MODE ....................................................................... 26

12.4 MODE 2. EXTERNAL EVENT COUNTER MODE ................................................................................ 26

12.5 MODE 3. INPUT CAPTURE MODE ..................................................................................................... 27

12.6 TIMER CONTROL FLAGS .................................................................................................................... 28

13.0 Power Save Modes .................................................................................................................................. 28

13.1 HALT MODE .......................................................................................................................................... 28

3

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Table of Contents (Continued)

13.2 IDLE MODE ........................................................................................................................................... 29

13.3 MULTI-INPUT WAKE-UP ...................................................................................................................... 30

14.0 Interrupts .................................................................................................................................................. 31

14.1 INTRODUCTION ................................................................................................................................... 31

14.2 MASKABLE INTERRUPTS ................................................................................................................... 32

14.3 VIS INSTRUCTION ............................................................................................................................... 33

14.3.1 VIS Execution .................................................................................................................................. 34

14.4 NON-MASKABLE INTERRUPT ............................................................................................................ 35

14.4.1 Pending Flag .................................................................................................................................... 35

14.4.2 Software Trap .................................................................................................................................. 35

14.4.2.1 Programming Example: External Interrupt ................................................................................. 36

14.5 PORT C AND PORT L INTERRUPTS .................................................................................................. 37

14.6 INTERRUPT SUMMARY ....................................................................................................................... 37

15.0 WATCHDOG/Clock Monitor ..................................................................................................................... 37

15.1 CLOCK MONITOR ................................................................................................................................ 38

15.2 WATCHDOG/CLOCK MONITOR OPERATION .................................................................................... 38

15.3 WATCHDOG AND CLOCK MONITOR SUMMARY .............................................................................. 38

15.4 DETECTION OF ILLEGAL CONDITIONS ............................................................................................ 39

16.0 MICROWIRE/PLUS .................................................................................................................................. 39

16.1 MICROWIRE/PLUS OPERATION ......................................................................................................... 39

16.2 MICROWIRE/PLUS MASTER MODE OPERATION ............................................................................. 40

16.3 MICROWIRE/PLUS SLAVE MODE OPERATION ................................................................................ 40

16.4 ALTERNATE SK PHASE OPERATION AND SK IDLE POLARITY ...................................................... 40

17.0 ACCESS.Bus Interface ............................................................................................................................ 42

17.1 DATA TRANSACTIONS ........................................................................................................................ 42

17.1.1 Start and Stop .................................................................................................................................. 43

17.1.2 Acknowledge Cycle .......................................................................................................................... 43

17.1.3 Addressing Transfer Formats .......................................................................................................... 43

17.2 BUS ARBITRATION .............................................................................................................................. 43

17.3 POWER SAVE MODES ........................................................................................................................ 43

17.4 SDA AND SCL DRIVER CONFIGURATION ......................................................................................... 43

17.5 ACB SERIAL DATA REGISTER (ACBSDA) .......................................................................................... 44

17.6 ACB STATUS REGISTER (ACBST) ..................................................................................................... 44

17.7 ACB CONTROL STATUS REGISTER (ACBCST) ................................................................................ 44

17.8 ACB CONTROL 1 REGISTER (ACBCTL1) .......................................................................................... 44

17.9 ACB CONTROL REGISTER 2 (ACBCTL2) .......................................................................................... 45

17.10 ACB OWN ADDRESS REGISTER (ACBADDR) ................................................................................ 45

18.0 Memory Map ............................................................................................................................................ 45

19.0 Instruction Set .......................................................................................................................................... 46

19.1 INTRODUCTION ................................................................................................................................... 46

19.2 INSTRUCTION FEATURES .................................................................................................................. 46

19.3 ADDRESSING MODES ......................................................................................................................... 46

19.3.1 Operand Addressing Modes ............................................................................................................ 47

19.3.2 Tranfer-of-Control Addressing Modes .............................................................................................. 48

19.4 INSTRUCTION TYPES ......................................................................................................................... 48

19.4.1 Arithmetic Instructions ...................................................................................................................... 48

19.4.2 Transfer-of-Control Instructions ....................................................................................................... 48

19.4.3 Load and Exchange Instructions ..................................................................................................... 49

19.4.4 Logical Instructions .......................................................................................................................... 49

19.4.5 Accumulator Bit Manipulation Instructions ....................................................................................... 49

19.4.6 Stack Control Instructions ................................................................................................................ 49

19.4.7 Memory Bit Manipulation Instructions ............................................................................................. 49

19.4.8 Conditional Instructions ................................................................................................................... 49

19.4.9 No-Operation Instruction .................................................................................................................. 49

19.5 REGISTER AND SYMBOL DEFINITION .............................................................................................. 49

19.6 INSTRUCTION SET SUMMARY .......................................................................................................... 50

19.7 INSTRUCTION EXECUTION TIME ...................................................................................................... 51

20.0 Development Support ............................................................................................................................. 54

20.1 TOOLS ORDERING NUMBERS FOR THE COP8TA 2.5V FLASH FAMILY DEVICES ....................... 54

20.2 COP8 TOOLS OVERVIEW ................................................................................................................... 55

20.3 WHERE TO GET TOOLS ..................................................................................................................... 56

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Table of Contents (Continued)

21.0 Revision History ....................................................................................................................................... 57

22.0 Physical Dimensions ................................................................................................................................ 58

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5.0 Connection Diagrams

20047502

Top View

44 Pin LLP Package

See NS Package Number LQA44A

20047505

Top View

20 Pin Plastic SOIC WIDE Package

See NS Package Number M20B

20047504

Top View

28 Pin Plastic SOIC WIDE Package

See NS Package Number M28B

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Pinouts for 44-, 20- and 28-Pin Packages

In System

Port

Type

Alt. Function

Emulation

Mode

44-Pin LLP^a

28-Pin SOIC^a20-Pin SOIC^a

L0

L1

L2

L3

L4

L5

L6

L7

I/O

I

MIWU/SDA

MIWU/SCL

MIWU

INT

12

13

14

15

20

21

22

23

2

18

19

20

21

22

23

24

25

12

11

10

9

12

13

14

15

16

17

18

19

10

9

G0

G1

G2

G3

G4

G5

G6

G7

C0

C1

C2

C3

C4

C5

C6

C7

F0

Input

POUT

Output

Clock

WDOUT^a

1

T1B

44

43

32

33

34

35

37

38

39

40

16

17

18

19

4

8

T1A

7

SO

2

20

1

SK

3

SI

4

2

I

CKO

5

3

I/O

MIWU

14

15

16

17

F1

5

F2

6

F3

7

F4

8

F5

9

F6

10

11

24

25

26

27

28

29

30

31

42

41

36

3

F7

J0

26

27

28

1

J1

J2

J3

J4

J5

J6

J7

V_CC

GND

CKI

RESET

V_CC

8

7

6

5

GND

I

6

4

RESET

13

11

a. G1 operation as WDOUT is controlled by Option Register, bit 2.

7

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well-engineered products that compete in the marketplace.

Many of these issues can be addressed through the manner

in which a microcontroller’s instruction set handles process-

ing tasks. And that’s why the COP8 family offers a unique

and code-efficient instruction set - one that provides the

flexibility, functionality, reduced costs and faster time to mar-

ket that today’s microcontroller based products require.

6.0 Architectural Overview

6.1 EMI REDUCTION

The COP8TAB9/TAC9 devices incorporate circuitry that

guards against electromagnetic interference - an increasing

problem in today’s microcontroller board designs. National’s

patented EMI reduction technology offers low EMI clock

circuitry, gradual turn-on output drivers (GTOs) and internal

Icc smoothing filters, to help circumvent many of the EMI

issues influencing embedded control designs. National has

achieved 15 dB–20 dB reduction in EMI transmissions when

designs have incorporated its patented EMI reducing cir-

cuitry.

Code efficiency is important because it enables designers to

pack more on-chip functionality into less program memory

space (ROM, OTP or Flash). Selecting a microcontroller with

less program memory size translates into lower system

costs, and the added security of knowing that more code can

be packed into the available program memory space.

6.5.1 Key Instruction Set Features

6.2 IN-SYSTEM PROGRAMMING

The COP8 family incorporates a unique combination of in-

struction set features, which provide designers with optimum

code efficiency and program memory utilization.

The devices include a program in a boot ROM that provides

the capability, through the MICROWIRE/PLUS serial inter-

face, to erase, program and read the contents of the Flash

memory.

6.5.2 Single Byte/Single Cycle Code Execution

Additional routines are included in the boot ROM, which can

be called by the user program, to enable the user to custom-

ize in-system software update capability if MICROWIRE/

PLUS is not desired.

The efficiency is due to the fact that the majority of instruc-

tions are of the single byte variety, resulting in minimum

program space. Because compact code does not occupy a

substantial amount of program memory space, designers

can integrate additional features and functionality into the

microcontroller program memory space. Also, the majority

instructions executed by the device are single cycle, result-

ing in minimum program execution time. In fact, 77% of the

instructions are single byte single cycle, providing greater

code and I/O efficiency, and faster code execution.

The contents of the boot ROM have been defined by Na-

tional. Execution of code from the boot ROM is dependent

on the state of the FLEX bit in the Option Register on exit

from RESET. If the FLEX bit is a zero, the Flash Memory is

assumed to be empty and execution from the boot ROM

begins.

6.3 TRUE IN-SYSTEM EMULATION

6.5.3 Many Single-Byte, Multi-Function Instructions

On-chip emulation capability has been added which allows

the user to perform true in-system emulation using final

production boards and devices. This simplifies testing and

evaluation of software in real environmental conditions. The

user, merely by providing for a standard connector which can

be bypassed by jumpers on the final application board, can

provide for software and hardware debugging using actual

production units.

The COP8 instruction set utilizes many single-byte, multi-

function instructions. This enables a single instruction to

accomplish multiple functions, such as DRSZ, DCOR, JID,

LD (Load) and

X (Exchange) instructions with post-

incrementing and post-decrementing, to name just a few

examples. In many cases, the instruction set can simulta-

neously execute as many as three functions with the same

single-byte instruction.

JID: (Jump Indirect); Single byte instruction decodes exter-

nal events and jumps to corresponding service routines

(analogous to “DO CASE” statements in higher level lan-

guages).

6.4 ARCHITECTURE

The COP8 family is based on a modified Harvard architec-

ture, which allows data tables to be accessed directly from

program memory. This is very important with modern

microcontroller-based applications, since program memory

is usually ROM or EPROM, while data memory is usually

RAM. Consequently constant data tables need to be con-

tained in non-volatile memory, so they are not lost when the

microcontroller is powered down. In a modified Harvard ar-

chitecture, instruction fetch and memory data transfers can

be overlapped with a two stage pipeline, which allows the

next instruction to be fetched from program memory while

the current instruction is being executed using data memory.

This is not possible with a Von Neumann single-address bus

architecture.

LAID: (Load Accumulator-Indirect); Single byte look up table

instruction provides efficient data path from the program

memory to the CPU. This instruction can be used for table

lookup and to read the entire program memory for checksum

calculations.

RETSK: (Return Skip); Single byte instruction allows return

from subroutine and skips next instruction. Decision to

branch can be made in the subroutine itself, saving code.

AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These

instructions use the two memory pointers B and X to effi-

ciently process a block of data (simplifying “FOR NEXT” or

other loop structures in higher level languages).

The COP8 family supports a software stack scheme that

allows the user to incorporate many subroutine calls. This

capability is important when using High Level Languages.

With a hardware stack, the user is limited to a small fixed

number of stack levels.

6.5.4 Bit-Level Control

Bit-level control over many of the microcontroller’s I/O ports

provides a flexible means to ease layout concerns and save

board space. All members of the COP8 family provide the

ability to set, reset and test any individual bit in the data

memory address space, including memory-mapped I/O ports

and associated registers.

6.5 INSTRUCTION SET

In today’s 8-bit microcontroller application arena cost/

performance, flexibility and time to market are several of the

key issues that system designers face in attempting to build

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8

troller users try to avoid using large packages to get the I/O

needed. Large packages take valuable board space and

increase device cost, two trade-offs that microcontroller de-

signs can ill afford.

6.0 Architectural Overview (Continued)

6.5.5 Register Set

Three memory-mapped pointers handle register indirect ad-

dressing and software stack pointer functions. The memory

data pointers allow the option of post-incrementing or post-

decrementing with the data movement instructions (LOAD/

EXCHANGE). Fifteen (15) memory-mapped registers allow

designers to optimize the precise implementation of certain

specific instructions.

The COP8 family offers a wide range of packages to mni-

mize the need for unused pins.

6.6 PACKAGING/PIN EFFICIENCY

Real estate and board configuration considerations demand

maximum space and pin efficiency, particularly given today’s

high integration and small product form factors. Microcon-

9

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7.0 Absolute Maximum Ratings (Note

Total Current into V_CCPin (Source)

Total Current out of GND Pin

(Sink)

80 mA

1)

60 mA

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range

−65˚C to +140˚C

Note 1: Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

Supply Voltage (V_CC

)

3.5V

Voltage at Any Pin

−0.3V to V_CC+0.3V

ESD Protection Level

(Human Body Model)

(Machine Model)

2 kV

200V

8.0 Electrical Characteristics

DC Electrical Characteristics −40˚C ≤ T_A≤ +85˚C unless otherwise specified.

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter

Conditions

Min

Typ

Max

Units

Operating Voltage

2.25

2.75

V

Power Supply Rise Time from 0.0V

(On-Chip Power-On Reset Selected)

Power Supply Ripple (Note 3)

Supply Current (Note 4)

20 µs

10 ms

Peak-to-Peak

0.1 V_CC

V

CKI = 15 MHz

V_CC= 2.75V, t_C= 0.65µs

V_CC= 2.75V, t_C= 2.0 µs

V_CC= 2.75V, CKI = 0

MHz

6

3

mA

CKI = 5MHz

HALT Current (Note 5) —WATCHDOG Disabled

T_A=25˚C

2

15

µA

T_A=85˚C

100

IDLE Current (Note 4)

CKI = 15 MHz

V_CC= 2.75V, t_C= 0.65µs

V_CC= 2.75V, t_C= 2.0 µs

1

mA

CKI = 5MHz

0.8

Input Levels (V_IH, V_IL)

Logic High

L0 (SDA), L1 (SCL) and L2

1.8V compatibility option

selected and

1.4

V

ACCESS.Bus is enabled

All Other Inputs

0.8 V_CC

0.3

V

Logic Low

0.25 V_CC

2.5

Value of the Internal Bias Resistor

for the Crystal/Resonator Oscillator

Hi-Z Input Leakage (same as TRI-STATE output)

Input Pullup Current

1.0

MΩ

V_CC= 2.75V

−0.1

−15

0.1

+0.1

µA

V

V_CC= 2.75V, V_IN= 0V

−120

Port Input Hysteresis

Output Current Levels

Source (Weak Pull-Up)

V_CC= 2.25V, V_OH= 1.7V

V_CC= 2.25V, V_OL= 0.4V

−10

10

−80

µA

mA

Source (Push-Pull Mode)

Sink (Push-Pull Mode)

mA

Allowable Sink & Source Current per Pin

Maximum Input Current without Latchup

RAM Retention Voltage, Vr

Input Capacitance

16

200

TBD

8.5

mA

V

pF

Flash Endurance

20K

Erase/Write

Cycles

years

Flash Data Retention

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25˚C

100

10

8.0 Electrical Characteristics (Continued)

AC Electrical Characteristics −40˚C ≤ T_A≤ +85˚C unless otherwise specified.

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter

Conditions

Min

Typ

Max

15

Units

Oscillator Frequency

Crystal/Resonator, External

Internal R/C Oscillator

2.25V ≤ V_CC≤ 2.75V

MHz

%

9.0

R/C Oscillator Frequency Variation

Instruction Cycle Time (t_C)

30

Crystal/Resonator, External

Internal R/C Oscillator

2.25V ≤ V_CC≤ 2.75V

fr = Max

0.65

45

DC

µs

%

1.1

External CKI Clock Duty Cycle

Rise Time

55

12

8

fr = 10 MHz Ext Clock

ns

Fall Time

MICROWIRE Setup Time (t_UWS) Figure 1

MICROWIRE Hold Time (t_UWH) Figure 1

MICROWIRE Output Propagation Delay (t_UPD) Figure

1

20

150

MICROWIRE Maximum Shift Clock

Master Mode

750

1.5

kHz

Slave Mode

MHz

Input Pulse Width

Interrupt Input High Time (Note 2)

Interrupt Input Low Time

1

t_C

Timer Input High Time

1

t_C

Timer Input Low Time

1

t_C

Reset Pulse Width

0.5

200

20

µs

ms

Mass Erase Time

Page Erase Time

ACCESS.Bus Input signals (Note 6)

Bus Free Time Between Stop and Start Condition

(t_BUFi) Figure 2

t_SCLhigho

SCL Setup Time (t_CSTOsi) Figure 2

SCL Hold Time (t_CSTRhi) Figure 2

SCL Setup Time (t_CSTRsi) Figure 3

Data High Setup Time (t_DHCsi) Figure 3

Data Low Setup Time (t_DLCsi) Figure 2

SCL Low Time (t_SCLlowi) Figure 4

SCL High Time (t_SCLhighi) Figure 4

SDA Hold Time (t_SDAhi) Figure 4

SDA Setup Time (t_SDAsi) Figure 4

ACCESS.Bus Output Signals (Note 6)

Bus Free Time Between Stop and Start Condition

(t_BUFo) Figure 2

Before Stop Condition

After Start Condition

Before Start Condition

Before SCL Rising Edge (RE)

Before SCL RE

8

mclk

ns

8

2

After SCL Falling Edge (FE)

After SCL RE

12

0

After SCL FE

Before SCL RE

2

mclk

t_SCLhigho

SCL Setup Time (t_CSTOso) Figure 2

SCL Hold Time (t_CSTRho) Figure 3

SCL Setup Time (t_CSTRso) Figure 3

Data High Setup Time (t_DHCso) Figure 3

Data Low Setup Time (t_DLCso) Figure 2

SCL Low Time (t_SCLlowo) Figure 4

SCL High Time (t_SCLhigho) Figure 4

Before Stop Condition

After Start Condition

Before Start Condition

Before SCL RE

t_SCLhigho

16

Before SCL RE

After SCL FE

mclk

After SCL RE

16

11

www.national.com

8.0 Electrical Characteristics (Continued)

AC Electrical Characteristics −40˚C ≤ T_A≤ +85˚C unless otherwise specified. (Continued)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter

SDA Hold Time (t_SDAho) Figure 4

SDA Valid Time (t_SDAso) Figure 4

Conditions

After SCL FE

Before SCL RE

Min

7

Typ

Max

Units

mclk

7

Note 2: t = Instruction cycle time (Clock input frequency divided by 10).

C

<

Note 3: Maximum rate of voltage change must be 0.5 V/ms.

Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, inputs connected to V and outputs driven low but not connected

CC

to a load.

Note 5: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. CKI is TRI-STATE. Measurement of I HALT is done with device

DD

neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving

a load; all inputs tied to V ; WATCHDOG and clock monitor disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.

CC

2

Note 6: The ACCESS.Bus interface of the COP8TAB9/TAC9 device implements and meets the timings necessary for interface to the I C and SMBus protocols at

logic levels. The bus drivers are designed with open-drain outputs, as required for proper bidirectional operation. The device will not meet the AC timing and

current/voltage drive requirements of the full bus specifications.

20047582

FIGURE 1. MICROWIRE/PLUS Timing

20047583

FIGURE 2. ACB Start and Stop Condition Timing

www.national.com

12

8.0 Electrical Characteristics (Continued)

20047584

FIGURE 3. ACB Start Condition Timing

20047585

FIGURE 4. ACB Data Timing

speakers. This flexibility helps to ensure a cleaner design,

with fewer external components and lower costs. Below is

the general description of all available pins.

9.0 Pin Descriptions

The COP8TAB9/TAC9 I/O structure enables designers to

reconfigure the microcontroller’s I/O functions with a single

instruction. Each individual I/O pin can be independently

configured as output pin low, output high, input with high

impedance or input with weak pull-up device. A typical ex-

ample is the use of I/O pins as the keyboard matrix input

lines. The input lines can be programmed with internal weak

pull-ups so that the input lines read logic high when the keys

are all open. With a key closure, the corresponding input line

will read a logic zero since the weak pull-up can easily be

overdriven. When the key is released, the internal weak

pull-up will pull the input line back to logic high. This elimi-

nates the need for external pull-up resistors. The high cur-

rent options are available for driving LEDs, motors and

V_CCand GND are the power supply pins.

Users of the LLP package are cautioned to be aware that the

central metal area and the pin 1 index mark on the bottom of

the package may be internally connected to GND. See figure

below:

13

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C2 Multi-Input Wake-Up

C1 Multi-Input Wake-Up

C0 Multi-Input Wake-Up

9.0 Pin Descriptions (Continued)

Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O

ports. Pin G6 is always a general purpose Hi-Z input. All G

pins have Schmitt Triggers on their inputs. Pin G1 serves as

the dedicated WATCHDOG output with weak pull-up if

the WATCHDOG feature is selected by the Option regis-

ter. The pin is a general purpose I/O, if WATCHDOG

feature is not selected. If WATCHDOG feature is selected,

bit 1 of the Port G configuration and data register does not

have any effect on Pin G1 setup. Pin G7 is either input or

output depending on the oscillator option selected. With the

crystal oscillator option selected, G7 serves as the dedicated

output pin for the CKO clock output. With the internal R/C or

the external oscillator option selected, G7 serves as a gen-

eral purpose Hi-Z input pin and is also used to bring the

device out of HALT mode with a low to high transition on G7.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin (crystal clock option) or general purpose

input (R/C or external clock option), the associated bits in the

data and configuration registers for G6 and G7 are used for

special purpose functions as outlined below. Reading the G6

and G7 data bits will return zeros.

20047520

FIGURE 5. LLP Package Bottom View

CKI is the clock input. This pin can be connected (in con-

junction with CKO) to an external crystal circuit to form a

crystal oscillator, to an external resistor for RC oscillator

operation or to an external clock. See Oscillator Description

section.

The device will be placed in the HALT mode by writing a “1”

to bit 7 of the Port G Data Register. Similarly the device will

be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register

enables the MICROWIRE/PLUS to operate with the alter-

nate phase of the SK clock. The G7 configuration bit, if set

high, enables the clock start up delay after HALT when the

R/C clock configuration is used.

RESET is the master reset input. See Reset description

section.

The device contains up to five bidirectional 8-bit I/O ports (C,

F, G, J and L), where each individual bit may be indepen-

dently configured as an input (Schmitt trigger inputs on all

ports), output or TRI-STATE under program control. Three

data memory address locations are allocated for each of

these I/O ports. Each I/O port has three associated 8-bit

memory mapped registers, the CONFIGURATION register,

the output DATA register and the Pin input register. (See the

memory map for the various addresses associated with the

I/O ports.) Figure 6 shows the I/O port configurations. The

DATA and CONFIGURATION registers allow for each port bit

to be individually configured under software control as

shown below:

Config. Reg.

CLKDLY

Alternate SK

Data Reg.

HALT

IDLE

G7

G6

Port G has the following alternate features:

G7 CKO Oscillator dedicated output or general purpose

input.

G6 SI (MICROWIRE/PLUS Serial Data Input)

G5 SK (MICROWIRE/PLUS Serial Clock)

G4 SO (MICROWIRE/PLUS Serial Data Output)

G3 T1A (Timer T1 I/O)

CONFIGURATION

Register

DATA

Port Set-Up

Hi-Z Input

Register

0

G2 T1B (Timer T1 Capture Input)

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

G1 WDOUT WATCHDOG and/or Clock Monitor if WATCH-

DOG enabled, otherwise it is a general purpose I/O

0

1

0

1

G0 INTR (External Interrupt Input)

G0 through G3 are also used for In-System Emulation.

Port C supports the Multi-Input Wake-Up feature on all eight

pins. Port C is not available on 20 and 28 pin packages.

When using these packages, the user should ensure that

Port C Multi-Input Wake-Up is disabled by clearing the

CWKEN Register to prevent spurious interrupts and

wake-up events. Port C has the following alternate pin func-

tions:

Port J is an 8-bit I/O port. All J pins have Schmitt triggers on

the inputs. At RESET, Port J outputs are enabled and are

forced to the High state.

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on

the inputs.

Pins L0 (SDA), L1 (SCL) and L2 inputs provide compatibility

with 1.8V logic levels when LVCMP (Option Register bit 7) is

set and the ACCESS.Bus is enabled.

C7 Multi-Input Wake-Up

C6 Multi-Input Wake-Up

C5 Multi-Input Wake-Up

C4 Multi-Input Wake-Up

C3 Multi-Input Wake-Up

Port L supports the Multi-Input Wake-Up feature on all eight

pins. Port L has the following alternate pin functions:

L7 Multi-Input Wake-Up

L6 Multi-Input Wake-Up

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14

9.1 EMULATION CONNECTION

9.0 Pin Descriptions (Continued)

Connection to the emulation system is made via a 2 x 7

connector which interrupts the continuity of the RESET, G0,

G1, G2 and G3 signals between the COP8 device and the

rest of the target system (as shown in Figure 9). This con-

nector can be designed into the production pc board and can

be replaced by jumpers or signal traces when emulation is

no longer necessary. The emulator will replicate all functions

of G0 - G3 and RESET. For proper operation, no connection

should be made on the device side of the emulator connec-

tor.

L5 Multi-Input Wake-Up

L4 Multi-Input Wake-Up

L3 Multi-Input Wake-Up

L2 Multi-Input Wake-Up (optional 1.8V compatible input)

L1 Multi-Input Wake-Up or ACCESS.Bus Serial Clock (op-

tional 1.8V compatible input)

L0 Multi-Input Wake-Up or ACCESS.Bus Serial Data (op-

tional 1.8V compatible input)

20047560

FIGURE 6. I/O Port Configurations

20047509

FIGURE 9. Emulation Connection

10.0 Functional Description

The architecture of the device is a modified Harvard archi-

tecture. With the Harvard architecture, the program memory

(Flash) is separate from the data store memory (RAM). Both

Program Memory and Data Memory have their own separate

addressing space with separate address buses. The archi-

tecture, though based on the Harvard architecture, permits

transfer of data from Flash Memory to RAM.

20047561

FIGURE 7. I/O Port Configurations—Output Mode

10.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t_C) cycle time.

20047562

FIGURE 8. I/O Port Configurations—Input Mode

15

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10.2 PROGRAM MEMORY

10.0 Functional Description

The program memory consists of 4096 bytes of Flash

Memory. These bytes may hold program instructions or con-

stant data (data tables for the LAID instruction, jump vectors

for the JID instruction, and interrupt vectors for the VIS

instruction). The program memory is addressed by the 15-bit

program counter (PC). All interrupts in the device vector to

program memory location 00FF Hex. The program memory

reads 00 Hex in the erased state. Program execution starts

at location 0 after RESET.

(Continued)

There are five CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

If a Return instruction is executed when the SP contains 6F

(hex), instruction execution will continue from Program

Memory location 7FFF (hex). If location 7FFF is accessed by

an instruction fetch, the Flash Memory will return a value of

00. This is the opcode for the INTR instruction and will cause

a Software Trap.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). With reset, the SP is initialized to

RAM address 06F Hex. The SP is decremented as items are

pushed onto the stack. SP points to the next available loca-

tion on the stack.

For the purpose of erasing and rewriting the Flash Memory,

it is organized in pages of 512 bytes as shown in Table 1.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

TABLE 1. Available Memory Address Ranges

Program

Maximum

RAM

Address

(HEX)

Flash Memory

Memory

Option

Register

Address (Hex)

Data Memory

Size (RAM)

(Bytes)

RAM

Segments

Available

Device

Page Size

(Bytes)

Size

(Flash)(Bytes)

2048

COP8TAB9

COP8TAC9

0x07FF (hex)

0x0FFF (hex)

512

128

Segment 0

06F

4096

10.3 DATA MEMORY

The format of the Option register is as follows:

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

register, ACCESS.Bus Interface and the various registers

and counters associated with the timer, T1. Data memory is

addressed directly by the instruction or indirectly by the B, X

and SP pointers.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WATCH

DOG

LVCMP CLKSEL2 SEC CLKSEL1 CLKSEL0

HALT FLEX

Bit 7

Bit 6

When this bit is set and the ACCESS.Bus is en-

abled, inputs L0, L1 and L2, are compatible with

1.8V logic levels.

This bit defines the most significant bit of the os-

cillator selection. (See Section 10.7 OSCILLATOR

CIRCUITS) for more information on Oscillator

selection.)

The data memory consists of 128 bytes of RAM. Sixteen

bytes of RAM are mapped as “registers” at addresses 0F0 to

0FF Hex. These registers can be loaded immediately, and

also decremented and tested with the DRSZ (decrement

register and skip if zero) instruction. The memory pointer

registers X, SP and B are memory mapped into this space at

address locations 0FC to 0FE Hex respectively, with the

other registers being available for general usage.

Bit 5

= 1

Security enabled. Flash Memory read and write

are not allowed except in User ISP/Virtual E²com-

mands. Mass Erase is allowed.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumu-

lator (A) bits can also be directly and individually tested.

= 0

Security disabled. Flash Memory read and write

are allowed.

Bits 4, 3 These bits define the two least significant bits of

the oscillator selection.

Bit 2

Note: RAM contents are undefined upon power-up.

= 1

WATCHDOG feature disabled. G1 is a general

purpose I/O.

10.4 OPTION REGISTER

= 0

WATCHDOG feature enabled. G1 pin is

WATCHDOG output with weak pullup.

The Option register, located at address 0x0FFF (hex) or

0x07FF (hex) in the Flash Program Memory, is used to

configure the user selectable security, WATCHDOG, HALT

and Oscillator selection options. The register can be pro-

grammed only in external Flash Memory programming or

ISP Programming modes. Therefore, the register must be

programmed at the same time as the program memory. The

contents of the Option register shipped from the factory read

00 Hex.

Bit 1

= 1

= 0

HALT mode disabled.

HALT mode enabled.

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16

1, however the MICROWIRE/PLUS ISP routines require the

address FFFF (hex) to be used to read the Option Register

when the Flash Memory is secured.

10.0 Functional Description

(Continued)

Bit 0

The entire Option Register must be programmed at one time

and cannot be rewritten without first erasing the entire last

page of Flash Memory.

= 1

Execution following RESET will be from Flash

Memory.

= 0

Flash Memory is erased. Execution following RE-

SET will be from Boot ROM with the MICROWIRE/

PLUS ISP routines.

10.6 RESET

The device is initialized when the RESET pin is pulled low or

the On-chip Power-On Reset is activated.

The COP8 assembler defines a special ROM section type,

CONF, into which the Option Register data may be coded.

The Option Register is programmed automatically by pro-

grammers that are certified by National.

The user needs to ensure that the FLEX bit will be set when

the device is programmed.

The following examples illustrate the declaration of the Op-

tion Register.

Syntax:

20047521

[label:].sect

.db

config, conf

value ;1 byte,

FIGURE 10. Reset Logic

;configures

;options

The following occurs upon initialization:

.endsect

Port F: TRI-STATE (High Impedance Input)

Example: The following sets a value in the Option Register

and User Identification for a COP8TAC9HLQ7. The Option

Register bit values shown select options: Security disabled,

WATCHDOG enabled HALT mode enabled and execution

will commence from Flash Memory.

Port G: TRI-STATE (High Impedance Input). Exceptions:

If Watchdog is enabled, then G1 is Watchdog output. G0

and G2 have their weak pull-up enabled during RESET.

Port J: Output High

Port L: TRI-STATE (High Impedance Input)

PC: CLEARED to 0000

.chip

.sect

.db

8TAC

option, conf

0x01

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR:

;wd, halt, flex

.endsect

...

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

ITMR, CLKPS: Cleared

.end

start

Note: All programmers certified for programming this family

of devices will support programming of the Option Register.

Please contact National or your device programmer supplier

for more information.

Accumulator and Timer 1:

RANDOM after RESET

CWKEN, CWKEDG, LWKEN, LWKEDG: CLEARED

CWKPND, LWKPND: RANDOM

SP (Stack Pointer):

10.5 SECURITY

The device has a security feature which, when enabled,

prevents external reading of the Flash program memory. The

security bit in the Option Register determines, whether se-

curity is enabled or disabled. If the security feature is dis-

abled, the contents of the internal Flash Memory may be

read by external programmers or by the built in

MICROWIRE/PLUS serial interface ISP. Security must be

enforced by the user when the contents of the Flash

Memory are accessed via the user ISP.

Initialized to RAM address 06F Hex

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

ISP CONTROL:

If the security feature is enabled, then any attempt to exter-

nally read the contents of the Flash Memory will result in the

value FF (hex) being read from all program locations (except

the Option Register). In addition, with the security feature

enabled, the write operation to the Flash program memory

and Option Register is inhibited. Page Erases are also inhib-

ited when the security feature is enabled. The Option Reg-

ister is readable regardless of the state of the security bit by

accessing location FFFF (hex). Mass Erase Operations are

possible regardless of the state of the security bit.

ISPADLO: CLEARED

ISPADHI: CLEARED

PGMTIM: PRESET TO VALUE FOR 10 MHz CKI

WATCHDOG (if enabled):

The device comes out of reset with both the WATCHDOG

logic and the Clock Monitor detector armed, with the

WATCHDOG service window bits set and the Clock Moni-

tor bit set. The WATCHDOG and Clock Monitor circuits

are inhibited during reset. The WATCHDOG service win-

dow bits being initialized high default to the maximum

WATCHDOG service window of 64k T0 clock cycles. The

Clock Monitor bit being initialized high will cause a Clock

The security bit can be erased only by a Mass Erase of the

entire contents of the Flash unless Flash operation is under

the control of User ISP functions.

Note: The actual memory address of the Option Register is

dependent on the Flash Memory size and is defined in Table

17

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t_C. After the underflow, the logic is designed such that the

Power On Reset circuit will generate no additional internal

resets as long as V_CCremains above 2.0V.

10.0 Functional Description

(Continued)

Note: The POR feature of the COP8TAB9/TAC9 is not intended to function as

a brownout detector. A brownout condition is reached whenever VCC

of the device goes below the minimum guaranteed operating condi-

tions. The minimum guaranteed operating conditions are defined in the

Electrical Specifications. We strongly recommend the use of an exter-

nal supervisory circuit which ensures that the COP8 device is held in

the RESET state until Vcc has recovered to the minimum operating

conditions as stated above.

Monitor error following reset if the clock has not reached

the minimum specified frequency at the termination of

reset. A Clock Monitor error will cause an active low output

on pin G1. This error output will continue until 16–32 T0

clock cycles following the clock frequency reaching the

minimum specified value, at which time the G1 output will

go high.

The contents of data registers and RAM are unknown fol-

lowing the on-chip reset.

10.6.1 External Reset

The RESET input, when pulled low, initializes the device.

The RESET pin must be held low for a minimum of one

instruction cycle to guarantee a valid reset. An R/C circuit on

the RESET pin with a delay 5 times (5x) greater than the

power supply rise time is recommended. Reset should also

be long enough to ensure crystal start-up upon Power-Up.

RESET may also be used to cause an exit from the HALT

mode.

Note: Flash memory may be non-volatile, but it is not invulnerable. Any

controller which features the capability for the software to modify the

contents of the Flash memory is susceptible to inadvertent writes or

erases any time V

is below the minimum guaranteed operating

CC

conditions, the clock is running and the device is not held in Reset. For

this reason, we recommend the use of external brownout detection

any time V

drops below the minimum guaranteed V /Frequency

CC

operating conditions.

A recommended reset circuit for this device is shown in

Figure 11.

20047523

FIGURE 12. Reset Timing (Power-On Reset Enabled)

with V_CCTied to RESET

20047522

10.7 OSCILLATOR CIRCUITS

There are five clock oscillator options available: fully internal

R/C Oscillator, R/C Oscillator with external frequency deter-

mination resistor, Crystal Oscillator with or without on-chip

bias resistor and External Oscillator. The oscillator feature is

selected by programming the Option Byte, which is summa-

rized in Table 2.

FIGURE 11. Reset Circuit Using External Reset

10.6.2 On-Chip Power-On Reset

The device generates an internal reset as V_CCrises to a

voltage level above 2.0V. The on-chip reset circuitry is able

to detect both fast and slow rise times on V_CC(V_CCrise time

between 20 µs and 10 ms).

TABLE 2. Oscillator Option

Under no circumstances should the RESET pin be allowed

to float. If the on-chip Power-On Reset feature is being used,

RESET pin should be connected to V_CC, either directly or

through a pull-up resistor. If forced operation from the Boot

ROM is anticipated, a pull-up resistor should always be used

so that the ISP circuit can override the RESET circuit and

force the RESET pin low. The output of the power-on reset

detector will always preset the Idle timer to 00FF(256 t_C). At

this time, the internal reset will be generated.

Option Option Option

Oscillator Option

Bit 6

Bit 4

Bit 3

0

1

0

1

0

On-Chip R/C Oscillator

R/C Oscillator with External Resistor

Crystal Oscillator with Internal Bias

Resistor

0

1

x

1

x

Crystal Oscillator with External Bias

Resistor

External Oscillator

The internal reset will not be turned off until the Idle timer

underflows. The internal reset will perform the same func-

tions as external reset. The user is responsible for ensuring

that V_CCis at the minimum level for operating within the 256

www.national.com

18

10.0 Functional Description

(Continued)

10.7.1 R/C Oscillator

The device features an R/C oscillator with two modes of

operation:

1. R/C with internal R operating at a fixed frequency (R/C

mode)

2. R/C with external frequency control resistor (R/C+R

mode).

If the Oscillator Selection bits of the Option Byte remain

unprogrammed (equal to zero), the internal R/C Oscillator

mode will be selected. In internal R/C oscillation mode, CKI

may be left unconnected, while G7/CKO is available as a

general purpose input G7 and/or HALT control. The internal

R/C oscillator has on-chip resistor and capacitor for prede-

termined R/C oscillator frequency operation. The predeter-

mined frequency is 10 MHz 20% for temperature range of

−40˚C to +85˚C.

20047525

FIGURE 14. Crystal Oscillator With External Bias

Resistor

The R/C Oscillator with external frequency control resistor

mode (R/C+R) can be selected by programming Option Bit 3

to 1 and Option Bits 6 and 4 to 0. In R/C+R mode, the

frequency of oscillation is controlled by the current through a

resistor connected from the CKI pin to GND. G7/CKO is

available as a general purpose input G7 and/or HALT con-

trol. The maximum frequency is 10 MHz 20% for tempera-

ture range of −40˚C to +85˚C. For lower frequencies, an

external resistor should be connected between CKI and

GND. PC board trace length on the CKI pin should be kept

as short as possible.

20047526

Table 3 shows the oscillator frequency as a function of

approximate external resistance on the CKI pin. Figure 16

shows the R/C oscillator configuration.

FIGURE 15. External Oscillator

TABLE 3. R/C+R Oscillator Configuration,

−40˚C to +85˚C,

OSC Freq. Variation of 20%

External Resistor

OSC Freq

Instr. Cycle

(µs)

(kΩ)

60

(MHz)

15

10

5

0.65

100

200

500

1.0

2.0

2

5.0

20047524

FIGURE 13. Crystal Oscillator With On-Chip Bias

Resistor

19

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10.0 Functional Description (Continued)

With External Frequency Control Resistor (R/C+R)

With Fully On-Chip R/C Oscillator.

20047527

20047528

FIGURE 16. R/C Oscillator

10.7.2 Crystal Oscillator

TABLE 5. Clock Prescale Register (CLKPS)

CLKPS

The Crystal Oscillator mode can be selected by program-

ming Option Bit 4 to 1. CKI is the clock input while G7/CKO

is the clock generator output to the crystal. An on-chip bias

resistor connected between CKI and CKO can be enabled

by programming Option Bit 3 to 0. The value of the resistor is

in the range of 0.3M to 2.5M (typically 1.0M).

Bit 7

Bit 0

10.8 CONTROL REGISTERS

10.8.1 CNTRL Register (Address X'00EE)

Table 4 shows the component values required for various

standard crystal values. Resistor R2 is only used when the

on-chip bias resistor is disabled. Figure 13 and Figure 14

show the crystal oscillator connection diagrams.

T1C3

Bit 7

T1C2

T1C1

T1C0

MSEL

IEDG

SL1

SL0

Bit 0

The Timer1 (T1) and MICROWIRE/PLUS control register

contains the following bits:

TABLE 4. Crystal Oscillator Configuration,

T_A= 25˚C, V_CC= 2.5V

T1C3

T1C2

T1C1

T1C0

Timer T1 mode control bit

R1 (kΩ) R2 (MΩ) C1 (pF) C2 (pF) CKI Freq. (MHz)

0

1

18

45

18

15

10

Timer T1 Start/Stop control in timer

modes 1 and 2. T1 Underflow Interrupt

Pending Flag in timer mode 3

0

30–36

4

5.6

100 100–156

0.455

MSEL

IEDG

Selects G5 and G4 as MICROWIRE/PLUS

signals SK and SO respectively

External interrupt edge polarity select

(0 = Rising edge, 1 = Falling edge)

10.7.3 External Oscillator

The External Oscillator mode can be selected by program-

ming Option Bit 3 to 0 and Option Bit 4 to 0. CKI can be

driven by an external clock signal provided it meets the

specified duty cycle, rise and fall times, and input levels.

G7/CKO is available as a general purpose input G7 and/or

Halt control. Figure 13 shows the external oscillator connec-

tion diagram.

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

by (00 = 2, 01 = 4, 1x = 8)

10.8.2 PSW Register (Address X'00EF)

HC

C

T1PNDA

T1ENA

EXPND

BUSY

EXEN

GIE

Bit 7

Bit 0

10.7.4 Clock Prescaler

The PSW register contains the following select bits:

The device is equipped with a programmable clock prescaler

which allows the user to dynamically adjust the clock speed,

and thus the power dissipation, to the processing needs of

the application. By merely writing an eight-bit value to the

CLKPS register, the user can divide the input oscillator clock

by an integer multiple (1—256) and reduce the CPU clock

frequency. The format of the CLKPS Register is shown in

Table 5. The value written to the CLKPS register is one less

than the desired divider. A value of 0 (zero) written to the

CLKPS register yields a CPU clock equal to the input clock

frequency. A value of 255 written to the CLKPS register

yields a CPU clock with a period equal to 256 input clock

periods.

HC

C

Half Carry Flag

Carry Flag

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA

in mode 1, T1 Underflow in Mode 2, T1A capture

edge in mode 3)

T1ENA Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

EXPND External interrupt pending

BUSY

EXEN

GIE

MICROWIRE/PLUS busy shifting flag

Enable external interrupt

Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that

affect the Carry flag. The SC (Set Carry) and RC (Reset

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20

10.0 Functional Description

(Continued)

Carry) instructions will respectively set or clear both the carry

flags. In addition to the SC and RC instructions, ADC, SUBC,

RRC and RLC instructions affect the Carry and Half Carry

flags.

10.8.3 ICNTRL Register (Address X'00E8)

Unused LPEN

Bit 7

T0PND

T0EN µWPND µWEN T1PNDB

T1ENB

Bit 0

The ICNTRL register contains the following bits:

LPEN

L/C Port Interrupt Enable (Multi-Input

Wake-Up/Interrupt)

T0PND Timer T0 Interrupt pending

20047529

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

µWPND MICROWIRE/PLUS interrupt pending

FIGURE 17. Block Diagram of ISP

µWEN

Enable MICROWIRE/PLUS interrupt

As described in Section 10.4 OPTION REGISTER, there is a

bit, FLEX, that controls whether the device exits RESET

executing from the Flash memory or the Boot ROM. The

user must program the FLEX bit as appropriate for the

application. In the erased state, the FLEX bit = 0 and the

device will power-up executing from Boot ROM. When FLEX

= 0, this assumes that either the MICROWIRE/PLUS ISP

routine or external programming is being used to program

the device. If using the MICROWIRE/PLUS ISP routine, the

software in the boot ROM will monitor the MICROWIRE/

PLUS for commands to program the Flash memory. When

programming the Flash program memory is complete, the

FLEX bit will have to be programmed to a 1 and the device

will have to be reset, either by pulling external Reset to

ground or by a MICROWIRE/PLUS ISP EXIT command,

before execution from Flash program memory will occur.

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture

edge

T1ENB Timer T1 Interrupt Enable for T1B Input capture

edge

10.8.4 ITMR Register (Address X'00CF)

RSVD

ITSEL2

ITSEL1 ITSEL0

Bit 0

Bit 7

The ITMR register contains the following bits:

RSVD These bits are reserved and must be 0.

ITSEL2 Idle Timer period select bit.

ITSEL1 Idle Timer period select bit.

ITSEL0 Idle Timer period select bit.

If FLEX = 1, upon exiting Reset, the device will begin ex-

ecuting from location 0000 in the Flash program memory.

The assumption, here, is that either the application is not

using ISP, is using MICROWIRE/PLUS ISP by jumping to it

within the application code, or is using a customized ISP

routine. If a customized ISP routine is being used, then it

must be programmed into the Flash memory by means of

the MICROWIRE/PLUS ISP or external programming as

described in the preceding paragraph.

11.0 In-System Programming

11.1 INTRODUCTION

This device provides the capability to program the program

memory while installed in an application board. This feature

is called In System Programming (ISP). It provides a means

of ISP by using the MICROWIRE/PLUS, or the user can

provide his own, customized ISP routine. The factory in-

stalled ISP uses the MICROWIRE/PLUS port. The user can

provide his own ISP routine that uses any of the capabilities

of the device, such as ACCESS.Bus, parallel port, etc. The

user is cautioned, however, to remove all calls to Boot ROM

functions prior to submission of code for ROM generation

and production in COP8TAx5 devices.

11.3 REGISTERS

There are six registers required to support ISP: Address

Register Hi byte (ISPADHI), Address Register Low byte

(ISPADLO), Read Data Register (ISPRD), Write Data Reg-

ister (ISPWR), Write Timing Register (PGMTIM), and the

Control Register (ISPCNTRL). The ISPCNTRL Register is

not available to the user. None of these six registers, which

support ISP, have been implemented in the COP8TAx5 ROM

based devices.

11.2 FUNCTIONAL DESCRIPTION

The organization of the ISP feature consists of the user

Flash program memory, the factory boot ROM, and some

registers dedicated to performing the ISP function. See Fig-

ure 17 for a simplified block diagram. The factory installed

ISP that uses MICROWIRE/PLUS is located in the Boot

ROM. The size of the Boot ROM is 1k bytes and also

contains code to facilitate in system emulation capability. If a

user chooses to write an application specific ISP routine, it

must be located in the Flash program memory.

11.3.1 ISP Address Registers

The address registers (ISPADHI & ISPADLO) are used to

specify the address of the byte of data being written or read.

For page erase operations, the address of the beginning of

the page should be loaded. For mass erase operations,

0000 must be placed into the address registers. When read-

ing the Option register, 07FF (hex) should be placed into the

address registers of COP8TAB9 devices and 0FFF (hex)

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11.3.3 ISP Write Data Register

11.0 In-System Programming

The Write Data Register (ISPWR) contains the data to be

written into the specified address. This register is undeter-

mined on Reset.

(Continued)

should be placed into the address registers of COP8TAC9

devices. Registers ISPADHI and ISPADLO are cleared to 00

on Reset.

TABLE 9. ISP Write Data Register

Note: The actual memory address of the Option Register is

0x0FFF (hex), however the MICROWIRE/PLUS ISP routines

require the address FFFF (hex) to be used to read the

Option Register when the Flash Memory is secured.

ISPWR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

11.3.4 ISP Write Timing Register

TABLE 6. High Byte of ISP Address

The Write Timing Register (PGMTIM) is used to control the

width of the timing pulses for write and erase operations. The

value to be written into this register is dependent on the

frequency of CKI and is shown in Table 10. This register

must be written before any write or erase operation can take

place. It only needs to be loaded once, for each value of CKI

frequency. The MICROWIRE/PLUS ISP routine that is resi-

dent in the boot ROM requires that this register be defined

prior to any access to the Flash memory. Refer to Section

11.7 MICROWIRE/PLUS ISP for more information on avail-

able ISP commands. On Reset, the PGMTIM register is

loaded with the value that corresponds to 10 MHz frequency

for CKI. The best choice for value of PGMTIM will center the

operating frequency in the CKI Frequency Range.

ISPADHi

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Addr 15 Addr 14 Addr 13 Addr 12 Addr 11 Addr 10 Addr 9 Addr 8

TABLE 7. Low Byte of ISP Address

ISPADLO

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Addr 7

Addr 6

Addr 5

Addr 4

Addr 3

Addr 2

Addr 1 Addr 0

11.3.2 ISP Read Data Register

The Read Data Register (ISPRD) contains the value read

back from a read operation. This register is undefined on

Reset.

TABLE 8. ISP Read Data Register

ISPRD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

TABLE 10. PGMTIM Register Format

PGMTIM

Register Bit

CKI Frequency Range

7

0

R

6

0

1

5

0

4

0

3

0

2

0

1

0

25 kHz–50 kHz

50 kHz–100 kHz

0

1

0

1

0

75 kHz–150 kHz

0

1

0

125 kHz–250 kHz

200 kHz–400 kHz

275 kHz–550 kHz

425 kHz–850 kHz

625 kHz–1.25 MHz

1.025 MHz–2.05 MHz

1.5 MHz–3 MHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.5 MHz–5 MHz

0

1

0

3.75 MHz–7.5 MHz

6.75 MHz–13.5 MHz

11.25 MHz–22.5 MHz

0

1

0

1

0

1

0

1

0

R/W

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22

the Flex bit has been erased by specific Page Erase or Mass

Erase ISP commands, execution will start from location 0000

in the Flash program memory. The forced entry to

MICROWIRE/PLUS ISP mode will not erase either the Flex

or the Security bit in the Option Register. The Security bit, if

set, can only be erased by a Mass Erase of the entire

contents of the Flash Memory unless under the control of

User ISP routines in the Application Program.

11.0 In-System Programming

(Continued)

11.4 MANEUVERING BACK AND FORTH BETWEEN

FLASH MEMORY AND BOOT ROM

When using ISP, at some point, it will be necessary to

maneuver between the Flash program memory and the Boot

ROM, even when using customized ISP routines. This is

because it’s not possible to execute from the Flash program

memory while it’s being programmed.

The MICROWIRE/PLUS routine in Boot ROM monitors the

G6 input, waits for it to go low, debounces it, and then

enables the ISP routine. The user may wish to disconnect

other circuitry while RESET, G0, G2 and the MICROWIRE/

PLUS pins are in use for ISP.

Two instructions are available to perform the jumping back

and forth: Jump to Boot (JSRB) and Return to Flash (RETF).

The JSRB instruction is used to jump from Flash memory to

Boot ROM, and the RETF is used to return from the Boot

ROM back to the Flash program memory. See Section 19.0

Instruction Set for specific details on the operation of these

instructions.

The correct sequence to be used to force execution from

Boot ROM is :

1. Apply V_CCto the device.

2. Pull RESET Low.

The JSRB instruction must be used in conjunction with the

Key register. This is to prevent jumping to the Boot ROM in

the event of run-away software. For the JSRB instruction to

actually jump to the Boot ROM, the Key bit must be set. This

is done by writing the value shown in Table 11 to the Key

register. The Key is a 6 bit key and if the key matches, the

KEY bit will be set for 8 instruction cycles. The JSRB instruc-

tion must be executed while the KEY bit is set. If the KEY

does not match, then the KEY bit will not be set and the

JSRB will jump to the specified location in the Flash memory.

In emulation mode, if a breakpoint is encountered while the

KEY is set, the counter that counts the instruction cycles will

be frozen until the breakpoint condition is cleared. If an

interrupt occurs while the key is set, the key will expire

before interrupt service is complete. It is recommended

that the software globally disable interrupts before set-

ting the key and re-enable interrupts on completion of

Boot ROM execution. The Key register is a memory

mapped register. Its format when writing is shown in Table

11.

3. Using G2 as a shift clock, shift a value of 5E38AC(hex)

into the G0 pin least significant bit first.

4. Pull RESET High.

5. Pull G6 low and initiate the MICORWIRE/PLUS commu-

nication.

11.6 RETURN TO FLASH MEMORY WITHOUT

HARDWARE RESET

After programming the entire program memory, including

options, it is necessary to exit the Boot ROM and return to

the Flash program memory for program execution. Upon

receipt and completion of the EXIT command through the

MICROWIRE/PLUS ISP, the ISP code will reset the part and

begin execution from the Flash program memory as de-

scribed in the Reset section. This assumes that the FLEX bit

in the Option register was programmed to 1.

11.7 MICROWIRE/PLUS ISP

National Semiconductor provides a program, which is avail-

able from our web site at www.national.com/cop8, that is

capable of programming a device from the parallel port of a

PC. The software accepts manually input commands and is

capable of downloading standard Intel HEX Format files.

TABLE 11. KEY Register Write Format

KEY When Writing

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Users who wish to write their own MICROWIRE/PLUS ISP

host software should refer to the COP8 FLASH ISP User

Manual, available from the same web site. This document

includes details of command format and delays necessary

between command bytes.

1

0

1

0

X

Bits 7–2: Key value that must be written to set the KEY bit.

Bits 1–0: Don’t care.

The MICROWIRE/PLUS ISP supports the following features

and commands:

11.5 FORCED EXECUTION FROM BOOT ROM

When the user is developing a customized ISP routine, code

lockups due to software errors may be encountered. The

normal, and preferred, method to recover from these condi-

tions is to reprogram the device with the corrected code by

either an external parallel programmer or the emulation

tools. As a last resort, when this equipment is not available,

there is a hardware method to get out of these lockups and

force execution from the Boot ROM MICROWIRE/PLUS

routine. The customer will then be able to erase the Flash

Memory code and start over.

•

Write a value to the ISP Write Timing Register. NOTE:

This must be the first command after entering

MICROWIRE/PLUS ISP mode.

•

Erase the entire Flash program memory (mass erase).

Erase a page at a specified address.

Read Option register.

Read a byte from a specified address.

Write a byte to a specified address.

Read multiple bytes starting at a specified address.

Write multiple bytes starting at a specified address.

Exit ISP and return execution to Flash program memory.

The method to force this condition is to shift a 24 bit code

into the G0 pin, using the G2 pin as a shift clock, while Reset

is activated. This special condition will bypass checking the

state of the Flex bit in the Option Register and will start

execution from location 0000 in the Boot ROM. In this state,

the user can input the appropriate commands, using

MICROWIRE/PLUS, to erase the Flash program memory

and reprogram it. If the device is subsequently reset before

The following table lists the MICROWIRE/PLUS ISP com-

mands and provides information on required parameters and

return values.

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11.0 In-System Programming (Continued)

TABLE 12. MICROWIRE/PLUS ISP Commands

Command

Value (Hex)

0x3B

Command

PGMTIM_SET

Function

Parameters

Return Data

Write Pulse Timing

Register

Value

N/A

PAGE_ERASE

MASS_ERASE

READ_BYTE

Page Erase

0xB3

0xBF

0x1D

Starting Address of

Page

Mass Erase

Read Byte

Confirmation Code

N/A (The entire Flash

Memory will be erased)

Address High, Address Data Byte if Security not

Low

set. 0xFF if Security set.

Option Register if address

= 0xFFFF, regardless of

Security

BLOCKR

Block Read

0xA3

Address High, Address n Data Bytes if Security

Low, Byte Count (n)

High, Byte Count (n)

Low

not set.

n Bytes of 0xFF if

Security set.

0 ≤ n ≤ 32767

WRITE_BYTE

BLOCKW

Write Byte

Block Write

0x71

0x8F

Address High, Address N/A

Low, Data Byte

Address High, Address N/A

Low, Byte Count (0 ≤ n

≤ 16), n Data Bytes

EXIT

N/A

0xD3

N/A

N/A (Device will Reset)

N/A

INVALID

Any other invalid

command will be

ignored

Note: The user must ensure that Block Writes do not cross a 64 byte boundary within one operation.

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24

Bits 11 through 15 of the ITMR register can be selected for

triggering the IDLE Timer interrupt. Each time the selected

bit underflows (every 4k, 8k, 16k, 32k or 64k selected

clocks), the IDLE Timer interrupt pending bit T0PND is set,

thus generating an interrupt (if enabled), and bit 6 of the Port

G data register is reset, thus causing an exit from the IDLE

mode if the device is in that mode.

12.0 Timers

The device contains a very versatile set of timers (T0 and

T1). Timer T1 and associated autoreload/capture registers

power up containing random data.

12.1 TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE Timer T0, which is a

16-bit timer. The user cannot read or write to the IDLE Timer

T0, which is a count down timer.

In order for an interrupt to be generated, the IDLE Timer

interrupt enable bit T0EN must be set, and the GIE (Global

Interrupt Enable) bit must also be set. The T0PND flag and

T0EN bit are bits 5 and 4 of the ICNTRL register, respec-

tively. The interrupt can be used for any purpose. Typically, it

is used to perform a task upon exit from the IDLE mode. For

more information on the IDLE mode, refer to Section 13.2

IDLE MODE.

The clock to the IDLE Timer is the instruction cycle clock

(one-tenth of the CKI frequency).

In addition to its time base function, the Timer T0 supports

the following functions:

The Idle Timer period is selected by bits 0–2 of the ITMR

register Bit 3 of the ITMR Register is reserved and should

not be used as a software flag. Bits 4 through 7 of the ITMR

Register are reserved and must be zero.

•

Exit out of the Idle Mode (See Idle Mode description)

WATCHDOG logic (See WATCHDOG description)

Start up delay out of the HALT mode

Start up delay from POR

Figure 18 is a functional block diagram showing the structure

of the IDLE Timer and its associated interrupt logic.

20047530

FIGURE 18. Functional Block Diagram for Idle Timer T0

12.1.1 ITMR Register

RSVD

TABLE 13. Idle Timer Window Length

ITSEL2

ITSEL1

ITSEL0

Idle Timer Period

4,096 inst. cycles

ITSEL2 ITSEL1 ITSEL0

Bit 2 Bit 1 Bit 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

8,192 inst. cycles

RSVD: These bits are reserved and must be set to 0.

16,384 inst. cycles

32,768 inst. cycles

65,536 inst. cycles

Reserved - Undefined

ITSEL2:0: Selects the Idle Timer period as described in

Table 13

Any time the IDLE Timer period is changed there is the

possibility of generating a spurious IDLE Timer interrupt by

setting the T0PND bit. The user is advised to disable IDLE

Timer interrupts prior to changing the value of the ITSEL bits

of the ITMR Register and then clear the T0PND bit before

attempting to synchronize operation to the IDLE Timer.

The ITSEL bits of the ITMR register are cleared on Reset

and the Idle Timer period is reset to 4,096 instruction cycles.

25

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interrupt when a timer underflow causes the R1B register to

be reloaded into the timer. Resetting the timer enable flags

will disable the associated interrupts.

12.0 Timers (Continued)

12.2 TIMER T1

One of the main functions of a microcontroller is to provide

timing and counting capability for real-time control tasks. The

COP8 family offers a very versatile 16-bit timer/counter

structure, and two supporting 16-bit autoreload/capture reg-

isters (R1A and R1B), optimized to reduce software burdens

in real-time control applications. The timer block has two pins

associated with it, T1A and T1B. Pin T1A supports I/O re-

quired by the timer block, while pin T1B is an input to the

timer block.

Either or both of the timer underflow interrupts may be

enabled. This gives the user the flexibility of interrupting

once per PWM period on either the rising or falling edge of

the PWM output. Alternatively, the user may choose to inter-

rupt on both edges of the PWM output.

The timer block has three operating modes: Processor Inde-

pendent PWM mode, External Event Counter mode, and

Input Capture mode.

The control bits T1C3, T1C2, and T1C1 allow selection of the

different modes of operation.

12.3 MODE 1. PROCESSOR INDEPENDENT PWM

MODE

One of the timer’s operating modes is the Processor Inde-

pendent PWM mode. In this mode, the timer generates a

“Processor Independent” PWM signal because once the

timer is setup, no more action is required from the CPU

which translates to less software overhead and greater

throughput. The user software services the timer block only

when the PWM parameters require updating. This capability

is provided by the fact that the timer has two separate 16-bit

reload registers. One of the reload registers contains the

“ON” timer while the other holds the “OFF” time. By contrast,

a microcontroller that has only a single reload register re-

quires an additional software to update the reload value

(alternate between the on-time/off-time).

20047531

FIGURE 19. Timer in PWM Mode

12.4 MODE 2. EXTERNAL EVENT COUNTER MODE

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, T1, is clocked by the input signal from the T1A pin. The

T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer

to be clocked either on a positive or negative edge from the

T1A pin. Underflows from the timer are latched into the

T1PNDA pending flag. Setting the T1ENA control flag will

cause an interrupt when the timer underflows.

The timer can generate the PWM output with the width and

duty cycle controlled by the values stored in the reload

registers. The reload registers control the countdown values

and the reload values are automatically written into the timer

when it counts down through 0, generating interrupt on each

reload. Under software control and with minimal overhead,

the PMW outputs are useful in controlling motors, triacs, the

intensity of displays, and in providing inputs for data acqui-

sition and sine wave generators.

In this mode the input pin T1B can be used as an indepen-

dent positive edge sensitive interrupt input if the T1ENB

control flag is set. The occurrence of a positive edge on the

T1B input pin is latched into the T1PNDB flag.

In this mode, the timer T1 counts down at a fixed rate of t_C.

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, R1A and R1B. The very

first underflow of the timer causes the timer to reload from

the register R1A. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

register R1B.

Figure 20 shows a block diagram of the timer in External

Event Counter mode.

Note: The PWM output is not available in this mode since the T1A pin is

being used as the counter input clock.

The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the

timer for PWM mode operation.

Figure 19 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the T1A output

pin. The underflows can also be programmed to generate

interrupts.

Underflows from the timer are alternately latched into two

pending flags, T1PNDA and T1PNDB. The user must reset

these pending flags under software control. Two control

enable flags, T1ENA and T1ENB, allow the interrupts from

the timer underflow to be enabled or disabled. Setting the

timer enable flag T1ENA will cause an interrupt when a timer

underflow causes the R1A register to be reloaded into the

timer. Setting the timer enable flag T1ENB will cause an

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26

fied either as a positive or a negative edge. The trigger

condition for each input pin can be specified independently.

12.0 Timers (Continued)

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the T1A and T1B pins will be respectively latched into the

pending flags, T1PNDA and T1PNDB. The control flag

T1ENA allows the interrupt on T1A to be either enabled or

disabled. Setting the T1ENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

T1A pin. Similarly, the flag T1ENB controls the interrupts

from the T1B pin.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer T1C0

pending flag (the T1C0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the T1C0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the T1ENA control flag. When a T1A interrupt

occurs in the Input Capture mode, the user must check both

the T1PNDA and T1C0 pending flags in order to determine

whether a T1A input capture or a timer underflow (or both)

caused the interrupt.

20047532

FIGURE 20. Timer in External Event Counter Mode

12.5 MODE 3. INPUT CAPTURE MODE

Figure 21 shows a block diagram of the timer in Input Cap-

ture mode.

The device can precisely measure external frequencies or

time external events by placing the timer block, T1, in the

input capture mode. In this mode, the reload registers serve

as independent capture registers, capturing the contents of

the timer when an external event occurs (transition on the

timer input pin). The capture registers can be read while

maintaining count, a feature that lets the user measure

elapsed time and time between events. By saving the timer

value when the external event occurs, the time of the exter-

nal event is recorded. Most microcontrollers have a latency

time because they cannot determine the timer value when

the external event occurs. The capture register eliminates

the latency time, thereby allowing the applications program

to retrieve the timer value stored in the capture register.

In this mode, the timer T1 is constantly running at the fixed t_C

rate. The two registers, R1A and R1B, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

R1A acts in conjunction with the T1A pin and the register

R1B acts in conjunction with the T1B pin.

20047533

FIGURE 21. Timer in Input Capture Mode

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

T1C3, T1C2 and T1C1, allow the trigger events to be speci-

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T1PNDA Timer Interrupt Pending Flag

T1ENA Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

12.0 Timers (Continued)

12.6 TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

0 = Timer Interrupt Disabled

T1C3

T1C2

T1C1

T1C0

Timer mode control

T1PNDB Timer Interrupt Pending Flag

T1ENB Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

0 = Timer Interrupt Disabled

The timer mode control bits (T1C3, T1C2 and T1C1) are

detailed below:

Timer Underflow Interrupt Pending Flag in Mode

3 (Input Capture)

Interrupt A

Source

Interrupt B

Source

Timer

Counts On

Mode

T1C3

T1C2

T1C1

Description

1

0

1

0

PWM: T1A Toggle

PWM: No T1A

Toggle

Autoreload RA

Autoreload RB

t_C

1

t_C

0

1

0

1

0

External Event

Counter

Timer Underflow Pos. T1B Edge

Pos. T1A

Edge

2

External Event

Counter

Pos. T1A

Edge

Captures:

Pos. T1A Edge

or Timer

Pos. T1B Edge

t_C

T1A Pos. Edge

T1B Pos. Edge

Captures:

Underflow

1

0

1

0

1

Pos. T1A

Neg. T1B

Edge

t_C

T1A Pos. Edge

T1B Neg. Edge

Captures:

Edge or Timer

Underflow

3

Neg. T1A

Neg. T1B

Edge

T1A Neg. Edge

T1B Neg. Edge

Captures:

Edge or Timer

Underflow

Neg. T1A

Neg. T1B

Edge

T1A Neg. Edge

T1B Neg. Edge

Edge or Timer

Underflow

activities are stopped. In the IDLE mode, the on-board os-

cillator circuitry and timer T0 are active but all other micro-

controller activities are stopped. In either mode, all on-board

RAM, registers, I/O states, and timers (with the exception of

T0) are unaltered.

13.0 Power Save Modes

Today, the proliferation of battery-operated based applica-

tions has placed new demands on designers to drive power

consumption down. Battery-operated systems are not the

only type of applications demanding low power. The power

budget constraints are also imposed on those consumer/

industrial applications where well regulated and expensive

power supply costs cannot be tolerated. Such applications

rely on low cost and low power supply voltage derived di-

rectly from the “mains” by using voltage rectifier and passive

components. Low power is demanded even in automotive

applications, due to increased vehicle electronics content.

This is required to ease the burden from the car battery. Low

power 8-bit microcontrollers supply the smarts to control

battery-operated, consumer/industrial, and automotive appli-

cations.

Clock Monitor if enabled can be active in both modes.

13.1 HALT MODE

The device can be placed in the HALT mode by writing a “1”

to the HALT flag (G7 data bit). All microcontroller activities,

including the clock and timers, are stopped. The WATCH-

DOG logic on the device is disabled during the HALT mode.

However, the clock monitor circuitry, if enabled, remains

active and will cause the WATCHDOG output pin (WDOUT)

to go low. If the HALT mode is used and the user does not

want to activate the WDOUT pin, the Clock Monitor should

be disabled after the device comes out of reset (resetting the

Clock Monitor control bit with the first write to the WDSVR

register). In the HALT mode, the power requirements of the

device are minimal and the applied voltage (V_CC) may be

decreased to V_r(V_r= 2.0V) without altering the state of the

machine.

The COP8TAx devices offer system designers a variety of

low-power consumption features that enable them to meet

the demanding requirements of today’s increasing range of

low-power applications. These features include low voltage

operation, low current drain, and power saving features such

as HALT, IDLE, and Multi-Input Wake-Up (MIWU).

The device supports three different ways of exiting the HALT

mode. The first method of exiting the HALT mode is with the

Multi-Input Wake-Up feature on Port L and Port C. The

The devices offer the user two power save modes of opera-

tion: HALT and IDLE. In the HALT mode, all microcontroller

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28

If an R/C clock option is being used, the fixed delay is

introduced optionally. A control bit, CLKDLY, mapped as

configuration bit G7, controls whether the delay is to be

introduced or not. The delay is included if CLKDLY is set,

and excluded if CLKDLY is reset. The CLKDLY bit is cleared

on reset.

13.0 Power Save Modes (Continued)

second method is with a low to high transition on the CKO

(G7) pin. This method precludes the use of the crystal clock

configuration (since CKO becomes a dedicated output), and

so may only be used with an R/C clock configuration. The

third method of exiting the HALT mode is by pulling the

RESET pin low.

The device has two options associated with the HALT mode.

The first option enables the HALT mode feature, while the

second option disables the HALT mode selected through bit

0 of the Option Byte. With the HALT mode enable option, the

device will enter and exit the HALT mode as described

above. With the HALT disable option, the device cannot be

placed in the HALT mode (writing a “1” to the HALT flag will

have no effect, the HALT flag will remain “0”).

Since a crystal or ceramic resonator may be selected as the

oscillator, the Multi-Input Wake-Up signal is not allowed to

start the chip running immediately since crystal oscillators

and ceramic resonators have a delayed start up time to

reach full amplitude and frequency stability. The IDLE timer

is used to generate a fixed delay to ensure that the oscillator

has indeed stabilized before allowing instruction execution.

In this case, upon detecting a valid Multi-Input Wake-Up

signal, only the oscillator circuitry is enabled. The IDLE timer

is loaded with a value of 256 and is clocked with the t_C

instruction cycle clock. The t_Cclock is derived by dividing the

oscillator clock down by a factor of 10. The Schmitt trigger

following the CKI inverter on the chip ensures that the IDLE

timer is clocked only when the oscillator has a sufficiently

large amplitude to meet the Schmitt trigger specifications.

This Schmitt trigger is not part of the oscillator closed loop.

The start-up time-out from the IDLE timer enables the clock

signals to be routed to the rest of the chip.

The WATCHDOG detector circuit is inhibited during the

HALT mode. However, the clock monitor circuit if enabled

remains active during HALT mode in order to ensure a clock

monitor error if the device inadvertently enters the HALT

mode as a result of a runaway program or power glitch.

If the device is placed in the HALT mode, with the R/C

oscillator selected, the clock input pin (CKI) is forced to a

logic high internally. With the crystal or external oscillator the

CKI pin is TRI-STATE.

20047534

FIGURE 22. Multi-Input Wake-Up from HALT

13.2 IDLE MODE

The user can enter the IDLE mode with the Timer T0 inter-

rupt enabled. In this case, when the T0PND bit gets set, the

device will first execute the Timer T0 interrupt service routine

and then return to the instruction following the “Enter Idle

Mode” instruction.

The device is placed in the IDLE mode by writing a “1” to the

IDLE flag (G6 data bit). In this mode, all activities, except the

associated on-board oscillator circuitry and the IDLE Timer

T0, are stopped.

Alternatively, the user can enter the IDLE mode with the

IDLE Timer T0 interrupt disabled. In this case, the device will

resume normal operation with the instruction immediately

following the “Enter IDLE Mode” instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions

are necessary to allow clock resynchronization following the HALT or

IDLE modes.

As with the HALT mode, the device can be returned to

normal operation with a reset, or with a Multi-Input Wake-Up

from the L Port. Alternately, the microcontroller resumes

normal operation from the IDLE mode when the twelfth bit

(representing 4.096 ms at internal clock frequency of

10 MHz, t_C= 1 µs) of the IDLE Timer toggles.

This toggle condition of the twelfth bit of the IDLE Timer T0 is

latched into the T0PND pending flag.

The user has the option of being interrupted with a transition

on the twelfth bit of the IDLE Timer T0. The interrupt can be

enabled or disabled via the T0EN control bit. Setting the

T0EN flag enables the interrupt and vice versa.

29

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13.0 Power Save Modes (Continued)

20047535

FIGURE 23. Wake-Up from IDLE

13.3 MULTI-INPUT WAKE-UP

ing bit in CWKPND or LWKPND remains set until cleared by

software. The device will not enter HALT or IDLE mode if any

Wake-Up input is both enabled and pending.

The Multi-Input Wake-Up feature is used to exit from the

HALT and IDLE modes. In addition, the Multi-Input Wake-

Up/Interrupt feature may be used to generate up to 16

edge-selectable external interrupts on the 44-pin devices or

8 interrupts on the 20- and 28-pin devices. Figure 24 shows

the Multi-Input Wake-Up logic.

Changing a trigger condition control bit requires several

steps to avoid generating a spurious Wake-Up event or

interrupt as a side effect

•

First, the corresponding CWKEN or LWKEN bit should be

cleared to disable any Wake-Up event or interrupt for that

port pin.

The Multi-Input Wake-Up feature uses the C and L ports.

(The 20- and 28-pin devices only have the L port.) Software

selects which port bit (or set of port bits) may cause the

device to exit the HALT or IDLE modes. The selection is

controlled by the CWKEN and LWKEN registers. These

registers are 8-bit read/write registers, which contain control

bits that correspond to the C and L port bits. Setting a

CWKEN or LWKEN bit enables a Wake-Up event or interrupt

from the associated C or L port pin.

•

Second, the trigger condition is selected in CWKEDG or

LWKEDG.

Third, any spurious pending event is removed by clearing

the associated bit in CWKPND or LWKPND.

Finally, the trigger is re-enabled by setting the associated

bit in CWKEN or LWKEN.

An example shows how software performs this procedure.

Assume the trigger condition for L port bit 5 is to be changed

from positive (low-to-high transition) to negative (high-to-low

transition), and bit 5 has previously been enabled for an

input interrupt. Software would execute the following instruc-

tions:

If the ACCESS.Bus module is enabled, port pin L0 may also

be used to generate a Wake-Up event on ACCESS.Bus

activity. Please see the section on Section 17.0 ACCESS-

.Bus Interface for more information.

Software selects whether the trigger condition on the se-

lected port pin is a positive edge (low-to-high transition) or a

negative edge (high-to-low transition). The trigger conditions

are selected in the CWKEDG and LWKEDG registers, which

are 8-bit control registers with bits corresponding to the C

and L port pins. Setting a trigger condition control bit selects

the negative edge, while clearing the bit selects the positive

edge.

RBIT 5, LWKEN

; Disable MIWU Port L.5

SBIT 5, LWKEDG ; Change edge polarity

RBIT 5, LWKPND ; Reset pending flag

SBIT 5, LWKEN

; Enable MIWU Port L.5

If the C or L port pins have been used as outputs and then

changed to inputs using the Multi-Input Wake-Up feature, a

safe procedure should be used to avoid generating a spuri-

ous Wake-Up event or interrupt. After the selected C or L

port pins have been changed from output to input, the trigger

conditions are selected in CWKEDG or LWKEDG and the

pending bits in CWKPND or LWKPND are cleared. Finally,

the CWKEN or LWKEN bits are set to enable the desired

Wake-Up events or interrupts.

The occurrence of a selected trigger condition is latched in

the pending registers called CWKPND and LWKPND. The

bits of these registers correspond to the C and L port pins.

These bits are set on the occurrence of the selected trigger

condition on the corresponding port pin, whether or not the

trigger condition is enabled in CWKEN or LWKEN. Software

has responsibility for clearing the pending bits before en-

abling them for Wake-Up events or interrupts. Any set pend-

The same procedure should be used following reset, be-

cause the C and L port pins are left floating. The CWKPND

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30

CWKEN and LWKEN are read/write registers that are

cleared at reset, so no Wake-Up events or interrupts are

enabled following reset. CWKEDG and LWKEDG are also

cleared at reset.

13.0 Power Save Modes (Continued)

and LWKPND registers contain undefined values after reset,

so software should clear these bits after reset to ensure that

no spurious Wake-Up events or interrupts are left pending.

20047581

FIGURE 24. Multi-Input Wake-Up Logic

The Software trap has the highest priority while the default

VIS has the lowest priority.

14.0 Interrupts

Each of the 13 maskable inputs has a fixed arbitration rank-

ing and vector.

14.1 INTRODUCTION

The device supports eleven vectored interrupts. Interrupt

sources include Timer 1, Timer 2, Timer T0, Multi-Input

Wake-Up, Software Trap, MICROWIRE/PLUS and External

Input.

Figure 25 shows the Interrupt block diagram.

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

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14.0 Interrupts (Continued)

20047576

FIGURE 25. Interrupt Block Diagram

14.2 MASKABLE INTERRUPTS

enabled; if the pending bit is already set, it will immediately

trigger an interrupt. A maskable interrupt is active if its asso-

ciated enable and pending bits are set.

All interrupts other than the Software Trap are maskable.

Each maskable interrupt has an associated enable bit and

pending flag bit. The pending bit is set to 1 when the interrupt

condition occurs. The state of the interrupt enable bit, com-

bined with the GIE bit determines whether an active pending

flag actually triggers an interrupt. All of the maskable inter-

rupt pending and enable bits are contained in mapped con-

trol registers, and thus can be controlled by the software.

An interrupt is an asychronous event which may occur be-

fore, during, or after an instruction cycle. Any interrupt which

occurs during the execution of an instruction is not acknowl-

edged until the start of the next normally executed instruc-

tion. If the next normally executed instruction is to be

skipped, the skip is performed before the pending interrupt is

acknowledged.

A maskable interrupt condition triggers an interrupt under the

following conditions:

At the start of interrupt acknowledgment, the following ac-

tions occur:

1. The enable bit associated with that interrupt is set.

2. The GIE bit is set.

1. The GIE bit is automatically reset to zero, preventing any

subsequent maskable interrupt from interrupting the cur-

rent service routine. This feature prevents one maskable

interrupt from interrupting another one being serviced.

3. The device is not processing a non-maskable interrupt.

(If

a non-maskable interrupt is being serviced, a

maskable interrupt must wait until that service routine is

completed.)

2. The address of the instruction about to be executed is

pushed onto the stack.

An interrupt is triggered only when all of these conditions are

met at the beginning of an instruction. If different maskable

interrupts meet these conditions simultaneously, the highest-

priority interrupt will be serviced first, and the other pending

interrupts must wait.

3. The program counter (PC) is loaded with 00FF Hex,

causing a jump to that program memory location.

The device requires seven instruction cycles to perform the

actions listed above.

Upon Reset, all pending bits, individual enable bits, and the

GIE bit are reset to zero. Thus, a maskable interrupt condi-

tion cannot trigger an interrupt until the program enables it by

setting both the GIE bit and the individual enable bit. When

enabling an interrupt, the user should consider whether or

not a previously activated (set) pending bit should be ac-

knowledged. If, at the time an interrupt is enabled, any

previous occurrences of the interrupt should be ignored, the

associated pending bit must be reset to zero prior to en-

abling the interrupt. Otherwise, the interrupt may be simply

If the user wishes to allow nested interrupts, the interrupts

service routine may set the GIE bit to 1 by writing to the PSW

register, and thus allow other maskable interrupts to interrupt

the current service routine. If nested interrupts are allowed,

caution must be exercised. The user must write the program

in such a way as to prevent stack overflow, loss of saved

context information, and other unwanted conditions.

The interrupt service routine stored at location 00FF Hex

should use the VIS instruction to determine the cause of the

interrupt, and jump to the interrupt handling routine corre-

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32

next priority interrupt is located at 0yE2 and 0yE3, and so

forth in increasing rank. The Software Trap has the highest

rand and its vector is always located at 0yFE and 0yFF. The

number of interrupts which can become active defines the

size of the table.

14.0 Interrupts (Continued)

sponding to the highest priority enabled and active interrupt.

Alternately, the user may choose to poll all interrupt pending

and enable bits to determine the source(s) of the interrupt. If

more than one interrupt is active, the user’s program must

decide which interrupt to service.

Table 14 shows the types of interrupts, the interrupt arbitra-

tion ranking, and the locations of the corresponding vectors

in the vector table.

Within a specific interrupt service routine, the associated

pending bit should be cleared. This is typically done as early

as possible in the service routine in order to avoid missing

the next occurrence of the same type of interrupt event.

Thus, if the same event occurs a second time, even while the

first occurrence is still being serviced, the second occur-

rence will be serviced immediately upon return from the

current interrupt routine.

The vector table should be filled by the user with the memory

locations of the specific interrupt service routines. For ex-

ample, if the Software Trap routine is located at 0310 Hex,

then the vector location 0yFE and -0yFF should contain the

data 03 and 10 Hex, respectively. When a Software Trap

interrupt occurs and the VIS instruction is executed, the

program jumps to the address specified in the vector table.

An interrupt service routine typically ends with an RETI

instruction. This instruction set the GIE bit back to 1, pops

the address stored on the stack, and restores that address to

the program counter. Program execution then proceeds with

the next instruction that would have been executed had

there been no interrupt. If there are any valid interrupts

pending, the highest-priority interrupt is serviced immedi-

ately upon return from the previous interrupt.

The interrupt sources in the vector table are listed in order of

rank, from highest to lowest priority. If two or more enabled

and pending interrupts are detected at the same time, the

one with the highest priority is serviced first. Upon return

from the interrupt service routine, the next highest-level

pending interrupt is serviced.

If the VIS instruction is executed, but no interrupts are en-

abled and pending, the lowest-priority interrupt vector is

used, and a jump is made to the corresponding address in

the vector table. This is an unusual occurrence and may be

the result of an error. It can legitimately result from a change

in the enable bits or pending flags prior to the execution of

the VIS instruction, such as executing a single cycle instruc-

tion which clears an enable flag at the same time that the

pending flag is set. It can also result, however, from inad-

vertent execution of the VIS command outside of the context

of an interrupt.

Note: While executing from the Boot ROM for ISP or virtual

E2 operations, the hardware will disable interrupts from oc-

curring. The hardware will leave the GIE bit in its current

state, and if set, the hardware interrupts will occur when

execution is returned to Flash Memory. Subsequent inter-

rupts, during ISP operation, from the same interrupt source

will be lost.

14.3 VIS INSTRUCTION

The general interrupt service routine, which starts at address

00FF Hex, must be capable of handling all types of inter-

rupts. The VIS instruction, together with an interrupt vector

table, directs the device to the specific interrupt handling

routine based on the cause of the interrupt.

The default VIS interrupt vector can be useful for applica-

tions in which time critical interrupts can occur during the

servicing of another interrupt. Rather than restoring the pro-

gram context (A, B, X, etc.) and executing the RETI instruc-

tion, an interrupt service routine can be terminated by return-

ing to the VIS instruction. In this case, interrupts will be

serviced in turn until no further interrupts are pending and

the default VIS routine is started. After testing the GIE bit to

ensure that execution is not erroneous, the routine should

restore the program context and execute the RETI to return

to the interrupted program.

VIS is a single-byte instruction, typically used at the very

beginning of the general interrupt service routine at address

00FF Hex, or shortly after that point, just after the code used

for context switching. The VIS instruction determines which

enabled and pending interrupt has the highest priority, and

causes an indirect jump to the address corresponding to that

interrupt source. The jump addresses (vectors) for all pos-

sible interrupts sources are stored in a vector table.

This technique can save up to fifty instruction cycles (t_C), or

more, (100 µs at 10 MHz oscillator) of latency for pending

interrupts with a penalty of fewer than ten instruction cycles

if no further interrupts are pending.

The vector table may be as long as 32 bytes (maximum of 16

vectors) and resides at the top of the 256-byte block con-

taining the VIS instruction. However, if the VIS instruction is

at the very top of a 256-byte block (such as at 00FF Hex),

the vector table resides at the top of the next 256-byte block.

Thus, if the VIS instruction is located somewhere between

00FF and 01DF Hex (the usual case), the vector table is

located between addresses 01E0 and 01FF Hex. If the VIS

instruction is located between 01FF and 02DF Hex, then the

vector table is located between addresses 02E0 and 02FF

Hex, and so on.

To ensure reliable operation, the user should always use the

VIS instruction to determine the source of an interrupt. Al-

though it is possible to poll the pending bits to detect the

source of an interrupt, this practice is not recommended. The

use of polling allows the standard arbitration ranking to be

altered, but the reliability of the interrupt system is compro-

mised. The polling routine must individually test the enable

and pending bits of each maskable interrupt. If a Software

Trap interrupt should occur, it will be serviced last, even

though it should have the highest priority. Under certain

conditions, a Software Trap could be triggered but not ser-

viced, resulting in an inadvertent “locking out” of all

maskable interrupts by the Software Trap pending flag.

Problems such as this can be avoided by using VIS

instruction.

Each vector is 15 bits long and points to the beginning of a

specific interrupt service routine somewhere in the 32-kbyte

memory space. Each vector occupies two bytes of the vector

table, with the higher-order byte at the lower address. The

vectors are arranged in order of interrupt priority. The vector

of the maskable interrupt with the lowest rank is located to

0yE0 (higher-order byte) and 0yE1 (lower-order byte). The

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14.0 Interrupts (Continued)

TABLE 14. Interrupt Vector Table

Vector Address (Note 7)

Arbitration Ranking

Source Description

(Hi-Low Byte)

(1) Highest

Software

INTR Instruction

0yFE–0yFF

(2)

(3)

(4)

(5)

(6)

(7)

(8)

Reserved for NMI

External

0yFC–0yFD

0yFA–0yFB

0yF8–0yF9

0yF6–0yF7

0yF4–0yF5

0yF2–0yF3

G0

Timer T0

Underflow

T1A/Underflow

T1B

Timer T1

MICROWIRE/PLUS

ACCESS.Bus

BUSY Low

Address Match, Bus Error, 0yF0–0yF1

Negative Acknowledge,

Valid Sto or SDAST is set

0yEE–0yEF

(9)

Reserved

(10)

(11)

(12)

(13)

(14)

(15)

Reserved

0yEC–0yED

Reserved

0yEA–0yEB

Reserved

0yE8–0yE9

Reserved

0yE6–0yE7

Reserved

0yE4–0yE5

Port L/Wake-up

Port C/Wake-up

Default VIS

Port L Edge

Port C Edge

Reserved

0yE2–0yE3

(16) Lowest

0yE0–0yE1

Note 7: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last

address of a block. In this case, the table must be in the next block.

14.3.1 VIS Execution

the active interrupt with the highest arbitration ranking. This

vector is read from program memory and placed into the PC

which is now pointed to the 1st instruction of the service

routine of the active interrupt with the highest arbitration

ranking.

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc....) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FA is generated and so forth. If no active interrupt

is pending, than E0 is generated. This number replaces the

lower byte of the PC. The upper byte of the PC remains

unchanged. The new PC is therefore pointing to the vector of

Figure 26 illustrates the different steps performed by the VIS

instruction. Figure 27 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

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34

14.0 Interrupts (Continued)

20047577

FIGURE 26. VIS Operation

14.4 NON-MASKABLE INTERRUPT

14.4.1 Pending Flag

Nothing can interrupt a Software Trap service routine except

for another Software Trap. The STPND can be reset only by

the RPND instruction or a chip Reset.

There is a pending flag bit associated with the non-maskable

Software Trap interrupt, called STPND. This pending flag is

not memory-mapped and cannot be accessed directly by the

software.

The Software Trap indicates an unusual or unknown error

condition. Generally, returning to normal execution at the

point where the Software Trap occurred cannot be done

reliably. Therefore, the Software Trap service routine should

re-initialize the stack pointer and perform a recovery proce-

dure that re-starts the software at some known point, similar

to a device Reset, but not necessarily performing all the

same functions as a device Reset. The routine must also

execute the RPND instruction to reset the STPND flag.

Otherwise, all other interrupts will be locked out. To the

extent possible, the interrupt routine should record or indi-

cate the context of the device so that the cause of the

Software Trap can be determined.

The pending flag is reset to zero when a device Reset

occurs. When the non-maskable interrupt occurs, the asso-

ciated pending bit is set to 1. The interrupt service routine

should contain an RPND instruction to reset the pending flag

to zero. The RPND instruction always resets the STPND

flag.

14.4.2 Software Trap

The Software Trap is a special kind of non-maskable inter-

rupt which occurs when the INTR instruction (used to ac-

knowledge interrupts) is fetched from program memory and

placed in the instruction register. This can happen in a

variety of ways, usually because of an error condition. Some

examples of causes are listed below.

If the user wishes to return to normal execution from the

point at which the Software Trap was triggered, the user

must first execute RPND, followed by RETSK rather than

RETI or RET. This is because the return address stored on

the stack is the address of the INTR instruction that triggered

the interrupt. The program must skip that instruction in order

to proceed with the next one. Otherwise, an infinite loop of

Software Traps and returns will occur.

If the program counter incorrectly points to a memory loca-

tion beyond the programmed Flash memory space, the un-

used memory location returns zeros which is interpreted as

the INTR instruction.

Programming a return to normal execution requires careful

consideration. If the Software Trap routine is interrupted by

another Software Trap, the RPND instruction in the service

routine for the second Software Trap will reset the STPND

flag; upon return to the first Software Trap routine, the

STPND flag will have the wrong state. This will allow

maskable interrupts to be acknowledged during the servicing

of the first Software Trap. To avoid problems such as this, the

A Software Trap can be triggered by a temporary hardware

condition such as a brownout or power supply glitch.

The Software Trap has the highest priority of all interrupts.

When a Software Trap occurs, the STPND bit is set. The GIE

bit is not affected and the pending bit (not accessible by the

user) is used to inhibit other interrupts and to direct the

program to the ST service routine with the VIS instruction.

35

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programming error or hardware condition (brownout, power

supply glitch, etc.) sets the STPND flag without providing a

way for it to be cleared, all other interrupts will be locked out.

To alleviate this condition, the user can use extra RPND

instructions in the main program and in the Watchdog ser-

vice routine (if present). There is no harm in executing extra

RPND instructions in these parts of the program.

14.0 Interrupts (Continued)

user program should contain the Software Trap routine to

perform a recovery procedure rather than a return to normal

execution.

Under normal conditions, the STPND flag is reset by a

RPND instruction in the Software Trap service routine. If a

20047578

FIGURE 27. VIS Flow Chart

14.4.2.1 Programming Example: External Interrupt

PSW

CNTRL

RBIT

SBIT

JP

=00EF

=00EE

0,PORTGC

0,PORTGD

IEDG, CNTRL

GIE, PSW

EXEN, PSW

WAIT

; G0 pin configured Hi-Z

; Ext interrupt polarity; falling edge

; Set the GIE bit

; Enable the external interrupt

; Wait for external interrupt

WAIT:

.

.=0FF

VIS

; The interrupt causes a

; branch to address 0FF

; The VIS causes a branch to

; interrupt vector table

.

.=01FA

.ADDRW SERVICE

; Vector table (within 256 byte

; of VIS inst.) containing the ext

; interrupt service routine

.

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36

14.0 Interrupts (Continued)

.

SERVICE:

; Interrupt Service Routine

RBIT,EXPND,PSW

; Reset ext interrupt pend. bit

.

RET I

; Return, set the GIE bit

14.5 PORT C AND PORT L INTERRUPTS

terrupts, during ISP operation, from the same interrupt

source will be lost.

Ports C and L provides the user with an additional sixteen

fully selectable, edge sensitive interrupts which are all vec-

tored into the same service subroutine.

15.0 WATCHDOG/Clock Monitor

The interrupt from Ports C and L share logic with the

wake-up circuitry. The registers CWKEN and LWKEN allow

interrupts from Ports C and L to be individually enabled or

disabled. The register CWKEDG and LWKEDG specify the

trigger condition to be either a positive or a negative edge.

Finally, the registers CWKPND and LWKPND latch in the

pending trigger conditions.

The devices contain a user selectable WATCHDOG and

clock monitor. The following section is applicable only if

WATCHDOG feature has been selected in the Option Byte.

The WATCHDOG is designed to detect the user program

getting stuck in infinite loops resulting in loss of program

control or “runaway” programs.

The WATCHDOG logic contains two separate service win-

dows. While the user programmable upper window selects

the WATCHDOG service time, the lower window provides

protection against an infinite program loop that contains the

WATCHDOG service instruction.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port C and Port L interrupts. Setting the LPEN flag will

enable interrupts and vice versa. A separate global pending

flag is not needed since the registers CWKPND and LWK-

PND are adequate.

The COP8TAx devices provide the added feature of a soft-

ware trap that provides protection against stack overpops

and addressing locations outside valid user program space.

Since Ports C and L are also used for waking the device out

of the HALT or IDLE modes, the user can elect to exit the

HALT or IDLE modes either with or without the interrupt

enabled. If he elects to disable the interrupt, then the device

will restart execution from the instruction immediately follow-

ing the instruction that placed the microcontroller in the

HALT or IDLE modes. In the other case, the device will first

execute the interrupt service routine and then revert to nor-

mal operation.

The Clock Monitor is used to detect the absence of a clock or

a very slow clock below a specified rate on the CKI pin.

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 15 shows the WDSVR register.

14.6 INTERRUPT SUMMARY

The device uses the following types of interrupts, listed

below in order of priority:

1. The Software Trap non-maskable interrupt, triggered by

the INTR (00 opcode) instruction. The Software Trap is

acknowledged immediately. This interrupt service rou-

tine can be interrupted only by another Software Trap.

The Software Trap should end with two RPND instruc-

tions followed by a re-start procedure.

TABLE 15. WATCHDOG Service Register (WDSVR)

Window

Select

Key Data

Clock

Monitor

Y

X

0

1

0

2. Maskable interrupts, triggered by an on-chip peripheral

block or an external device connected to the device.

Under ordinary conditions, a maskable interrupt will not

interrupt any other interrupt routine in progress. A

maskable interrupt routine in progress can be inter-

The lower limit of the service window is fixed at 256 instruc-

tion cycles. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 16 shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

rupted by the non-maskable interrupt request.

A

maskable interrupt routine should end with an RETI

instruction or, prior to restoring context, should return to

execute the VIS instruction. This is particularly useful

when exiting long interrupt service routines if the time

between interrupts is short. In this case the RETI instruc-

tion would only be executed when the default VIS rou-

tine is reached.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

TABLE 16. WATCHDOG Service Window Select

3. While executing from the Boot ROM for ISP or virtual E2

operations, the hardware will disable interrupts from oc-

curring. The hardware will leave the GIE bit in its current

state, and if set, the hardware interrupts will occur when

execution is returned to Flash Memory. Subsequent in-

WDSVR WDSVR Clock

Service Window

(Lower-Upper Limits)

256–8k t_CCycles

Bit 7

Bit 6

Monitor

0

1

x

256–16k t_CCycles

37

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DOG key data. Subsequent writes to the WDSVR register

will compare the value being written by the user to the

WATCHDOG service window value and the key data (bits 7

through 1) in the WDSVR Register. Table 17 shows the

sequence of events that can occur.

15.0 WATCHDOG/Clock Monitor

(Continued)

TABLE 16. WATCHDOG Service Window

Select (Continued)

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The WATCH-

DOG may not be serviced more than once in every lower

limit of the service window. The user may service the

WATCHDOG as many times as wished in the time period

between the lower and upper limits of the service window.

The first write to the WDSVR Register is also counted as a

WATCHDOG service.

WDSVR WDSVR Clock

Service Window

(Lower-Upper Limits)

256–32k t_CCycles

Bit 7

Bit 6

Monitor

1

x

0

1

x

0

1

256–64k t_CCycles

Clock Monitor Disabled

Clock Monitor Enabled

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the port G. WDOUT is active

low and must be externally connected to the RESET pin or to

some other external logic which handles WATCHDOG event.

The WDOUT pin has a weak pullup in the inactive state. This

pull-up is sufficient to serve as the connection to V_CCfor

systems which use the internal Power On Reset. Upon

triggering the WATCHDOG, the logic will pull the WDOUT

(G1) pin low for an additional 16 t_C–32 t_Ccycles after the

signal level on WDOUT pin goes below the lower Schmitt

trigger threshold. After this delay, the device will stop forcing

the WDOUT output low. The WATCHDOG service window

will restart when the WDOUT pin goes high.

15.1 CLOCK MONITOR

The Clock Monitor aboard the device can be selected or

deselected under program control. The Clock Monitor is

guaranteed not to reject the clock if the instruction cycle

clock (1/t_C) is greater or equal to 10 kHz. This equates to a

clock input rate on CKI of greater or equal to 100 kHz.

15.2 WATCHDOG/CLOCK MONITOR OPERATION

The WATCHDOG is enabled by bit 2 of the Option Byte.

When this Option bit is 0, the WATCHDOG is enabled and

pin G1 becomes the WATCHDOG output with a weak pullup.

The WATCHDOG and Clock Monitor are disabled during

reset. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select bits (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

A WATCHDOG service while the WDOUT signal is active will

be ignored. The state of the WDOUT pin is not guaranteed

on reset, but if it powers up low then the WATCHDOG will

time out and WDOUT will go high.

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error. The Clock Monitor error will continue

until the clock frequency has reached the minimum specified

value, after which the G1 output will go high following 16

t_C–32 t_Cclock cycles. The Clock Monitor generates a con-

tinual Clock Monitor error if the oscillator fails to start, or fails

to reach the minimum specified frequency. The specification

for the Clock Monitor is as follows:

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR

register involves two irrevocable choices: (i) the selection of

the WATCHDOG service window (ii) enabling or disabling of

the Clock Monitor. Hence, the first write to WDSVR Register

involves selecting or deselecting the Clock Monitor, select

the WATCHDOG service window and match the WATCH-

>

1/t_C10 kHz—No clock rejection.

<

1/t_C10 Hz—Guaranteed clock rejection.

TABLE 17. WATCHDOG Service Actions

Key

Window

Data

Clock

Monitor

Match

Action

Data

Match

Valid Service: Restart Service Window

Don’t Care

Mismatch

Don’t Care

Mismatch

Don’t Care

Don’t Care Error: Generate WATCHDOG Output

Mismatch

Error: Generate WATCHDOG Output

15.3 WATCHDOG AND CLOCK MONITOR SUMMARY

•

The initial WATCHDOG service must match the key data

value in the WATCHDOG Service register WDSVR in

order to avoid a WATCHDOG error.

The following salient points regarding the WATCHDOG and

CLOCK MONITOR should be noted:

Subsequent WATCHDOG services must match all three

data fields in WDSVR in order to avoid WATCHDOG

errors.

•

Both the WATCHDOG and CLOCK MONITOR detector

circuits are inhibited during RESET.

•

Following RESET, the WATCHDOG and CLOCK MONI-

TOR are both enabled, with the WATCHDOG having the

maximum service window selected.

The correct key data value cannot be read from the

WATCHDOG Service register WDSVR. Any attempt to

read this key data value of 01100 from WDSVR will read

as key data value of all 0’s.

•

The WATCHDOG service window and CLOCK MONI-

TOR enable/disable option can only be changed once,

during the initial WATCHDOG service following RESET.

•

The WATCHDOG detector circuit is inhibited during both

the HALT and IDLE modes.

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This is an undefined ROM location and the instruction

fetched (all 0’s) from this location will generate a software

interrupt signaling an illegal condition.

15.0 WATCHDOG/Clock Monitor

(Continued)

•

The CLOCK MONITOR detector circuit is active during

both the HALT and IDLE modes. Consequently, the de-

vice inadvertently entering the HALT mode will be de-

tected as a CLOCK MONITOR error (provided that the

CLOCK MONITOR enable option has been selected by

the program).

Thus, the chip can detect the following illegal conditions:

1. Executing from undefined ROM

2. Over “POP”ing the stack by having more returns than

calls.

When the software interrupt occurs, the user can re-initialize

the stack pointer and do a recovery procedure before restart-

ing (this recovery program is probably similar to that follow-

ing reset, but might not contain the same program initializa-

tion procedures). The recovery program should reset the

software interrupt pending bit using the RPND instruction.

•

With the single-pin R/C oscillator option selected and the

CLKDLY bit reset, the WATCHDOG service window will

resume following HALT mode from where it left off before

entering the HALT mode.

With the crystal oscillator option selected, or with the

single-pin R/C oscillator option selected and the CLKDLY

bit set, the WATCHDOG service window will be set to its

selected value from WDSVR following HALT. Conse-

quently, the WATCHDOG should not be serviced for at

least 256 instruction cycles following HALT, but must be

serviced within the selected window to avoid a WATCH-

DOG error.

16.0 MICROWIRE/PLUS

MICROWIRE/PLUS is a serial SPI compatible synchronous

communications interface. The MICROWIRE/PLUS capabil-

ity enables the device to interface with MICROWIRE/PLUS

or SPI peripherals (i.e. A/D converters, display drivers, EE-

PROMs etc.) and with other microcontrollers which support

the MICROWIRE/PLUS or SPI interface. It consists of an

8-bit serial shift register (SIO) with serial data input (SI),

serial data output (SO) and serial shift clock (SK). Figure 28

shows a block diagram of the MICROWIRE/PLUS logic.

•

The IDLE timer T0 is not initialized with external RESET.

The user can sync in to the IDLE counter cycle with an

IDLE counter (T0) interrupt or by monitoring the T0PND

flag. The T0PND flag is set whenever the twelfth bit of the

IDLE counter toggles (every 4096 instruction cycles). The

user is responsible for resetting the T0PND flag.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS

arrangement with the internal clock source is called the

Master mode of operation. Similarly, operating the

MICROWIRE/PLUS arrangement with an external shift clock

is called the Slave mode of operation.

•

A hardware WATCHDOG service occurs just as the de-

vice exits the IDLE mode. Consequently, the WATCH-

DOG should not be serviced for at least 256 instruction

cycles following IDLE, but must be serviced within the

selected window to avoid a WATCHDOG error.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the

master mode, the SK clock rate is selected by the two bits,

SL0 and SL1, in the CNTRL register. Table 18 details the

different clock rates that may be selected.

Following RESET, the initial WATCHDOG service (where

the service window and the CLOCK MONITOR enable/

disable must be selected) may be programmed any-

where within the maximum service window (65,536 in-

struction cycles) initialized by RESET. Note that this initial

WATCHDOG service may be programmed within the ini-

tial 256 instruction cycles without causing a WATCHDOG

error.

TABLE 18. MICROWIRE/PLUS

Master Mode Clock Select

•

In order to RESET the device on the occurrence of a

WATCH event, the user must connect the WDOUT pin

(G1) pin to the RESET external to the device. The weak

pull-up on the WDOUT pin is sufficient to provide the

RESET connection to V_CCfor devices which use both

Power On Reset and WATCHDOG.

SL1

0

SL0

SK Period

0

1

x

2 x t_C

4 x t_C

8 x t_C

0

1

Where t is the instruction cycle clock

C

15.4 DETECTION OF ILLEGAL CONDITIONS

16.1 MICROWIRE/PLUS OPERATION

The device can detect various illegal conditions resulting

from coding errors, transient noise, power supply voltage

drops, runaway programs, etc.

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave. Figure 28 shows how

two microcontroller devices and several peripherals may be

interconnected using the MICROWIRE/PLUS arrangements.

Reading of undefined ROM gets zeroes. The opcode for

software interrupt is 00. If the program fetches instructions

from undefined ROM, this will force a software interrupt, thus

signaling that an illegal condition has occurred.

The subroutine stack grows down for each call (jump to

subroutine), interrupt, or PUSH, and grows up for each

return or POP. The stack pointer is initialized to RAM location

06F Hex during reset. Consequently, if there are more re-

turns than calls, the stack pointer will point to addresses 070

and 071 Hex (which are undefined RAM). Undefined RAM

from addresses 070 to 07F (Segment 0), and all other seg-

ments (i.e., Segments 4 … etc.) is read as all 1’s, which in

turn will cause the program to return to address 7FFF Hex.

WARNING

The SIO register should only be loaded when the SK clock is

in the idle phase. Loading the SIO register while the SK clock

is in the active phase, will result in undefined data in the SIO

register.

Setting the BUSY flag when the input SK clock is in the

active phase while in the MICROWIRE/PLUS is in the slave

39

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Master always initiates all data exchanges. The MSEL bit in

the CNTRL register must be set to enable the SO and SK

functions onto the G Port. The SO and SK pins must also be

selected as outputs by setting appropriate bits in the Port G

configuration register. In the slave mode, the shift clock

stops after 8 clock pulses. Table 19 summarizes the bit

settings required for Master mode of operation.

16.0 MICROWIRE/PLUS (Continued)

mode may cause the current SK clock for the SIO shift

register to be narrow. For safety, the BUSY flag should only

be set when the input SK clock is in the idle phase.

16.2 MICROWIRE/PLUS MASTER MODE OPERATION

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE

20047537

FIGURE 28. MICROWIRE/PLUS Application

16.3 MICROWIRE/PLUS SLAVE MODE OPERATION

Master is shifted properly. After eight clock pulses the BUSY

flag is clear, the shift clock is stopped, and the sequence

may be repeated.

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and

resetting the appropriate bits in the Port G configuration

register. Table 19 summarizes the settings required to enter

the Slave mode of operation.

16.4 ALTERNATE SK PHASE OPERATION AND SK

IDLE POLARITY

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK idle polarity can be either high or low.

The polarity is selected by bit 5 of Port G data register. In the

normal mode data is shifted in on the rising edge of the SK

clock and the data is shifted out on the falling edge of the SK

clock. The SIO register is shifted on each falling edge of the

SK clock. In the alternate SK phase operation, data is shifted

in on the falling edge of the SK clock and shifted out on the

rising edge of the SK clock. Bit 6 of Port G configuration

register selects the SK edge.

This table assumes that the control flag MSEL is set.

TABLE 19. MICROWIRE/PLUS Mode Settings

G4 (SO)

Config. Bit

1

G5 (SK)

Config. Bit

1

G4

Fun.

SO

G5

Fun.

Int.

Operation

MICROWIRE/PLUS

Master

SK

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configu-

ration bit. The SKSEL flag will power up in the reset condi-

tion, selecting the normal SK signal.

0

1

0

1

0

TRI-

STATE

SO

Int.

MICROWIRE/PLUS

Master

SK

Ext.

SK

MICROWIRE/PLUS

Slave

TRI-

Ext.

SK

MICROWIRE/PLUS

Slave

STATE

The user must set the BUSY flag immediately upon entering

the Slave mode. This ensures that all data bits sent by the

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16.0 MICROWIRE/PLUS (Continued)

TABLE 20. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase

Port G

SK Idle

Phase

SK Phase

G6 (SKSEL)

G5

SO Clocked Out On:

SI Sampled On:

Config. Bit

Data Bit

Normal

Alternate

Normal

0

1

0

1

0

1

SK Falling Edge

SK Rising Edge

SK Falling Edge

SK Rising Edge

SK Falling Edge

SK Rising Edge

Low

High

20047538

FIGURE 29. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low

20047539

FIGURE 30. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low

20047540

FIGURE 31. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High

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16.0 MICROWIRE/PLUS (Continued)

20047541

FIGURE 32. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High

The ACCESS.Bus protocol supports multiple master and

17.0 ACCESS.Bus Interface

slave transmitters and receivers. Each bus device has a

The ACCESS.Bus interface module (ACB) is a two-wire

unique address and can operate as a transmitter or a re-

serial interface compatible with the ACCESS.Bus physical

ceiver (though some peripherals are only receivers).

layer. It permits easy interfacing to a wide range of low-cost

memories and I/O devices, including: EEPROMs, SRAMs,

17.1 DATA TRANSACTIONS

timers, A/D converters, D/A converters, clock chips, and

During data transactions, the master device initiates the

peripheral drivers. It is compatible with Intel’s SMBus and

transaction, generates the clock signal and terminates the

Philips’ I²C bus. The module can be configured as a bus

transaction. For example, when the ACB initiates a data

master or slave, and can maintain bidirectional communica-

transaction with an ACCESS.Bus peripheral, the ACB be-

tions with both multiple master and multiple slave devices.

comes the master. When the peripheral responds and trans-

•

ACCESS.Bus master and slave

mits data to the ACB, their master/slave (data transaction

initiator and clock generator) relationship is unchanged,

even though their transmitter/receiver functions are re-

versed.

Supports polling and interrupt-controlled operation

Generate a wake-up signal on detection of a Start Con-

dition, while in reduced-power mode

One data bit is transferred during each clock period. Data is

sampled during the high phase of the serial clock (SCL).

Consequently, throughout the clock high phase, the data

must remain stable (see Figure 33). Any change on the SDA

signal during the high phase of the SCL clock and in the

middle of a transaction aborts the current transaction. New

data must be driven during the low phase of the SCL clock.

This protocol permits a single data line to transfer both

command/control information and data using the synchro-

nous serial clock.

•

Optional internal pull-up on SDA and SCL pins

Optional 1.8V logic compatibility on SDA and SCL pins

The ACCESS.Bus protocol uses a two-wire interface for

bidirectional communication between the devices connected

to the bus. The two interface signals are the Serial Data Line

(SDA) and the Serial Clock Line (SCL). These signals should

be connected to the positive supply, through pull-up resis-

tors, to keep the signals high when the bus is idle. When the

ACCESS.Bus module is enabled and Bit 7 of the Option

Register (LVCMP) is set, the SDA and SCL inputs, along with

input L2, provide compatibility with 1.8V logic levels.

20047579

FIGURE 33. Bit Transfer

Each data transaction is composed of a Start Condition, a

number of byte transfers (programmed by software) and a

Stop Condition to terminate the transaction. Each byte is

transferred with the most significant bit first, and after each

byte, an Acknowledge signal must follow.

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17.1.1 Start and Stop

17.0 ACCESS.Bus Interface

The ACCESS.Bus master generates Start and Stop Condi-

tions (control codes). After a Start Condition is generated,

the bus is considered busy and it retains this status until a

certain time after a Stop Condition is generated. A high-to-

low transition of the data line (SDA) while the clock (SCL) is

high indicates a Start Condition. A low-to-high transition of

the SDA line while the SCL is high indicates a Stop Condition

(Figure 34).

(Continued)

At each clock cycle, the slave can stall the master while it

handles the previous data, or prepares new data. The slave

can hold SCL low, to extend the clock-low period, on each bit

transfer, or on a byte boundary, to accomplish this. Typically,

slaves extend the first clock cycle of a transfer if a byte read

has not yet been stored, or if the next byte to be transmitted

is not yet ready. Some microcontrollers, with limited hard-

ware support for ACCESS.Bus, extend the access after each

bit, to allow software time to handle this bit.

20047580

FIGURE 34. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start

Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a change in

the direction of the data transfer.

arbitration. In master mode, the device immediately aborts a

transaction if the value sampled on the SDA line differs from

the value driven by the device.

When an abort occurs during the address transmission, the

master that identifies the conflict should give up the bus,

switch to slave mode, and continue to sample SDA to see if

it is being addressed by the winning master on the

ACCESS.Bus.

17.1.2 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the ac-

knowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiv-

ing device.

17.3 POWER SAVE MODES

The master generates an acknowledge clock pulse after

each byte transfer. The receiver sends an acknowledge

signal after every byte received. There are two exceptions to

the "acknowledge after every byte" rule.

When this device is placed in HALT or IDLE mode, the ACB

module is effectively disabled. Registers ACBST, ACBCST

and ACBCTL1 are reset, however ACBSDA, ACBADDR and

ACBCTL2 are unaffected. If the ACB is enabled

(ACBCTL2.ENABLE = 1) on detection of a Start Condition, a

wake-up signal is issued to the Multi-Input Wake-Up module.

The byte transfer which causes the Wake-Up event will not

be acknowledged by the COP8 ACCESS.Bus and thus must

be retransmitted. The Multi-Input Wake-Up logic must be

configured, by the user, to enable Wake-Up on ACCESS.Bus

transfer. The ACCESS.Bus SDA signal is an alternate func-

tion of the one of the Multi-Input Wake-Up pins, and thus the

associated bit of the LWKEN or CWKEN and LWKEDG or

CWKEDG registers must be configured to cause a Wake-Up

event on a rising edge. See Figure 24 and the pinout table

for determination of the Multi-Input Wake-Up channel asso-

ciated with the ACCESS.Bus.

•

When the master is the receiver, it must indicate to the

transmitter an end-of-data condition by not-

acknowledging ("negative acknowledge") the last byte

clocked out of the slave. This "negative acknowledge"

still includes the acknowledge clock pulse (generated by

the master), but the SDA line is not pulled down.

•

When the receiver is full, otherwise occupied, or a prob-

lem has occurred, it sends a negative acknowledge to

indicate that it cannot accept additional data bytes.

17.1.3 Addressing Transfer Formats

Each device on the bus has a unique address. Before any

data is transmitted, the master transmits the address of the

slave being addressed. The slave device should send an

acknowledge signal on the SDA signal, once it recognizes its

address.

17.4 SDA AND SCL DRIVER CONFIGURATION

SDA and SCL are driven as open-drain signals on Port L

signals L0 and L1. If the ACB interface is not being used,

these pins are available for use as general-purpose port pins

or Multi-Input Wake-Up inputs.

17.2 BUS ARBITRATION

Arbitration is required when multiple master devices attempt

to gain control of the bus simultaneously. Control of the bus

is initially determined according to the address bits and clock

cycle. If the masters are trying to address the same bus

device, data comparisons determine the outcome of this

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17.0 ACCESS.Bus Interface

TGSCL

TSDA

The Toggle SCL bit enables toggling the SCL

signal during error recovery. When the SDA

signal is low, writing 1 to this bit drives the

SCL signal high for one cycle. Writing 1 to

TGSCL when the SDA signal is high is

ignored.

(Continued)

17.5 ACB SERIAL DATA REGISTER (ACBSDA)

The ACBSDA register is a byte-wide, read/write shift register

used to transmit and receive data. The most significant bit is

transmitted (received) first and the least significant bit is

transmitted (received) last.

The Test SDA bit samples the state of the

SDA signal. This bit can be used while

recovering from an error condition in which

the SDA signal is constantly pulled low by a

slave that has lost synchronization. This bit is

a read-only bit.

7

0

DATA

17.6 ACB STATUS REGISTER (ACBST)

The ACBST register is a byte-wide, read-only register that

reports the current ACB status.

GCMTCH The Global Call Match bit is set in slave

mode when the ACBCTL1.GCMEN bit is set

and the address byte (the first byte

7

6

5

4

3

2

1

0

SLVSTP SDAST BER NEGACK RSVD NMATCH MASTER XMIT

transferred after a Start Condition) is 00.

MATCH

The Address Match bit indicates in slave

mode when ACBADDR.SAEN is set and the

first seven bits of the address byte (the first

byte transferred after a Start Condition)

matches the 7-bit address in the ACBADDR

register.

SLVSTP

SDAST

BER

The Slave Stop bit is set when a Stop

Condition was detected after a slave transfer

(i.e., after a slave transfer in which MATCH

or GCMTCH is set).

The SDA Status bit is set when the SDA

data register is waiting for data (transmit, as

master or slave) or holds data that should be

read (receive, as master or slave)

BB

The Bus Busy bit indicates the bus is busy. It

is set when the bus is active (i.e., a low level

on either SDA or SCL) or by a Start

Condition. It is cleared when the module is

disabled or a Stop Condition is detected.

The BUSY bit indicates that the ACB module

is:

The Bus Error bit is set when a Start or Stop

Condition is detected during data transfer or

when an arbitration problem is detected.

BUSY

NEGACK The Negative Acknowledge bit is set when a

transmission is not acknowledged.

•

Generating a Start Condition

RSVD

This bit is reserved and will be zero.

In Master mode (ACBST.MASTER is set)

NMATCH The New Match bit is set when the address

byte following a Start Condition, or repeated

starts, causes a match or a global-call

match.

In Slave mode (ACBCST.MATCH or

ACBCST.GCMTCH is set)

•

In the period between detecting a Start and

completing the reception of the address

byte. After this, the ACB either becomes

not busy or enters slave mode. The BUSY

bit is cleared by the completion of any of

the above states, or by disabling the

module. BUSY is a read only bit.

MASTER The Master bit indicates that the module is

currently in master mode. It is set when a

request for bus mastership succeeds. It is

cleared upon arbitration loss (BER is set) or

the recognition of a Stop Condition.

XMIT

The Direction bit is set when the ACB

module is currently in master/slave transmit

mode. Otherwise, it is clear.

17.8 ACB CONTROL 1 REGISTER (ACBCTL1)

The ACBCTL1 register is a byte-wide, read/write register

that configures and controls the ACB module. At reset and

while the module is disabled (ACBCTL2.ENABLE = 0), the

ACBCTL1 register is cleared.

17.7 ACB CONTROL STATUS REGISTER (ACBCST)

The ACBCST register is a byte-wide, read/write register that

reports the current ACB status. At reset and when the mod-

ule is disabled, the non-reserved bits of ACBCST are

cleared.

7

6

5

4

3

2

1

0

CLRST NMINTE GCMEN ACK RSVD INTEN STOP START

CLRST

The Clear Status bit clears the NMATCH,

BER, NEGACK and SLVSTP bits when 1 is

written to this bit.

7

6

5

4

3

2

1

0

RSVD

TGSCL TSDA GCMTCH MATCH BB

BUSY

NMINTE

The New Match Interrupt Enable controls

whether ACB interrupts are generated on

new matches.

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44

17.0 ACCESS.Bus Interface

ENABLE

The Enable bit controls the ACB

module. When this bit is set, the ACB

module is enabled. When the Enable

bit is clear, the ACB module is

(Continued)

GCMEN

The Global Call Match Enable bit enables

the match of an incoming address byte to

the general call address (Start Condition

followed by address byte of 00) while the

ACB is in slave mode.

disabled, the ACBCTL1, ACBST, and

ACBCST registers are cleared, and the

ACB module clocks are halted.

ACK

The Acknowledge bit holds the value this

device sends in master or slave mode during

the next acknowledge cycle. Setting this bit

to 1 instructs the transmitting device to stop

sending data, because the receiver either

does not need, or cannot receive, any more

data.

17.10 ACB OWN ADDRESS REGISTER (ACBADDR)

The ACBADDR register is a byte-wide, read/write register

that holds the module’s first ACCESS.Bus address.

7

6

0

SEAN

ADDR

SAEN

The Slave Address Enable bit controls

whether address matching is performed

in slave mode. When set, the SAEN bit

indicates that the ADDR field holds a

valid address and enables the match of

ADDR to an incoming address byte.

The Own Address field holds the 7-bit

ACCESS.Bus address of this device. In

slave mode, the 7 bits received after a

Start Condition are compared to this field

(first bit received to bit 6, and the last to

bit 0). If the address field matches the

received data and the SAEN bit is set, a

match is detected.

INTEN

The Interrupt Enable bit controls generating

ACB interrupts. When the INTEN bit is set,

interrupts are enabled. An interrupt is

generated on any of the following events:

•

An address MATCH is detected

(ACBST.NMATCH = 1) and the NMINTE

bit is set.

ADDR

•

A Bus Error occurs (ACBST.BERR = 1).

Negative acknowledge after sending

byte (ACBST.NEGACK = 1).

a

•

An interrupt is generated on acknowledge

of each transaction (same as hardware

setting the ACBST.SDAST bit).

Detection of a Stop Condition while in

slave receive mode (ACBST.SLVSTP =

1).

18.0 Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

STOP

The Stop bit in master mode generates a

Stop Condition that completes or aborts the

current message transfer.

Address

Contents

ADD REG

START

The Start bit is set to generate a Start

Condition on the ACCESS.Bus. This bit

should be set only when in Master mode or

when requesting Master mode. An address

send sequence should then be performed.

00 to 6F

70 to 7F

On-Chip RAM bytes (112 bytes)

Unused RAM Address Space (Reads As

All Ones)

80 to 83

84

Unused RAM Address Space (Reads

Undefined Data)

17.9 ACB CONTROL REGISTER 2 (ACBCTL2)

Port C MIWU Edge Select Register

(Reg: CWKEDG)

The ACBCTL2 register is a byte-wide, read/write register

that controls the module and selects the ACB clock rate. At

reset, the ACBCTL2 register is cleared.

85

Port C MIWU Enable Register (Reg:

CWKEN)

7

1

0

86

Port C MIWU Pending Register (Reg:

CWKPND)

SCLFRQ

ENABLE

SCLFRQ

The SCL Frequency field specifies the

SCL period (low time and high time) in

master mode. The clock low time and

high time are defined as follows:

t_SCLK1= t_SCLKh= 2 x SCLFRQ x t_SCLK

Where tCLK is this device’s clock

period when in Active mode. The

SCLFRQ field may be programmed to

values in the range of 0001000

through 1111111.

87 to 8F

90 to 93

94

Reserved

Port F Data Register

Port F Configuration Register

Port F Input pins (Read Only)

Reserved for Port F

95

96

97

98 to 9F

A0 to A7

Reserved

45

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18.0 Memory Map (Continued)

Address

Contents

ADD REG

Address

Contents

ADD REG

E7

Timer T1 Autoload Register T1RB Upper

Byte

A8

ISP Address Register Low Byte

(ISPADLO)

E8

E9

EA

EB

EC

ICNTRL Register

MICROWIRE/PLUS Shift Register

Timer T1 Lower Byte

Timer T1 Upper Byte

Timer T1 Autoload Register T1RA Lower

Byte

A9

ISP Address Register High Byte

(ISPADHI)

AA

ISP Read Data Register (ISPRD)

ISP Write Data Register (ISPWR)

Reserved

AB

AC to AF

B0 to B7

B8

ED

Timer T1 Autoload Register T1RA Upper

Byte

Reserved

ACB Serial Data Register (ACBSDA)

ACB Status Register (ACBST)

ACB Control And Status (ACBCST)

ACB Control Register 1 (ACBCTL1)

ACB Own Address Register (ACBADDR)

ACB Control Register 2(ACBCTL2)

Reserved

EE

CNTRL Control Register

PSW Register

B9

EF

BA

F0 to FB

FC

On-Chip RAM Mapped as Registers

X Register

BB

BC

FD

SP Register

BD

FE

B Register

BE to BF

C0 to C6

C7

FF

On-Chip RAM Mapped as Register

Reserved

Note: Reading memory locations 70H–7FH will return all ones. Reading

unused memory locations 80H–83H, 87H–93H will return undefined

data.

WATCHDOG Service Register

(Reg:WDSVR)

C8

C9

CA

Port L MIWU Edge Select Register

(Reg:LWKEDG)

19.0 Instruction Set

Port L MIWU Enable Register

(Reg:LWKEN)

19.1 INTRODUCTION

This section defines the instruction set of the COP8 Family

members. It contains information about the instruction set

features, addressing modes and types.

Port L MIWU Pending Register

(Reg:LWKPND)

CB to CE

CF

D0

Reserved

19.2 INSTRUCTION FEATURES

Idle Timer Control Register (ITMR)

Port L Data Register

The strength of the instruction set is based on the following

features:

D1

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

•

Mostly single-byte opcode instructions minimize program

size.

D2

D3

One instruction cycle for the majority of single-byte in-

structions to minimize program execution time.

D4

Port G Data Register

Many single-byte, multiple function instructions such as

DRSZ.

D5

Port G Configuration Register

Port G Input Pins (Read Only)

Reserved

D6

Three memory mapped pointers: two for register indirect

addressing, and one for the software stack.

D7

D8

Port C Data Register

Sixteen memory mapped registers that allow an opti-

mized implementation of certain instructions.

D9

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved

Ability to set, reset, and test any individual bit in data

memory address space, including the memory-mapped

I/O ports and registers.

DA

DB

DC

DD

DE

DF

E0

Port J Data Register

•

Register-Indirect LOAD and EXCHANGE instructions

with optional automatic post-incrementing or decrement-

ing of the register pointer. This allows for greater effi-

ciency (both in cycle time and program code) in loading,

walking across and processing fields in data memory.

Port J Configuration Register

Port J Input Pins (Read Only)

CPU Clock Prescale Register (CLKPS)

Reserved

Unique instructions to optimize program size and

throughput efficiency. Some of these instructions are:

DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.

E1

Flash Memory Write Timing Register

(PGMTIM)

E2

ISP Key Register (ISPKEY)

Reserved

19.3 ADDRESSING MODES

E3 to E5

E6

The instruction set offers a variety of methods for specifying

memory addresses. Each method is called an addressing

mode. These modes are classified into two categories: op-

Timer T1 Autoload Register T1RB Lower

Byte

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46

Register

B or X Indirect with Post-Incrementing/

19.0 Instruction Set (Continued)

Decrementing. The relevant memory address is specified

by the contents of the B Register or X register (pointer

register). The pointer register is automatically incremented

or decremented after execution, allowing easy manipulation

of memory blocks with software loops. In assembly lan-

guage, the notation [B+], [B−], [X+], or [X−] specifies which

register serves as the pointer, and whether the pointer is to

be incremented or decremented.

erand addressing modes and transfer-of-control addressing

modes. Operand addressing modes are the various meth-

ods of specifying an address for accessing (reading or writ-

ing) data. Transfer-of-control addressing modes are used in

conjunction with jump instructions to control the execution

sequence of the software program.

19.3.1 Operand Addressing Modes

Example: Exchange Memory with Accumulator, B Indirect

with Post-Increment

The operand of an instruction specifies what memory loca-

tion is to be affected by that instruction. Several different

operand addressing modes are available, allowing memory

locations to be specified in a variety of ways. An instruction

can specify an address directly by supplying the specific

address, or indirectly by specifying a register pointer. The

contents of the register (or in some cases, two registers)

point to the desired memory location. In the immediate

mode, the data byte to be used is contained in the instruction

itself.

X A,[B+]

Reg/Data

Memory

Contents

Before

Contents

After

Accumulator

Memory Location

0005 Hex

03 Hex

62 Hex

05 Hex

03 Hex

06 Hex

B Pointer

Each addressing mode has its own advantages and disad-

vantages with respect to flexibility, execution speed, and

program compactness. Not all modes are available with all

instructions. The Load (LD) instruction offers the largest

number of addressing modes.

Intermediate. The data for the operation follows the instruc-

tion opcode in program memory. In assembly language, the

number sign character (#) indicates an immediate operand.

Example: Load Accumulator Immediate

LD A,#05

The available addressing modes are:

•

Direct

Reg/Data

Memory

Contents

Before

Contents

After

Register B or X Indirect

Register

Decrementing

B or X Indirect with Post-Incrementing/

Accumulator

XX Hex

05 Hex

•

Immediate

Immediate Short. This is a special case of an immediate

instruction. In the “Load B immediate” instruction, the 4-bit

immediate value in the instruction is loaded into the lower

nibble of the B register. The upper nibble of the B register is

reset to 0000 binary.

Immediate Short

Indirect from Program Memory

The addressing modes are described below. Each descrip-

tion includes an example of an assembly language instruc-

tion using the described addressing mode.

Example: Load B Register Immediate Short

LD B,#7

Direct. The memory address is specified directly as a byte in

the instruction. In assembly language, the direct address is

written as a numerical value (or a label that has been defined

elsewhere in the program as a numerical value).

Reg/Data

Memory

B Pointer

Contents

Before

Contents

After

12 Hex

07 Hex

Example: Load Accumulator Memory Direct

LD A,05

Indirect from Program Memory. This is a special case of

an indirect instruction that allows access to data tables

stored in program memory. In the “Load Accumulator Indi-

rect” (LAID) instruction, the upper and lower bytes of the

Program Counter (PCU and PCL) are used temporarily as a

pointer to program memory. For purposes of accessing pro-

gram memory, the contents of the Accumulator and PCL are

exchanged. The data pointed to by the Program Counter is

loaded into the Accumulator, and simultaneously, the original

contents of PCL are restored so that the program can re-

sume normal execution.

Reg/Data

Memory

Contents

Before

Contents

After

Accumulator

Memory Location

0005 Hex

XX Hex

A6 Hex

Register B or X Indirect. The memory address is specified

by the contents of the B Register or X register (pointer

register). In assembly language, the notation [B] or [X] speci-

fies which register serves as the pointer.

Example: Load Accumulator Indirect

LAID

Example: Exchange Memory with Accumulator, B Indirect

X A,[B]

Reg/Data

Memory

Contents

Before

04 Hex

35 Hex

1F Hex

Contents

After

Reg/Data

Memory

Contents

Before

Contents

After

PCU

04 Hex

36 Hex

25 Hex

PCL

Accumulator

Memory Location

0005 Hex

01 Hex

87 Hex

Accumulator

Memory Location

041F Hex

87 Hex

05 Hex

01 Hex

05 Hex

25 Hex

B Pointer

47

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19.0 Instruction Set (Continued)

19.3.2 Tranfer-of-Control Addressing Modes

Reg/

Memory

PCU

Contents

Before

Contents

After

42 Hex

36 Hex

25 Hex

Program instructions are usually executed in sequential or-

der. However, Jump instructions can be used to change the

normal execution sequence. Several transfer-of-control ad-

dressing modes are available to specify jump addresses.

PCL

Jump Indirect. In this 1-byte instruction, the lower byte of

the jump address is obtained from a table stored in program

memory, with the Accumulator serving as the low order byte

of a pointer into program memory. For purposes of access-

ing program memory, the contents of the Accumulator are

written to PCL (temporarily). The data pointed to by the

Program Counter (PCH/PCL) is loaded into PCL, while PCH

remains unchanged.

A change in program flow requires a non-incremental

change in the Program Counter contents. The Program

Counter consists of two bytes, designated the upper byte

(PCU) and lower byte (PCL). The most significant bit of PCU

is not used, leaving 15 bits to address the program memory.

Different addressing modes are used to specify the new

address for the Program Counter. The choice of addressing

mode depends primarily on the distance of the jump. Farther

jumps sometimes require more instruction bytes in order to

completely specify the new Program Counter contents.

Example: Jump Indirect

JID

Reg/

Memory

PCU

Contents

Before

01 Hex

C4 Hex

26 Hex

Contents

After

The available transfer-of-control addressing modes are:

•

Jump Relative

01 Hex

32 Hex

26 Hex

Jump Absolute

Jump Absolute Long

Jump Indirect

PCL

Accumulator

Memory

Location

0126 Hex

The transfer-of-control addressing modes are described be-

low. Each description includes an example of a Jump in-

struction using a particular addressing mode, and the effect

on the Program Counter bytes of executing that instruction.

32 Hex

The VIS instruction is a special case of the Indirect Transfer

of Control addressing mode, where the double-byte vector

associated with the interrupt is transferred from adjacent

addresses in program memory into the Program Counter in

order to jump to the associated interrupt service routine.

Jump Relative. In this 1-byte instruction, six bits of the

instruction opcode specify the distance of the jump from the

current program memory location. The distance of the jump

can range from −31 to +32. A JP+1 instruction is not allowed.

The programmer should use a NOP instead.

Example: Jump Relative

JP 0A

19.4 INSTRUCTION TYPES

The instruction set contains a wide variety of instructions.

The available instructions are listed below, organized into

related groups.

Contents

Before

Contents

After

Reg

Some instructions test a condition and skip the next instruc-

tion if the condition is not true. Skipped instructions are

executed as no-operation (NOP) instructions.

PCU

PCL

02 Hex

05 Hex

02 Hex

0F Hex

Jump Absolute. In this 2-byte instruction, 12 bits of the

instruction opcode specify the new contents of the Program

Counter. The upper three bits of the Program Counter re-

main unchanged, restricting the new Program Counter ad-

dress to the same 4-kbyte address space as the current

instruction. (This restriction is relevant only in devices using

more than one 4-kbyte program memory space.)

19.4.1 Arithmetic Instructions

The arithmetic instructions perform binary arithmetic such as

addition and subtraction, with or without the Carry bit.

Add (ADD)

Add with Carry (ADC)

Subtract with Carry (SUBC)

Increment (INC)

Example: Jump Absolute

JMP 0125

Decrement (DEC)

Decimal Correct (DCOR)

Clear Accumulator (CLR)

Set Carry (SC)

Contents

Before

Contents

After

Reg

PCU

PCL

0C Hex

77 Hex

01 Hex

25 Hex

Reset Carry (RC)

19.4.2 Transfer-of-Control Instructions

Jump Absolute Long. In this 3-byte instruction, 15 bits of

the instruction opcode specify the new contents of the Pro-

gram Counter.

The transfer-of-control instructions change the usual se-

quential program flow by altering the contents of the Pro-

gram Counter. The Jump to Subroutine instructions save the

Program Counter contents on the stack before jumping; the

Return instructions pop the top of the stack back into the

Program Counter.

Example: Jump Absolute Long

JMP 03625

Jump Relative (JP)

Jump Absolute (JMP)

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48

If Carry (IFC)

19.0 Instruction Set (Continued)

Jump Absolute Long (JMPL)

If Not Carry (IFNC)

If Bit (IFBIT)

Jump Indirect (JID)

If B Pointer Not Equal (IFBNE)

And Skip if Zero (ANDSZ)

Decrement Register and Skip if Zero (DRSZ)

Jump to Subroutine (JSR)

Jump to Subroutine Long (JSRL)

Jump to Boot ROM Subroutine (JSRB)

Return from Subroutine (RET)

Return from Subroutine and Skip (RETSK)

Return from Interrupt (RETI)

Software Trap Interrupt (INTR)

Vector Interrupt Select (VIS)

19.4.9 No-Operation Instruction

The no-operation instruction does nothing, except to occupy

space in the program memory and time in execution.

No-Operation (NOP)

Note: The VIS is a special case of the Indirect Transfer of

Control addressing mode, where the double byte vector

associated with the interrupt is transferred from adjacent

addresses in the program memory into the program counter

(PC) in order to jump to the associated interrupt service

routine.

19.4.3 Load and Exchange Instructions

The load and exchange instructions write byte values in

registers or memory. The addressing mode determines the

source of the data.

Load (LD)

19.5 REGISTER AND SYMBOL DEFINITION

Load Accumulator Indirect (LAID)

Exchange (X)

The following abbreviations represent the nomenclature

used in the instruction description and the COP8 cross-

assembler.

19.4.4 Logical Instructions

Registers

The logical instructions perform the operations AND, OR,

and XOR (Exclusive OR). Other logical operations can be

performed by combining these basic operations. For ex-

ample, complementing is accomplished by exclusive-ORing

the Accumulator with FF Hex.

A

8-Bit Accumulator Register

8-Bit Address Register

B

X

8-Bit Address Register

S

8-Bit Segment Register

Logical AND (AND)

Logical OR (OR)

SP

PC

PU

PL

C

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

Exclusive OR (XOR)

19.4.5 Accumulator Bit Manipulation Instructions

Lower 8 Bits of PC

The Accumulator bit manipulation instructions allow the user

to shift the Accumulator bits and to swap its two nibbles.

1 Bit of PSW Register for Carry

1 Bit of PSW Register for Half Carry

1 Bit of PSW Register for Global Interrupt

Enable

HC

GIE

Rotate Right Through Carry (RRC)

Rotate Left Through Carry (RLC)

Swap Nibbles of Accumulator (SWAP)

VU

VL

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

19.4.6 Stack Control Instructions

Push Data onto Stack (PUSH)

Pop Data off of Stack (POP)

Symbols

[B]

Memory Indirectly Addressed by B Register

Memory Indirectly Addressed by X Register

Direct Addressed Memory

Direct Addressed Memory or [B]

Direct Addressed Memory or [B] or

Immediate Data

[X]

19.4.7 Memory Bit Manipulation Instructions

MD

The memory bit manipulation instructions allow the user to

set and reset individual bits in memory.

Mem

Meml

Set Bit (SBIT)

Reset Bit (RBIT)

Reset Pending Bit (RPND)

Imm

Reg

8-Bit Immediate Data

Register Memory: Addresses F0 to FF

(Includes B, X and SP)

19.4.8 Conditional Instructions

The conditional instruction test a condition. If the condition is

true, the next instruction is executed in the normal manner; if

the condition is false, the next instruction is skipped.

Bit

←

Bit Number (0 to 7)

Loaded with

If Equal (IFEQ)

↔

Exchanged with

If Not Equal (IFNE)

If Greater Than (IFGT)

49

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19.0 Instruction Set (Continued)

19.6 INSTRUCTION SET SUMMARY

←

ADD

ADC

A,Meml

ADD

A

A + Meml

A + Meml + C, C Carry,

←

ADD with Carry

←

HC Half Carry

← ←

A − MemI + C, C Carry,

SUBC

A,Meml

Subtract with Carry

A

←

HC Half Carry

←

AND

A,Meml

Logical AND

A

A and Meml

Skip next if (A and Imm) = 0

ANDSZ A,Imm

Logical AND Immed., Skip if Zero

Logical OR

←

OR

A,Meml

MD,Imm

A,Meml

#

A

A or Meml

XOR

IFEQ

IFNE

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

RPND

X

Logical EXclusive OR

IF EQual

A xor Meml

Compare MD and Imm, Do next if MD = Imm

Compare A and Meml, Do next if A = Meml

IF EQual

≠

Compare A and Meml, Do next if A Meml

>

Compare A and Meml, Do next if A Meml

≠

Do next if lower 4 bits of B Imm

IF Not Equal

IF Greater Than

If B Not Equal

←

Reg

Decrement Reg., Skip if Zero

Set BIT

Reg Reg − 1, Skip if Reg = 0

#,Mem

1 to bit, Mem (bit = 0 to 7 immediate)

0 to bit, Mem

Reset BIT

IF BIT

If bit #,A or Mem is true do next instruction

Reset Software Interrupt Pending Flag

Reset PeNDing Flag

EXchange A with Memory

EXchange A with Memory [X]

LoaD A with Memory

LoaD A with Memory [X]

LoaD B with Immed.

LoaD Memory Immed.

LoaD Register Memory Immed.

EXchange A with Memory [B]

EXchange A with Memory [X]

LoaD A with Memory [B]

LoaD A with Memory [X]

LoaD Memory [B] Immed.

CLeaR A

↔

←

A,Mem

A,[X]

A

B

Mem

[X]

X

LD

A,Meml

A,[X]

Meml

[X]

LD

B,Imm

Mem,Imm

Reg,Imm

A, [B ]

A, [X ]

A, [B ]

A, [X ]

[B ],Imm

A

Imm

←

Mem Imm

LD

←

Reg Imm

↔

←

LD

←

[B], (B B 1)

X

A

←

[X], (X X 1)

X

←

[B], (B B 1)

LD

←

[X], (X X 1)

LD

← ←

[B] Imm, (B B 1)

LD

←

A

←

A

←

A

←

A

←

A

→

C

←

C

CLR

INC

DEC

LAID

DCOR

RRC

RLC

SWAP

SC

0

A

INCrement A

A + 1

A

DECrement A

A − 1

Load A InDirect from ROM

Decimal CORrect A

Rotate A Right thru C

Rotate A Left thru C

SWAP nibbles of A

Set C

ROM (PU,A)

A

BCD correction of A (follows ADC, SUBC)

→

←

→

←

→

A0 C

A7

…

←

A0 C, HC A0

↔

A7…A4 A3…A0

←

C

1, HC

0, HC

1

0

RC

Reset C

IFC

IF C

IF C is true, do next instruction

IFNC

POP

PUSH

VIS

IF Not C

If C is not true, do next instruction

← ←

SP SP + 1, A [SP]

A

POP the stack into A

PUSH A onto the stack

Vector to Interrupt Service Routine

Jump absolute Long

Jump absolute

←

[SP] A, SP SP − 1

←

PU [VU], PL [VL]

←

PC ii (ii = 15 bits, 0 to 32k)

JMPL

JMP

JP

Addr.

Disp.

←

PC9…0 i (i = 12 bits)

←

PC PC + r (r is −31 to +32, except 1)

Jump relative short

www.national.com

50

19.0 Instruction Set (Continued)

← ← ←

[SP] PL, [SP−1] PU,SP−2, PC ii

JSRL

JSR

Addr.

Addr

Jump SubRoutine Long

Jump SubRoutine

←

[SP] PL, [SP−1] PU,SP−2, PC9…0 i

← ←

[SP] PL, [SP−1] PU,SP−2,

JSRB

Jump SubRoutine Boot ROM

←

PL Addr,PU 00, switch to flash

←

PL ROM (PU,A)

JID

Jump InDirect

← ←

SP + 2, PL [SP], PU [SP−1]

RET

RETurn from subroutine

RETurn and SKip

←

RETSK

SP + 2, PL [SP],PU [SP−1],

skip next instruction

←

RETI

INTR

NOP

RETurn from Interrupt

Generate an Interrupt

No OPeration

SP + 2, PL [SP],PU [SP−1],GIE 1

←

[SP] PL, [SP−1] PU, SP−2, PC 0FF

←

PC PC + 1

19.7 INSTRUCTION EXECUTION TIME

Instructions Using A & C

Most instructions are single byte (with immediate addressing

mode instructions taking two bytes).

CLRA

INCA

DECA

LAID

1/1

1/3

1/1

1/3

2/2

Most single byte instructions take one cycle time to execute.

Skipped instructions require x number of cycles to be

skipped, where x equals the number of bytes in the skipped

instruction opcode.

DCORA

RRCA

RLCA

SWAPA

SC

See the BYTES and CYCLES per INSTRUCTION table for

details.

Bytes and Cycles per Instruction

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

RC

Arithmetic and Logic Instructions

IFC

[B]

1/1

Direct

3/4

Immed.

2/2

IFNC

ADD

ADC

SUBC

AND

OR

PUSHA

POPA

ANDSZ

3/4

2/2

3/4

2/2

3/4

2/2

Transfer of Control Instructions

3/4

2/2

XOR

IFEQ

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

3/4

2/2

JMPL

JMP

JP

3/4

2/3

1/3

3/5

2/5

1/3

1/5

1/7

1/1

3/4

2/2

3/4

2/2

JSRL

JSR

1/3

3/4

1/1

JSRB

JID

VIS

RET

RETSK

RETI

INTR

NOP

RPND

1/1

51

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19.0 Instruction Set (Continued)

Memory Transfer Instructions

Register Indirect

Auto Incr. & Decr.

[B+, B−] [X+, X−]

1/2 1/3

1/3

Register

Indirect

Direct Immed.

[B]

1/1

[X]

1/3

X A, (Note 8)

LD A, (Note 8)

LD B,Imm

2/3

2/2

1/1

2/2

1/2

<

(If B 16)

>

(If B 15)

LD B,Imm

LD Mem,Imm

LD Reg,Imm

IFEQ MD,Imm

2/2

3/3

2/3

3/3

2/2

>

Memory location addressed by B or X or directly.

Note 8:

=

www.national.com

52

N i b b l e L o w e r

53

www.national.com

20.0 Development Support

20.1 TOOLS ORDERING NUMBERS FOR THE COP8TA 2.5V FLASH FAMILY DEVICES

This section provides specific tools ordering information for the devices in this datasheet, followed by a summary of the tools and

development kits available at print time. Up-to-date information, device selection guides, demos, updates, and purchase

information can be obtained at our web site at: www.national.com/cop8.

Unless otherwise noted, tools can be purchased for worldwide delivery from National’s e-store: http://www.national.com/

store/

Tool

Order Number

Cost*

Free

Notes/Includes

Evaluation Software and Reference Designs

Software and Utilities

Web Downloads:

Assembler/ Linker/ Simulators/ Library Manager/

Compiler Demos/ Flash ISP and NiceMon Debugger

Utilities/ Example Code/ etc.

www.national.com/cop8

(Flash Emulator support requires licensed COP8-NSDEV

CD-ROM).

Hardware Reference

Designs

None

Starter Kits and Hardware Target Boards

Starter Development

Kits

COP8-DB-TAC

L

Supports COP8TA - Target board with 44LLP and 28SOIC

sockets, LEDs, Test Points, and Breadboard Area.

Development CD, ISP Cable and Source Code. No p/s.

Also supports COP8 Low Voltage Flash Emulator and

Kanda ISP Tool.

Software Development Languages, and Integrated Development Environments

National’s WCOP8 IDE COP8-NSDEV

and Assembler on CD

Fully Licensed IDE with Assembler and

Emulator/Debugger Support. Assembler/ Linker/

Simulator/ Utilities/ Documentation. Updates from web.

Included with COP8-DB-TAC, SKFlash, COP8 Emulators.

The ultimate information source for COP8 developers -

Integrates with WCOP8 IDE. Organize and manage code,

notes, datasheets, etc.

COP8 Library Manager www.kkd.dk/libman.htm

from KKD

Eval

M

Hardware Emulation and Debug Tools

Hardware Emulators

COP8-IMFlash-LV

Includes 110v/220v p/s, target cable with 2x7 connector,

manuals and software on CD.

Development and Production Programming Tools

Programming Adapters COP8-PGMA-20SF2

L

For programming 20SOIC COP8TA only.

For programming 28SOIC COP8TA only.

For programming 44LLP COP8TAC only.

(For any programmer

COP8-PGMA-28SF2

supporting flash adapter

COP8-PGMA-44CF2

base pinout)

KANDA’s Flash ISP

Programmer

COP8 USB ISP

www.kanda.com

USB connected Dongle, with target cable and Control

Software; Updateable from the web; Purchase from

www.kanda.com

Development Devices

COP8TAB9

COP8TAC9

Free

All packages. Obtain samples from: www.national.com

<

*Cost: Free; VL= $100; L=$100-$300; M=$300-$1k; H=$1k-$3k; VH=$3k-$5k

www.national.com

54

20.0 Development Support (Continued)

20.2 COP8 TOOLS OVERVIEW

COP8 Evaluation Software and Reference Designs -

Software and Hardware for: Evaluation of COP8 Development Environments; Learning about COP8 Architecture and

Features; Demonstrating Application Specific Capabilities.

Product

WCOP8 IDE

and Software

Downloads

Description

Source

Software Evaluation downloads for Windows. Includes WCOP8 IDE evaluation

version, Full COP8 Assembler/Linker, COP8-SIM Instruction Level Simulator or

Unis Simulator, Byte Craft COP8C Compiler Demo, IAR Embedded Workbench

(Assembler version), Manuals, Applications Software, and other COP8 technical

information.

www.national.com/cop8

FREE Download

COP8 Starter Kits and Hardware Target Solutions -

Hardware Kits for: In-depth Evaluation and Testing of COP8 capabilities; Developing and Testing Code; Implementing

Target Design.

Product

COP8TAC

Starter Kits

Description

Source

NSC Distributor,

COP8-DB-TAC - A complete Code Development Tool for 2.5V COP8Flash

Families. A Windows IDE with Assembler, Simulator, and Debug Monitor,

combined with a simple realtime target environment. Quickly design and

simulate your code, then download to the target COP8flash device for

execution and simple debugging. Includes a library of software routines, and

source code. No power supply.

or Order from:

www.national.com/cop8

(Add a COP8-EMFlash Emulator for advanced emulation and debugging)

COP8 Software Development Languages and Integrated Environments -

Integrated Software for: Project Management; Code Development; Simulation and Debug.

Description

Product

WCOP8 IDE

from National

on CD-ROM

Source

National’s COP8 Software Development package for Windows on CD. Fully

licensed versions of our WCOP8 IDE and Emulator Debugger, with Assembler/

Linker/ Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon

Debugger Utilities/ Example Code/ etc. Includes all COP8 datasheets and

documentation. Included with most tools from National.

NSC Distributor, or Order

from:

www.national.com/cop8

Unis Processor

Expert

Processor Expert( from Unis Corporation - COP8 Code Generation and

Simulation tool with Graphical and Traditional user interfaces. Automatically

generates customized source code "Beans" (modules) containing working code

for all on-chip features and peripherals, then integrates them into a fully

functional application code design, with all documentation.

Unis, or Order from:

www.national.com/cop8

Byte Craft

COP8C

ByteCraft COP8C- C Cross-Compiler and Code Development System. Includes

BCLIDE (Integrated Development Environment) for Win32, editor, optimizing C

Cross-Compiler, macro cross assembler, BC-Linker, and MetaLinktools support.

(DOS/SUN versions available; Compiler is linkable under WCOP8 IDE)

IAR EWCOP8 - ANSI C-Compiler and Embedded Workbench. A fully integrated

Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and

C-Spy high-level simulator/debugger. (EWCOP8-M version includes COP8Flash

Emulator support) (EWCOP8-BL version is limited to 4k code limit; no FP).

ByteCraft Distributor,

or Order from:

Compiler

www.national.com/cop8

IAR Embedded

Workbench

IAR Distributor,

or Order from:

www.national.com/cop8

COP8 Hardware Emulation/Debug Tools -

Hardware Tools for: Real-time Emulation; Target Hardware Debug; Target Design Test.

Description

Product

COP8Flash

Source

COP8 In-Circuit Emulator for Flash Families. Windows based development and

real-time in-circuit emulation tool with 32k, trace 32k s/w breakpoints,

source/symbolic debugger, and device programming. Includes COP8-NSDEV

CD, Null Target, emulation cable with 2x7 connector, and power supply.

A simple, single-step debug monitor with one breakpoint. MICROWIRE

interface.

NSC Distributor,

Emulators -

or Order from:

COP8-DMFlash

www.national.com/cop8

NiceMon Debug

Monitor Utility

Download from:

www.national.com/cop8

55

www.national.com

20.0 Development Support (Continued)

Development and Production Programming Tools -

Programmers for: Design Development; Hardware Test; Pre-Production; Full Production.

Description

Product

COP8 Flash

Emulators

Source

COP8 Flash Emulators include in-circuit device programming capability during

development.

NSC Distributor, or

Order from:

www.national.com/cop8

Download from:

NiceMon

National’s software Utilities "KANDAFlash" and "NiceMon" provide development

In-System-Programming for our Flash Starter Kit, our Prototype Development

Board, or any other target board with appropriate connectors.

The COP8-ISP programmer from KANDA is available for engineering, and small

volume production use. PC parallel or serial interface.

Debugger,

KANDAFlash

KANDA

www.national.com/cop8

www.kanda.com

COP8-ISP

SofTec Micro

inDart COP8

Third-Party

Programmers

Factory

The inDart COP8 programmer from SofTec is available for engineering and

small volume production use. PC serial interface only.

www.softecmicro.com

Third-party programmers and automatic handling equipment are approved for

non-ISP engineering and production use.

Factory programming available for high-volume requirements and LLP

production.

National

Programming

Representative

20.3 WHERE TO GET TOOLS

Tools can be ordered directly from National, National’s e-store (Worldwide delivery: http://www.national.com/store/) , a National

Distributor, or from the tool vendor. Go to the vendor’s web site for current listings of distributors.

Vendor

Home Office

421 King Street North

Waterloo, Ontario

Canada N2J 4E4

Tel: 1-(519) 888-6911

Fax: (519) 746-6751

PO Box 23051

Electronic Sites

www.bytecraft.com

Other Main Offices

Byte Craft Limited

Distributors Worldwide

@

info bytecraft.com

IAR Systems AB

www.iar.se

USA:: San Francisco

Tel: +1-415-765-5500

Fax: +1-415-765-5503

UK: London

@

info iar.se

S-750 23 Uppsala

Sweden

@

info iar.com

@

info iarsys.co.uk

Tel: +46 18 16 78 00

Fax +46 18 16 78 38

@

info iar.de

Tel: +44 171 924 33 34

Fax: +44 171 924 53 41

Germany: Munich

Tel: +49 89 470 6022

Fax: +49 89 470 956

USA:

Embedded Results

Ltd.

P.O. Box 200,

www.kanda.com

@

Aberystwyth,

sales kanda.co

Tel: 408-441-1300

Fax: 408-437-8970

SY23 2WD, UK

@

Tel/Fax: +44 (0)8707 446 807

sales allamerican.com

www.allamerican.com

Tel/Fax: 800-510-3609

@

info ucpros.com

www.ucpros.com

@

K and K

Kaergaardsvej 42 DK-8355

Solbjerg Denmark

www.kkd.dk kkd kkd.dk

Development ApS

Fax: +45-8692-8500

2900 Semiconductor Dr.

Santa Clara, CA 95051

USA

National

www.national.com/cop8

Europe:

@

Semiconductor

support nsc.com

Tel: 49(0) 180 530 8585

Fax: 49(0) 180 530 8586

Hong Kong:

@

europe.support nsc.com

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Distributors Worldwide

www.national.com

56

20.0 Development Support (Continued)

Vendor

SofTec Microsystems Via Roma, 1

33082 Azzano Decimo (PN)

Home Office

Electronic Sites

Other Main Offices

Germany:

@

info softecmicro.com

www.softecmicro.com

@

support softecmicro.com

Tel.:+49 (0) 8761 63705

France:

Italy

Tel: +39 0434 640113

Fax: +39 0434 631598

Tel: +33 (0) 562 072 954

UK:

Tel: +44 (0) 1970 621033

The following companies have approved COP8 programmers in a variety of configurations. Contact your vendor’s local office

or distributor and request a COP8FLASH update. You can link to their web sites and get the latest listing of approved

programmers at: www.national.com/cop8.

Advantech; BP Microsystems; Data I/O; Dataman; Hi-Lo Systems; KANDA, Lloyd Research; MQP; Needhams; Phyton; SofTec

Microsystems; System General; and Tribal Microsystems.

21.0 Revision History

Date

December,

2002

Section

Summary of Changes

Preliminary Datasheet Release.

April, 2003

User ISP and Virtual E²

Restrictions on Software

When Calling ISP Routines

in Boot ROM

Deleted

June, 2003

Multi-Input Wake-Up and

ACCESS.Bus Interface

Electrical Specifications,

Option Register and

ACCESS.Bus

Updated to account for C Port Wake-Up.

August, 2003

Added 1.8V input compatibility on L0 (SDA), L1 (SCL) and L2.

Added Electrical Specifications for ACCESS.Bus

February, 2004 Electrical Specifications,

Development Support

Updated Electrical Specifications, Updated Development Support

May, 2004

Reset

Clarified need for external Reset in Brownout conditions.

Modified Recommended Reset Circuit to include external Brownout detector.

Added missing Port C.

Memory Map

February, 2005 General

Clarify differences between COP8TAx9 and COP8TAx5 to minimize problems

when generating ROM code for COP8TAx5 production.

General rework, through Section 11.0 In-System Programming, for clarity.

Increase Input Capacitance specification.

Electrical Specifications

Add Oscillator Frequency specification.

Increase Typical R/C Oscillator specification.

Add Figure references to ACCESS.Bus timing specifications.

Correct SCL edge reference for SDA Valid Time.

Reduce Halt Current Specification.

57

www.national.com

22.0 Physical Dimensions inches (millimeters) unless otherwise noted

LLP Package

Order Number COP8TAB9HLQ8 or COP8TAC9HLQ8

NS Package Number LQA44A

SOIC Wide Package

Order Number COP8TAB9EMW8 or COP8TAC9EMW8

NS Package Number M28B

www.national.com

58

22.0 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

SOIC Wide Package

Order Number COP8TAB9CMW8 or COP8TAC9CMW8

NS Package Number M20B

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products

Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain

no ‘‘Banned Substances’’ as defined in CSP-9-111S2.

National Semiconductor

Americas Customer

Support Center

National Semiconductor

Europe Customer Support Center

Fax: +49 (0) 180-530 85 86

National Semiconductor

Asia Pacific Customer

Support Center

National Semiconductor

Japan Customer Support Center

Fax: 81-3-5639-7507

Email: new.feedback@nsc.com

Tel: 1-800-272-9959

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

Email: jpn.feedback@nsc.com

Tel: 81-3-5639-7560

www.national.com


型号：	COP8TAB9EMW8
厂家：	National Semiconductor
描述：	8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory 8位CMOS闪存微控制器与2K字节或4K字节存储器闪存存储微控制器
文件：	总59页 (文件大小：1113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

COP8TAB9EMW8 [NSC]

相关型号：

COP8TAB9HLQ8

COP8TAB9HMW8

COP8TAB9_0504

COP8TAC5

COP8TAC5CLQ8

COP8TAC5CMW8

COP8TAC5ELQ8

COP8TAC5EMW8

COP8TAC5HLQ8

COP8TAC5HMW8

COP8TAC9

COP8TAC9CLQ8