DAC101C081 [NSC]
12-Bit Micro Power Digital-to-Analog Converter with an I2C-Compatible Interface; 12位微功耗数位类比转换器具有一个I2C兼容接口
| 型号： | DAC101C081 |
| 厂家： | 
National Semiconductor |
| 描述： | 12-Bit Micro Power Digital-to-Analog Converter with an I2C-Compatible Interface |
| 文件： | 总24页 (文件大小：680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 20, 2007
DAC121C081/ DAC121C085
12-Bit Micro Power Digital-to-Analog Converter with an
I2C-Compatible Interface
General Description
The DAC121C081 is a 12-bit, single channel, voltage-output
digital-to-analog converter (DAC) that operates from a +2.7V
to 5.5V supply. The output amplifier allows rail-to-rail output
swing and has an 8.5usec settling time. The DAC121C081
uses the supply voltage as the reference to provide the widest
dynamic output range and typically consumes 132uA while
operating at 5.0V. It is available in 6-lead TSOT and LLP
packages and provides three address options (pin se-
lectable).
Features
Guaranteed Monotonicity to 12-bits
■
■
■
■
Low Power Operation: 156 µA max @ 3.3V
Extended power supply range (+2.7V to +5.5V)
I2C-Compatible 2-wire Interface which supports standard
(100kHz), fast (400kHz), and high speed (3.4MHz) modes
Rail-to-Rail Voltage Output
■
■
Very small 6-pin TSOT and LLP Packages
As an alternative, the DAC121C085 provides nine I2C ad-
dressing options and uses an external reference. It has the
same performance and settling time as the DAC121C081. It
is available in an 8-lead MSOP.
The DAC121C081 and DAC121C085 use a 2-wire, I2C-com-
patible serial interface that operates in all three speed modes,
including high speed mode (3.4MHz). An external address
selection pin allows up to three DAC121C081 or nine
DAC121C085 devices per 2-wire bus. Pin compatible alter-
natives to the DAC121C081 are available that provide addi-
tional address options.
Key Specifications
Resolution
INL
12 bits
±8 LSB (max)
+0.6 / -0.5 LSB (max)
8.5 µs (max)
■
■
■
■
■
■
■
DNL
Settling Time
Zero Code Error
Full-Scale Error
Supply Power
+10 mV (max)
−0.7 %FS (max)
Normal
380 µW (3V) / 730 µW (5V) typ
0.5 µW (3V) / 0.9 µW (5V) typ
—
—
Power Down
The DAC121C081 and DAC121C085 each have a 16-bit reg-
ister that controls the mode of operation, the power-down
condition, and the output voltage. A power-on reset circuit
ensures that the DAC output powers up to zero volts. A power-
down feature reduces power consumption to less than a
microWatt. Their low power consumption and small packages
make these DACs an excellent choice for use in battery op-
erated equipment. Each DAC operates over the extended
industrial temperature range of −40°C to +125°C.
Applications
Industrial Process Control
■
■
Portable Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Test Equipment
■
■
■
The DAC121C081 and DAC121C085 are each part of a fam-
ily of pin compatible DACs that also provide 8 and 10 bit
resolution. For 8-bit DACs see the DAC081C081 and
DAC081C085. For 10-bit DACs see the DAC101C081 and
DAC101C085.
Pin-Compatible Alternatives
All devices are fully pin and function compatible.
Resolution TSOT-6 and LLP-6 MSOP-8 Package w/
Packages
External Reference
12-bit
10-bit
8-bit
DAC121C081
DAC101C081
DAC081C081
DAC121C085
DAC101C085
DAC081C085
Connection Diagrams
30004901
30004902
30004910
I2C® is a registered trademark of Phillips Corporation.
© 2007 National Semiconductor Corporation
300049
www.national.com
Ordering Information
Order Code
Temperature Range
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Package
TSOT
Top Mark
X84C
X84C
X87
DAC121C081CIMK
DAC121C081CIMKX
DAC121C081CISD
DAC121C081CISDX
DAC121C085CIMM
DAC121C085CIMMX
DAC121C08XEB
TSOT Tape-and-Reel
LLP
LLP Tape-and-Reel
MSOP
X87
X90C
X90C
MSOP Tape-and-Reel
Evaluation Board
Block Diagram
30004903
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2
Pin Descriptions
Symbol
Type
Equivalent Circuit
Description
Analog Output Voltage.
VOUT
Analog Output
Power supply input. For the TSOT and LLP versions, this
supply is used as the reference. Must be decoupled to
GND.
VA
Supply
Ground
GND
Ground for all on-chip circuitry.
Serial Data bi-directional connection. Data is clocked into
or out of the internal 16-bit register relative to the clock
edges of SCL. This is an open drain data line that must be
pulled to the supply (VA) by an external pull-up resistor.
Digital
Input/Output
SDA
Serial Clock Input. SCL is used together with SDA to
control the transfer of data in and out of the device.
SCL
Digital Input
Tri-state Address Selection Input. Sets the two Least
Significant Bits (A1 & A0) of the 7-bit slave address. (see
Table 1)
Digital Input,
three levels
ADR0
Digital Input,
three levels
Tri-state Address Selection Input. Sets Bits A6 & A3 of the
7-bit slave address. (see Table 1)
ADR1
VREF
Unbufferred reference voltage. For the MSOP-8, this
supply is used as the reference. VREF must be free of noise
and decoupled to GND.
Supply
Ground
Exposed die attach pad can be connected to ground or left
floating. Soldering the pad to the PCB offers optimal
thermal performance and enhances package self-
alignment during reflow.
PAD
(LLP only)
Package Pinouts
VOUT
VA
2
VREF
N/A
N/A
7
GND
SDA
SCL
ADR0
ADR1
N/A
N/A
2
PAD (LLP only)
TSOT
LLP
1
6
8
3
4
5
4
3
4
5
2
3
6
1
1
N/A
7
5
MSOP-8
6
N/A
3
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Absolute Maximum Ratings
(Notes 1, 2)
Operating Ratings (Notes 1, 2)
Operating Temperature Range
−40°C ≤ TA ≤ +125°C
Supply Voltage, VA
+2.7V to 5.5V
+1.0V to VA
0.0V to 5.5V
0 to 1500 pF
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Reference Voltage, VREFIN
Digital Input Voltage (Note 7)
Output Load
Supply Voltage, VA
−0.3V to +6.5V
−0.3V to +6.5V
±10 mA
Voltage on any Input Pin
Package Thermal Resistances
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Consumption at TA = 25°C
Package
θJA
±20 mA
6-Lead TSOT
6-Lead LLP
250°C/W
190°C/W
240°C/W
See (Note 4)
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
2500V
250V
8-Lead MSOP
Charge Device Model (CDM)
1000V
Soldering
process
must
comply
with
National
Semiconductor's Reflow Temperature Profile specifications.
Refer to www.national.com/packaging. (Note 6)
Junction Temperature
Storage Temperature
+150°C
−65°C to +150°C
Electrical Characteristics
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, CL = 200 pF to GND, input code range 48 to 4047. Boldface
limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
STATIC PERFORMANCE
Resolution
12
12
Bits (min)
Bits (min)
Monotonicity
+2.2
−1.5
+0.18
−0.12
+1.1
−0.1
−0.2
−20
+8
LSB (max)
LSB (min)
LSB (max)
LSB (min)
mV (max)
%FSR (max)
%FSR (max)
µV/°C
INL
Integral Non-Linearity
−8
+0.6
−0.5
+10
−0.7
−0.7
DNL
Differential Non-Linearity
IOUT = 0
IOUT = 0
ZE
FSE
GE
Zero Code Error
Full-Scale Error
Gain Error
All ones Loaded to DAC register
ZCED
Zero Code Error Drift
VA = 3V
VA = 5V
−0.7
−1.0
ppm FSR/°C
ppm FSR/°C
TC GE Gain Error Tempco
ANALOG OUTPUT CHARACTERISTICS (VOUT
)
0
VREF
V (min)
V (max)
DAC121C085
DAC121C081
Output Voltage Range(Note 10)
0
VA
V (min)
V (max)
VA = 3V, IOUT = 200 µA
1.3
7.0
mV
mV
V
ZCO
FSO
IOS
Zero Code Output
VA = 5V, IOUT = 200 µA
VA = 3V, IOUT = 200 µA
2.984
4.989
56
Full Scale Output
VA = 5V, IOUT = 200 µA
V
VA = 3V, VOUT = 0V, Input Code = FFFh.
VA = 5V, VOUT = 0V, Input Code = FFFh.
VA = 3V, VOUT = 3V, Input Code = 000h.
VA = 5V, VOUT = 5V, Input Code = 000h.
mA
mA
mA
mA
Output Short Circuit Current
(ISOURCE
Output Short Circuit Current
(ISINK
)
69
−52
−75
IOS
IO
)
Continuous Output
Current (Note 10)
Available on the DAC output
11
mA (max)
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4
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
1500
1500
7.5
pF
pF
Ω
RL = ∞
RL = 2kΩ
CL
Maximum Load Capacitance
DC Output Impedance
ZOUT
REFERENCE INPUT CHARACTERISTICS- (DAC121C085 only)
Input Range Minimum
0.2
1.0
VA
V (min)
V (max)
kΩ
VREF
Input Range Maximum
Input Impedance
120
LOGIC INPUT CHARACTERISTICS (SCL, SDA)
VIH
VIL
0.7 x VA
0.3 x VA
±1
Input High Voltage
Input Low Voltage
Input Current
V (min)
V (max)
µA (max)
pF (max)
V (min)
IIN
CIN
Input Pin Capacitance (Note 10)
Input Hysteresis
3
VHYST
0.1 x VA
LOGIC INPUT CHARACTERISTICS (ADR0, ADR1)
VIH
VIL
IIN
VA- 0.8V
0.5
Input High Voltage
Input Low Voltage
Input Current
V (min)
V (max)
µA (max)
±1
LOGIC OUTPUT CHARACTERISTICS (SDA)
ISINK = 3 mA
ISINK = 6 mA
0.4
0.6
V (max)
V (max)
VOL
IOZ
Output Low Voltage
High-Impedence Output
Leakage Current
±1
µA (max)
5
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Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
POWER REQUIREMENTS
Supply Voltage Minimum
Supply Voltage Maximum
2.7
5.5
V (min)
V (max)
VA
Normal -- VOUT set to midscale. 2-wire interface quiet (SCL = SDA = VA). (output unloaded)
VA = 2.7V to 3.6V
IST_VA-1 VA DAC121C081 Supply Current
105
132
86
156
214
118
152
43
µA (max)
µA (max)
µA (max)
µA (max)
µA (max)
µA (max)
µW
VA = 4.5V to 5.5V
VA = 2.7V to 3.6V
IST_VA-5 VA DAC121C085 Supply Current
VA = 4.5V to 5.5V
98
VA = 2.7V to 3.6V
37
VREF Supply Current
IST_VREF
(DAC121C085 only)
VA = 4.5V to 5.5V
VA = 3.0V
53
61
380
730
Power Consumption
(VA & VREF for DAC121C085)
PST
VA = 5.0V
µW
Continuous Operation -- 2-wire interface actively addressing the DAC and writing to the DAC register. (output unloaded)
VA = 2.7V to 3.6V
VA = 4.5V to 5.5V
VA = 2.7V to 3.6V
VA = 4.5V to 5.5V
VA = 2.7V to 3.6V
VA = 4.5V to 5.5V
VA = 2.7V to 3.6V
VA = 4.5V to 5.5V
VA = 2.7V to 3.6V
VA = 4.5V to 5.5V
VA = 3.0V
134
192
225
374
101
142
193
325
33.5
49.5
480
1.06
810
2.06
220
300
320
500
155
220
235
410
55
µA (max)
µA (max)
µA (max)
µA (max)
µA (max)
µA (max)
µA (max)
µA (max)
µA (max)
µA (max)
µW
fSCL=400kHz
fSCL=3.4MHz
fSCL=400kHz
fSCL=3.4MHz
ICO_VA-1 VA DAC121C081 Supply Current
ICO_VA-5 VA DAC121C085 Supply Current
VREF Supply Current
ICO_VREF
(DAC121C085 only)
71.4
fSCL=400kHz
fSCL=3.4MHz
VA = 5.0V
mW
Power Consumption
PCO
(VA & VREF for DAC121C085)
VA = 3.0V
µW
VA = 5.0V
mW
Power Down -- 2-wire interface quiet (SCL = SDA = VA) after PD mode written to DAC register. (output unloaded)
VA = 2.7V to 3.6V
VA = 4.5V to 5.5V
VA = 3.0V
0.13
0.15
0.5
1.52
3.25
µA (max)
µA (max)
µW
Supply Current
(VA & VREF for DAC121C085)
All Power Down
Modes
IPD
Power Consumption
(VA & VREF for DAC121C085)
All Power Down
Modes
PPD
VA = 5.0V
0.9
µW
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6
A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, RL = Infinity, CL = 200 pF to GND. Boldface limits apply
for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
Limits
(Notes 9,
13)
Typical
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions (Note 13)
400h to C00h code change
Output Voltage Settling Time
(Note 10)
ts
SR
6
8.5
µs (max)
RL = 2kΩ, CL = 200 pF
Output Slew Rate
1
V/µs
nV-sec
nV-sec
kHz
Glitch Impulse
Code change from 800h to 7FFh
12
Digital Feedthrough
Multiplying Bandwidth(Note 12)
0.5
160
VREF = 2.5V ± 0.1Vpp
VREF = 2.5V ± 0.1Vpp
input frequency = 10kHz
VA = 3V
Total Harmonic Distortion(Note 12)
Wake-Up Time
70
dB
0.8
0.5
µsec
µsec
tWU
VA = 5V
DIGITAL TIMING SPECS (SCL, SDA)
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
100
400
3.4
1.7
KHz (max)
KHz (max)
MHz (max)
MHz (max)
fSCL
Serial Clock Frequency
SCL Low Time
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
4.7
1.3
160
320
us (min)
us (min)
ns (min)
ns (min)
tLOW
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
4.0
0.6
60
us (min)
us (min)
ns (min)
ns (min)
tHIGH
SCL High Time
120
Standard Mode
Fast Mode
High Speed Mode
250
100
10
ns (min)
ns (min)
ns (min)
tSU;DAT
Data Setup Time
0
3.45
us (min)
us (max)
Standard Mode
0
0.9
us (min)
us (max)
Fast Mode
tHD;DAT
Data Hold Time
0
70
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
0
150
ns (min)
ns (max)
Standard Mode
Fast Mode
High Speed Mode
4.7
0.6
160
us (min)
us (min)
ns (min)
Setup time for a start or a repeated
start condition
tSU;STA
Standard Mode
Fast Mode
High Speed Mode
4.0
0.6
160
us (min)
us (min)
ns (min)
Hold time for a start or a repeated start
condition
tHD;STA
Bus free time between a stop and start Standard Mode
4.7
1.3
us (min)
us (min)
tBUF
condition
Fast Mode
Standard Mode
Fast Mode
High Speed Mode
4.0
0.6
160
us (min)
us (min)
ns (min)
tSU;STO
Setup time for a stop condition
7
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Limits
(Notes 9,
13)
Typical
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions (Note 13)
Standard Mode
1000
20+0.1Cb
300
ns (max)
ns (min)
ns (max)
Fast Mode
trDA
Rise time of SDA signal
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
20
160
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
Standard Mode
250
20+0.1Cb
250
ns (max)
ns (min)
ns (max)
Fast Mode
tfDA
trCL
trCL1
tfCL
Fall time of SDA signal
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
20
160
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
Standard Mode
1000
20+0.1Cb
300
ns (max)
ns (min)
ns (max)
Fast Mode
Rise time of SCL signal
10
40
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
20
80
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
Standard Mode
1000
20+0.1Cb
300
ns (max)
ns (min)
ns (max)
Fast Mode
Rise time of SCL signal after a
repeated start condition and after an
acknowledge bit.
10
80
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
20
160
ns (min)
ns (max)
High Speed Mode, Cb = 400pF
Standard Mode
300
20+0.1Cb
300
ns (max)
ns (min)
ns (max)
Fast Mode
Fall time of a SCL signal
10
40
ns (min)
ns (max)
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
20
80
ns (min)
ns (max)
Capacitive load for each bus line (SCL
and SDA)
Cb
400
pF (max)
Pulse Width of spike suppressed
(Notes 11, 10)
Fast Mode
High Speed Mode
50
10
ns (max)
ns (max)
tSP
toutz
Fast Mode
High Speed Mode
87
38
270
60
ns (max)
ns (max)
SDA output delay (see Section 1.9)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package
input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond
the operating ratings, or the power supply polarity is reversed).
Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge
device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
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8
Note 6: Reflow temperature profiles are different for lead-free packages.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For
example, if VA is 3V, the digital input pins can be driven with a 5V logic device.
30004904
Note 8: To guarantee accuracy, it is required that VA and VREF be well bypassed.
Note 9: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 11: Spike suppression filtering on SCL and SDA will supress spikes that are less than 50ns for standard-fast mode and less than 10ns for hs-mode.
Note 12: Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the DAC Register will
digitally attenuate the signal at Vout.
Note 13: Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
MAXIMUM LOAD CAPACITANCE is the maximum capaci-
Specification Definitions
tance that can be driven by the DAC with output stability
maintained.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB,
which is VREF / 4096 = VA / 4096.
MONOTONICITY is the condition of being monotonic, where
the DAC has an output that never decreases when the input
code increases.
DIGITAL FEEDTHROUGH is a measure of the energy inject-
ed into the analog output of the DAC from the digital inputs
when the DAC output is not updated. It is measured with a
full-scale code change on the data bus.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest
value or weight of all bits in a word. Its value is 1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the
output amplitude falls 3dB below the input sine wave on
VREFIN with a full-scale code loaded into the DAC.
FULL-SCALE ERROR is the difference between the actual
output voltage with a full scale code (FFFh) loaded into the
DAC and the value of VA x 4095 / 4096.
POWER EFFICIENCY is the ratio of the output current to the
total supply current. The output current comes from the power
supply. The difference between the supply and output cur-
rents is the power consumed by the device without a load.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Zero and Full-
Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE
is Full-Scale Error and ZE is Zero Error.
SETTLING TIME is the time for the output to settle to within
1/2 LSB of the final value after the input code is updated.
GLITCH IMPULSE is the energy injected into the analog out-
put when the input code to the DAC register changes. It is
specified as the area of the glitch in nanovolt-seconds.
TOTAL HARMONIC DISTORTION (THD) is the measure of
the harmonics present at the output of the DACs with an ideal
sine wave applied to VREFIN. THD is measured in dB.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The end point method is used. INL for this product
is specified over a limited range, per the Electrical Tables.
WAKE-UP TIME is the time for the output to exit power-down
mode. This time is measured from the rising edge of SCL
during the ACK bit of the lower data byte to the time the output
voltage deviates from the power-down voltage of 0V.
ZERO CODE ERROR is the output error, or voltage, present
at the DAC output after a code of 000h has been entered.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the small-
est value or weight of all bits in a word. This value is
LSB = VREF / 2n
where VREF is the supply voltage for this product, and "n" is
the DAC resolution in bits, which is 12 for the DAC121C081.
9
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Transfer Characteristic
30004905
FIGURE 1. Input / Output Transfer Characteristic
Timing Diagrams
30004960
FIGURE 2. Serial Timing Diagram
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10
Typical Performance Characteristics VREF = VA, fSCL = 3.4MHz, TA = 25C, Input Code Range 48 to
4047, unless otherwise stated.
INL
DNL
30004920
30004921
INL/DNL vs Temperature at VA = 3.0V
INL/DNL vs Temperature at VA = 5.0V
30004922
30004923
INL/DNL vs VREFIN at VA = 3.0V
INL/DNL vs VREFIN at VA = 5.0V
30004924
30004925
11
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INL/DNL vs VA
Zero Code Error vs. VA
30004926
30004928
30004929
30004927
30004936
30004930
Zero Code Error vs. Temperature
Full Scale Error vs. VA
Full Scale Error vs. Temperature
Total Supply Current vs. VA
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12
VREF Supply Current vs. VA
Total Supply Current vs. Temperature @ VA = 3V
30004932
30004931
Total Supply Current vs. Temperature @ VA = 5V
5V Glitch Response
30004934
30004933
Power-On Reset
30004935
13
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1.0 Functional Description
1.1 DAC SECTION
1.2 OUTPUT AMPLIFIER
The DAC121C081 is fabricated on a CMOS process with an
architecture that consists of switches and resistor strings that
are followed by an output buffer.
The output amplifier is rail-to-rail, providing an output voltage
range of 0V to VA when the reference is VA. All amplifiers,
even rail-to-rail types, exhibit a loss of linearity as the output
approaches the supply rails (0V and VA, in this case). For this
reason, linearity is specified over less than the full output
range of the DAC. However, if the reference is less than VA,
there is only a loss in linearity in the lowest codes. The output
capabilities of the amplifier are described in the Electrical Ta-
bles.
For simplicity, a single resistor string is shown in Figure 3.
This string consists of 4096 equal valued resistors with a
switch at each junction of two resistors, plus a switch to
ground. The code loaded into the DAC register determines
which switch is closed, connecting the proper node to the
amplifier. The input coding is straight binary with an ideal out-
put voltage of:
The output amplifiers are capable of driving a load of 2 kΩ in
parallel with 1500 pF to ground or to VA. The zero-code and
full-scale outputs for given load currents are available in the
Electrical Characteristics Table.
VOUT = VREF x (D / 4096)
where D is the decimal equivalent of the binary code that is
loaded into the DAC register. D can take on any integer value
between 0 and 4095. This configuration guarantees that the
DAC is monotonic.
1.3 REFERENCE VOLTAGE
The DAC121C081 uses the supply (VA) as the reference.
With that said, VA must be treated as a reference. The Analog
output will only be as clean as the reference (VA). It is rec-
ommended that the reference be driven by a voltage source
with low output impedance.
The DAC121C085 comes with an external reference supply
pin (VREF). For the DAC121C085, it is important that VREF be
kept as clean as possible.
The Applications section describes a handful of ways to drive
the reference appropriately. Refer to Section 2.1 for details.
30004907
FIGURE 3. DAC Resistor String
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14
1.4 SERIAL INTERFACE
master is writing data, the slave ACKs after every data byte
is successfully received. When the master is reading data, the
master ACKs after every data byte is received to let the slave
know it wants to receive another data byte. When the master
wants to stop reading, it NACKs after the last data byte and
creates a Stop condition on the bus.
The I2C-compatible interface operates in all three speed
modes. Standard mode (100kHz) and Fast mode (400kHz)
are functionally the same and will be referred to as Standard-
Fast mode in this document. High-Speed mode (3.4MHz) is
an extension of Standard-Fast mode and will be referred to
as Hs-mode in this document. The following diagrams de-
scribe the timing relationships of the clock (SCL) and data
(SDA) signals. Pull-up resistors or current sources are re-
quired on the SCL and SDA busses to pull them high when
they are not being driven low. A logic zero is transmitted by
driving the output low. A logic high is transmitted by releasing
the output and allowing it to be pulled-up externally. The ap-
propriate pull-up resistor values will depend upon the total bus
capacitance and operating speed.
All communication on the bus begins with either a Start con-
dition or a Repeated Start condition. The protocol for starting
the bus varies between Standard-Fast mode and Hs-mode.
In Standard-Fast mode, the master generates a Start condi-
tion by driving SDA from high to low while SCL is high. In Hs-
mode, starting the bus is more complicated. Please refer to
section 1.4.3 for the full details of a Hs-mode Start condition.
A Repeated Start is generated to either address a different
device, or switch between read and write modes. The master
generates a Repeated Start condition by driving SDA low
while SCL is high. Following the Repeated Start, the master
sends out the slave address and a read/write bit as shown in
Figure 4. The bus continues to operate in the same speed
mode as before the Repeated Start condition.
1.4.1 Basic I2C Protocol
The I2C interface is bi-directional and allows multiple devices
to operate on the same bus. To facilitate this bus configura-
tion, each device has a unique hardware address which is
referred to as the "slave address." To communicate with a
particular device on the bus, the controller (master) sends the
slave address and listens for a response from the slave. This
response is referred to as an acknowledge bit. If a slave on
the bus is addressed correctly, it Acknowledges(ACKs) the
master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges
(NACKs) the master by letting SDA be pulled high. ACKs also
occur on the bus when data is being transmitted. When the
All communication on the bus ends with a Stop condition. In
either Standard-Fast mode or Hs-Mode, a Stop condition oc-
curs when SDA is pulled from low to high while SCL is high.
After a Stop condition, the bus remains idle until a master
generates a Start condition.
Please refer to the Phillips I2C® Specification (Version 2.1
Jan, 2000) for a detailed description of the serial interface.
30004911
FIGURE 4. Basic Operation.
1.4.2 Standard-Fast Mode
output updates to reflect the contents of the 16-bit DAC reg-
ister. Next, the master either sends another pair of data bytes,
generates a Stop condition to end communication, or gener-
ates a Repeated Start condition to communicate with another
device on the bus.
In Standard-Fast mode, the master generates a start condi-
tion by driving SDA from high to low while SCL is high. The
Start condition is always followed by a 7-bit slave address and
a Read/Write bit. After these eight bits have been transmitted
by the master, SDA is released by the master and the
DAC121C081 either ACKs or NACKs the address. If the slave
address matches, the DAC121C081 ACKs the master. If the
address doesn't match, the DAC121C081 NACKs the master.
For a read operation, the DAC121C081 sends out the upper
eight data bits of the DAC register. This is followed by an ACK
by the master. Next, the lower eight data bits of the DAC reg-
ister are sent to the master. The master then produces a
NACK by letting SDA be pulled high. The NACK is followed
by a master-generated Stop condition to end communication
on the bus, or a Repeated Start to communicate with another
device on the bus.
For a write operation, the master follows the ACK by sending
the upper eight data bits to the DAC121C081. Then the
DAC121C081 ACKs the transfer by driving SDA low. Next,
the lower eight data bits are sent by the master. The
DAC121C081 then ACKs the transfer. At this point, the DAC
15
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1.4.3 High-Speed (Hs) Mode
address to the DAC121C081, and communication continues
as shown above in the "Basic Operation" Diagram (see Figure
4).
For Hs-mode, the sequence of events to begin communica-
tion differ slightly from Standard-Fast mode. Figure 5 de-
scribes this in further detail. Initially, the bus begins running
in Standard-Fast mode. The master generates a Start condi-
tion and sends the 8-bit Hs master code (00001XXX) to the
DAC121C081. Next, the DAC121C081 responds with a
NACK. Once the SCL line has been pulled to a high level, the
master switches to Hs-mode by increasing the bus speed and
generating a Repeated Start condition (driving SDA low while
SCL is pulled high). At this point, the master sends the slave
When the master generates a Repeated Start condition while
in Hs-mode, the bus stays in Hs-mode awaiting the slave ad-
dress from the master. The bus continues to run in Hs-mode
until a Stop condition is generated by the master. When the
master generates a Stop condition on the bus, the bus must
be started in Standard-Fast mode again before increasing the
bus speed and switching to Hs-mode. ns16705
30004912
FIGURE 5. Beginning Hs-Mode Communication
1.4.4 I2C Slave (Hardware) Address
DAC121C085's on the 2-wire bus. When the bus is addressed
by the broadcast address, all the DAC121C081's and
DAC121C085's will respond and update synchronously. Fig-
ure 6 and Figure 7 describe how the master device should
address the DAC via the I2C-Compatible interface.
The DAC has a seven-bit I2C slave address. For the MSOP-8
version of the DAC, this address is configured by the ADR0
and ADR1 address selection inputs. For the DAC121C081,
the address is configured by the ADR0 address selection in-
put. ADR0 and ADR1 can be grounded, left floating, or tied to
VA. If desired, the address selection inputs can be set to VA/
2 rather than left floating. The state of these inputs sets the
address the DAC responds to on the I2C bus (see Table 1).
In addition to the selectable slave address, there is also a
broadcast address (1001000) for all DAC121C081's and
Keep in mind that the address selection inputs (ADR0 and
ADR1) are only sampled until the DAC is correctly addressed
with a non-broadcast address. At this point, the ADR0 and
ADR1 inputs TRI-STATE and the slave address is "locked".
Changes to ADR0 and ADR1 will not update the selected
slave address until the device is power-cycled.
TABLE 1. Slave Addresses
DAC121C081
DAC121C085 (MSOP-8)
(TSOT & LLP) *
Slave Address
[A6 - A0]
ADR1
Floating
Floating
Floating
GND
GND
GND
VA
ADR0
Floating
GND
VA
ADR0
Floating
0001100
0001101
0001110
0001000
0001001
0001010
1001100
1001101
1001110
1001000
GND
VA
Floating
GND
VA
---------------
---------------
---------------
---------------
---------------
---------------
Floating
GND
VA
VA
VA
--------------- Broadcast Address ---------------
* Pin-compatible alternatives to the DAC121C081 options are available with additional address options.
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16
1.4.5 Writing to the DAC Register
either sends the upper byte of the next data word to be con-
verted by the DAC, generates a Stop condition to end com-
munication, or generates a Repeated Start condition to begin
communication with another device on the bus. Until gener-
ating a Stop condition, the master can continuously write the
upper and lower data bytes to the DAC register. This allows
for a maximum DAC conversion rate of 188.9 kilo-conver-
sions per second in Hs-mode.
To write to the DAC, the master addresses the part with the
correct slave address (A6-A0) and writes a "zero" to the read/
write bit. If addressed correctly, the DAC returns an ACK to
the master. The master then sends out the upper data byte.
The DAC responds by sending an ACK to the master. Next,
the master sends the lower data byte to the DAC. The DAC
responds by sending an ACK again. At this point, the master
30004964
FIGURE 6. Typical Write to the DAC Register
1.4.6 Reading from the DAC Register
DAC sends the lower data byte to the master. Assuming only
one 16-bit data word is read, the master sends a NACK after
receiving the lower data byte. At this point, the master either
generates a Stop condition to end communication, or a Re-
peated Start condition to begin communication with another
device on the bus.
To read from the DAC register, the master addresses the part
with the correct slave address (A6-A0) and writes a "one" to
the read/write bit. If addressed correctly, the DAC returns an
ACK to the master. Next, the DAC sends out the upper data
byte. The master responds by sending an ACK to the DAC to
indicate that it wants to receive another data byte. Then the
30004963
FIGURE 7. Typical Read from the DAC Register
17
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1.5 DAC REGISTER
1.8 POWER-DOWN MODES
The DAC register, Figure 8, has sixteen bits. The first two bits
are always zero. The next two bits determine the mode of
operation (normal mode or one of three power-down modes).
The final twelve bits of the shift register are the data bits. The
data format is straight binary (MSB first, LSB last), with twelve
0's corresponding to an output of 0V and twelve 1's corre-
sponding to a full-scale output of VA - 1 LSB. When writing to
the DAC Register, VOUT will update on the rising edge of the
ACK following the lower data byte.
The DAC121C081 has three power-down modes. In power-
down mode, the supply current drops to 0.13µA at 3V and
0.15µA at 5V (typ). The DAC121C081 is put into power-down
mode by writing a one to PD1 and/or PD0. The outputs can
be set to high impedance, terminated by 2.5 kΩ to GND, or
terminated by 100 kΩ to GND (see Figure 8).
The bias generator, output amplifier, resistor string, and other
linear circuitry are all shut down in any of the power-down
modes. When the DAC121C081 is powered down, the value
written to the DAC register, including the power-down bits, is
saved. While the DAC is in power-down, the saved DAC reg-
ister contents can be read back. When the DAC is brought out
of power-down mode, the DAC register contents will be over-
written and VOUT will be updated with the new 12-bit data
value.
The time to exit power-down (Wake-Up Time) is typically
0.8µsec at 3V and 0.5µsec at 5V.
30004908
1.9 ADDITIONAL TIMING INFORMATION: toutz
FIGURE 8. DAC Register Contents
The toutz specification is provided to aid the design of the I2C
bus. After the SCL bus is driven low by the I2C master, the
SDA bus will be held for a short time by the DAC121C081.
This time is referred to as toutz. The following figure illustrates
the relationship between the fall of SCL, at the 30% threshold,
to the time when the DAC begins to transition the SDA bus.
The toutz specification only applies when the DAC is in control
of the SDA bus. The DAC is only in control of the bus during
an ACK by the DAC121C081 or a data byte read from the
DAC (see Figure 7).
1.6 POWER-ON RESET
The power-on reset circuit controls the output voltage of the
DAC during power-up. Upon application of power, the DAC
register is filled with zeros and the output voltage is 0 Volts.
The output remains at 0V until a valid write sequence is made
to the DAC.
When resetting the device, it is crutial that the VA supply be
lowered to a maximum of 200mV before the supply is raised
again to power-up the device. Dropping the supply to within
200mV of GND during a reset will ensure the ADC performs
as specified.
1.7 SIMULTANEOUS RESET
The broadcast address allows the I2C master to write a single
word to multiple DACs simultaneously. Provided that all of the
DACs exist on a single I2C bus, every DAC will update when
the broadcast address is used to address the bus. This fea-
ture allows the master to reset all of the DACs on a shared
I2C bus to a specific digital code. For instance, if the master
writes a power-down code to the bus with the broadcast ad-
dress, all of the DACs will power-down simultaneously.
30004965
FIGURE 9. Data Output Timing
The toutz specification is typically 87nsec in Standard-Fast
Mode and 38nsec in Hs-Mode.
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18
2.1.2 LM4050
2.0 Applications Information
Available with accuracy of 0.44%, the LM4050 shunt refer-
ence is also a good choice as a reference for the
DAC121C081. It is available in 4.096V and 5V versions and
comes in a space-saving 3-pin SOT23.
2.1 USING REFERENCES AS POWER SUPPLIES
While the simplicity of the DAC121C081 implies ease of use,
it is important to recognize that the path from the reference
input (VA for the DAC121C081 & VREF for the DAC121C085)
to VOUT will have essentially zero Power Supply Rejection
Ratio (PSRR). Therefore, it is necessary to provide a noise-
free supply voltage to the reference. In order to use the full
dynamic range of the DAC121C085, the supply pin (VA) and
VREF can be connected together and share the same supply
voltage. Since the DAC121C081 consumes very little power,
a reference source may be used as the supply voltage. The
advantages of using a reference source over a voltage regu-
lator are accuracy and stability. Some low noise regulators
can also be used. Listed below are a few reference and power
supply options for the DAC121C081. When using the
DAC121C081, it is important to treat the analog supply (VA)
as the reference.
2.1.1 LM4132
The LM4132, with its 0.05% accuracy over temperature, is a
good choice as a reference source for the DAC121C081. The
4.096V version is useful if a 0 to 4.095V output range is de-
sirable or acceptable. Bypassing the LM4132 VIN pin with a
0.1µF capacitor and the VOUT pin with a 2.2µF capacitor will
improve stability and reduce output noise. The LM4132
comes in a space-saving 5-pin SOT23.
30004914
FIGURE 11. The LM4050 as a power supply
The minimum resistor value in the circuit of Figure 11 must
be chosen such that the maximum current through the
LM4050 does not exceed its 15 mA rating. The conditions for
maximum current include the input voltage at its maximum,
the LM4050 voltage at its minimum, and the DAC121C081
drawing zero current. The maximum resistor value must allow
the LM4050 to draw more than its minimum current for regu-
lation plus the maximum DAC121C081 current in full opera-
tion. The conditions for minimum current include the input
voltage at its minimum, the LM4050 voltage at its maximum,
the resistor value at its maximum due to tolerance, and the
DAC121C081 draws its maximum current. These conditions
can be summarized as
R(min) = ( VIN(max) − VZ(min) ) /IZ(max)
and
30004913
FIGURE 10. The LM4132 as a power supply
R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )
where VZ(min) and VZ(max) are the nominal LM4050 output
voltages ± the LM4050 output tolerance over temperature, IZ
(max) is the maximum allowable current through the LM4050,
IZ(min) is the minimum current required by the LM4050 for
proper regulation, and IDAC(max) is the maximum
DAC121C081 supply current.
19
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2.1.3 LP3985
2.2 BIPOLAR OPERATION
The LP3985 is a low noise, ultra low dropout voltage regulator
with a 3% accuracy over temperature. It is a good choice for
applications that do not require a precision reference for the
DAC121C081. It comes in 3.0V, 3.3V and 5V versions,
among others, and sports a low 30 µV noise specification at
low frequencies. Since low frequency noise is relatively diffi-
cult to filter, this specification could be important for some
applications. The LP3985 comes in a space-saving 5-pin
SOT23 and 5-bump micro SMD packages.
The DAC121C081 is designed for single supply operation and
thus has a unipolar output. However, a bipolar output may be
obtained with the circuit in Figure 14. This circuit will provide
an output voltage range of ±5 Volts. A rail-to-rail amplifier
should be used if the amplifier supplies are limited to ±5V.
30004917
FIGURE 14. Bipolar Operation
30004915
The output voltage of this circuit for any code is found to be
VO = (VA x (D / 4096) x ((R1 + R2) / R1) - VA x R2 / R1)
FIGURE 12. Using the LP3985 regulator
where D is the input code in decimal form. With VA = 5V and
R1 = R2,
An input capacitance of 1.0µF without any ESR requirement
is required at the LP3985 input, while a 1.0µF ceramic ca-
pacitor with an ESR requirement of 5mΩ to 500mΩ is required
at the output. Careful interpretation and understanding of the
capacitor specification is required to ensure correct device
operation.
VO = (10 x D / 4096) - 5V
A list of rail-to-rail amplifiers suitable for this application are
indicated in Table 2.
TABLE 2. Some Rail-to-Rail Amplifiers
2.1.4 LP2980
Typ ISUPPLY
AMP
PKGS
ꢀTyp VOS
The LP2980 is an ultra low dropout regulator with a 0.5% or
1.0% accuracy over temperature, depending upon grade. It is
available in 3.0V, 3.3V and 5V versions, among others.
DIP-8
SOT23-5
LMC7111
0.9 mV
25 µA
SO-8
SOT23-5
LM7301
LM8261
0.03 mV
0.7 mV
620 µA
1 mA
SOT23-5
30004916
FIGURE 13. Using the LP2980 regulator
Like any low dropout regulator, the LP2980 requires an output
capacitor for loop stability. This output capacitor must be at
least 1.0µF over temperature, but values of 2.2µF or more will
provide even better performance. The ESR of this capacitor
should be within the range specified in the LP2980 data sheet.
Surface-mount solid tantalum capacitors offer a good combi-
nation of small size and ESR. Ceramic capacitors are attrac-
tive due to their small size but generally have ESR values that
are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large
size and have ESR values that may be too high at low tem-
peratures.
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20
2.3 DSP/MICROPROCESSOR INTERFACING
2.3.2 Interfacing to a Hs-mode Bus
Interfacing the DAC121C081 to microprocessors and DSPs
is quite simple. The following guidelines are offered to simplify
the design process.
Interfacing to a Hs-mode bus is very similar to interfacing to
a Standard-Fast mode bus. In Hs-mode, the specified rise
time of SCL is shortened. To create a faster rise time, the
master device (microcontroller) can drive the SCL bus high
and low. In other words, the microcontroller can drive the line
high rather than leaving it to the pull-up resistor. It is also pos-
sible to decrease the value of the pull-up resistors or increase
the pull-up current to meet the tighter timing specs. Please
refer to the I2C Specification for further details.
2.3.1 Interfacing to the 2-wire Bus
Figure 15 shows
a microcontroller interfacing to the
DAC121C081 via the 2-wire bus. Pull-up resistors (Rp)
should be chosen to create an appropriate bus rise time and
to limit the current that will be sunk by the open-drain outputs
of the devices on the bus. Please refer to the I2C Specification
for further details. Typical pull-up values to use in Standard-
Fast mode bus applications are 2kΩ to 10kΩ. SCL and SDA
series resisters (RS) near the DAC121C081 are optional. If
high-voltage spikes are expected on the 2-wire bus, series
resistors should be used to filter the voltage on SDA and SCL.
The value of the series resistance must be picked to ensure
the VIL threshold can be achieved. If used, RS is typically
51Ω.
2.4 LAYOUT, GROUNDING, AND BYPASSING
For best accuracy and minimum noise, the printed circuit
board containing the DAC121C081 should have separate
analog and digital areas. The areas are defined by the loca-
tions of the analog and digital power planes. Both of these
planes should be located on the same board layer. There
should be a single ground plane. A single ground plane is
preferred if digital return current does not flow through the
analog ground area. Frequently a single ground plane design
will utilize a "fencing" technique to prevent the mixing of ana-
log and digital ground current. Separate ground planes should
only be utilized when the fencing technique is inadequate.
The separate ground planes must be connected in one place,
preferably near the DAC121C081. Special care is required to
guarantee that digital signals with fast edge rates do not pass
over split ground planes. They must always have a continu-
ous return path below their traces.
The DAC121C081 power supply should be bypassed with a
4.7µF and a 0.1µF capacitor as close as possible to the device
with the 0.1µF right at the device supply pin. The 4.7µF ca-
pacitor should be a tantalum type and the 0.1µF capacitor
should be a low ESL, low ESR type. The power supply for the
DAC121C081 should only be used for analog circuits.
Avoid crossover of analog and digital signals and keep the
clock and data lines on the component side of the board.
These clock and data lines should have controlled
impedances.
30004909
FIGURE 15. Serial Interface Connection Diagram
21
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Physical Dimensions inches (millimeters) unless otherwise noted
6-Lead TSOT
Order Numbers DAC121C081CIMK
NS Package Number MK06A
6-Lead LLP
Order Numbers DAC121C081CISD
NS Package Number SDB06A
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22
8-Lead MSOP
Order Numbers DAC121C085CIMM
NS Package Number MUA08A
23
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