概述
规格参数
数据手册DM54194J 概述
4-Bit Bidirectional Universal Shift Registers 4位双向通用移位寄存器 移位寄存器
DM54194J 规格参数
| 是否无铅： | 含铅 | 是否Rohs认证： | 不符合 |
| 生命周期： | Obsolete | 包装说明： | DIP, DIP16,.3 |
| Reach Compliance Code： | unknown | 风险等级： | 5.78 |
| Is Samacsys： | N | 计数方向： | BIDIRECTIONAL |
| 系列： | TTL/H/L | JESD-30 代码： | R-GDIP-T16 |
| JESD-609代码： | e0 | 逻辑集成电路类型： | PARALLEL IN PARALLEL OUT |
| 最大频率@ Nom-Sup： | 25000000 Hz | 位数： | 4 |
| 功能数量： | 1 | 端子数量： | 16 |
| 最高工作温度： | 125 °C | 最低工作温度： | -55 °C |
| 输出极性： | TRUE | 封装主体材料： | CERAMIC, GLASS-SEALED |
| 封装代码： | DIP | 封装等效代码： | DIP16,.3 |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 5 V |
| 传播延迟（tpd）： | 26 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 5.08 mm | 子类别： | Shift Registers |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | NO |
| 技术： | TTL | 温度等级： | MILITARY |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 触发器类型： | POSITIVE EDGE |
| 宽度： | 7.62 mm | 最小 fmax： | 25 MHz |
| Base Number Matches： | 1 |
DM54194J 数据手册
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PDF下载June 1989
DM54194
4-Bit Bidirectional Universal Shift Registers
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register; it features parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating-mode-control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation, namely:
Clocking of the flip-flop is inhibited when both mode control
inputs are low. The mode controls of the DM54194/
DM74194 should be changed only while the clock input is
high.
Features
Y
Parallel (broadside) load
Shift right (in the direction Q toward Q )
Parallel inputs and outputs
Y
A
Shift left (in the direction Q toward Q )
D
Four operating modes:
D
A
Synchronous parallel load
Right shift
Left shift
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, S0
and S1, high. The data is loaded into the associated flip-
flops and appears at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibit-
ed.
Do nothing
Y
Positive edge-triggered clocking
Y
Direct overriding clear
Y
Typical clock frequency 36 MHz
Y
Typical power dissipation 195 mW
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data
input. When S0 is low and S1 is high, data shifts left syn-
chronously and new data is entered at the shift-left serial
input.
Connection Diagram
Dual-In-Line Package
TL/F/6564–1
Order Number DM54194J or DM54194W
See NS Package Number J16A or W16A
C
1995 National Semiconductor Corporation
TL/F/6564
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
5.5V
Operating Free Air Temperature Range
DM54
b
b
a
55 C to 125 C
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54194
Units
Symbol
Parameter
Min
4.5
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 4)
Pulse Width (Note 4)
IH
0.8
V
IL
b
0.8
16
I
I
mA
mA
MHz
OH
OL
f
0
36
25
CLK
W
t
Clock
Clear
Mode
Data
20
20
30
20
0
ns
ns
t
SU
Setup Time (Note 4)
t
t
Hold Time (Note 4)
ns
ns
H
Clear Release Time (Note 4)
Free Air Operating Temperature
25
REL
b
T
A
55
125
C
§
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
12 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
OH
CC
OH
2.4
3.4
0.2
e
e
Max, V
IL
IH
e
e
V
OL
Low Level Output
Voltage
V
V
Min, I
Max
CC
OL
0.4
V
e
e
Min, V
Max
IH
IL
@
Input Current Max
e
e
I
V
Max, V
5.5V
I
CC
I
1
mA
Input Voltage
e
e
e
e
e
e
I
I
I
I
High Level Input Current
Low Level Input Current
Short Circuit Output Current
Supply Current
V
CC
V
CC
V
CC
V
CC
Max, V
Max, V
2.4V
0.4V
40
mA
mA
mA
mA
IH
I
b
1.6
IL
I
b
b
57
63
Max (Note 2)
Max (Note 3)
20
OS
CC
39
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time.
CC
A
Note 3: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR and the serial inputs, I is tested with a momentary ground, then
CC
4.5V applied to CLOCK.
e
e
5V.
Note 4: T
25 C and V
§
A
CC
2
e
e
25 C (See Section 1 for Test Waveforms and Output Load)
Switching Characteristics at V
5V and T
§
CC
A
e
e
L
From (Input)
To (Output)
R
400X, C
15 pF
Max
L
Symbol
Parameter
Units
Min
f
t
Maximum Clock Frequency
25
MHz
ns
MAX
Propagation Delay Time
Low to High Level Output
Clock
to Q
PLH
22
26
30
t
Propagation Delay Time
High to Low Level Output
Clock
to Q
PHL
PHL
ns
ns
t
Propagation Delay Time
High to Low Level Output
Clear
to Q
Function Table
Inputs
Serial
Outputs
Mode
Clear
Parallel
Clock
Q
A
Q
Q
Q
D
B
C
S1
S0
Left
Right
A
B
C
D
L
X
X
H
L
X
X
H
H
H
L
X
L
X
X
X
X
X
H
L
X
X
X
H
L
X
X
a
X
X
b
X
X
c
X
X
d
L
L
L
L
H
H
H
H
H
H
H
e
Q
A0
Q
Q
C0
Q
D0
B0
a
H
L
b
c
d
u
u
u
u
u
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Q
Q
Q
An
An
Cn
Cn
B0
Bn
Bn
Dn
Dn
C0
Cn
Cn
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
H
H
L
X
X
X
Q
H
Bn
Bn
A0
L
Q
Q
L
L
X
Q
D0
e
e
H
High Level (steady state), L
Low Level (steady state), X
Don’t Care (any input, including transitions)
The level of steady state input at inputs A, B, C, or D, respectively
The level of Q , Q , Q , or Q , respectively, before the indicated steady state input conditions were established.
e
e
Transition from low to high level; a, b, c, d
u
Q
e
e
, Q , Q , Q
B0 C0
A0
D0
Dn
A
B
C
D
Q
, Q , Q , Q
Bn Cn
The level of Q , Q , Q , respectively, before the most recent
B
transition of the clock.
u
An
A
C
3
Logic Diagram
194
TL/F/6564–2
Timing Diagram
Typical Clear, Load, Right-Shift, Left-Shift,
Inhibit and Clear Sequences
TL/F/6564–3
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54194J
NS Package Number J16A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number DM54194W
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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Fax:
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49) 0-180-530 85 86
@
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Tel: (852) 2737-1600
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Email: cnjwge tevm2.nsc.com
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English Tel:
Fran3ais Tel:
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(
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49) 0-180-530 85 85
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
DM54194J 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| DM54194J-MIL | NSC | IC,SHIFT REGISTER,STD-TTL,DIP,16PIN,CERAMIC | 获取价格 |
|
| DM54194J-MIL | ROCHESTER | Parallel In Parallel Out | 获取价格 |
|
| DM54194J-MIL | TI | IC,SHIFT REGISTER,STD-TTL,DIP,16PIN,CERAMIC | 获取价格 |
|
| DM54194J/883 | TI | TTL/H/L SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16 | 获取价格 |
|
| DM54194J/883B | TI | IC,SHIFT REGISTER,STD-TTL,DIP,16PIN,CERAMIC | 获取价格 |
|
| DM54194J/883C | TI | IC,SHIFT REGISTER,STD-TTL,DIP,16PIN,CERAMIC | 获取价格 |
|
| DM54194J/883C | ROCHESTER | Parallel In Parallel Out | 获取价格 |
|
| DM54194W | NSC | 4-Bit Bidirectional Universal Shift Registers | 获取价格 |
|
| DM54194W/883 | ROCHESTER | Parallel In Parallel Out, TTL/H/L Series, 4-Bit, Bidirectional, True Output, TTL, CDFP16, DFP-16 | 获取价格 |
|
| DM54194W/883 | TI | TTL/H/L SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16 | 获取价格 |
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