DM54LS191W [NSC]
Synchronous 4-Bit Up/Down Counters with Mode Control; 同步4位加/减计数器，模式控制
| 型号： | DM54LS191W |
| 厂家： | 
National Semiconductor |
| 描述： | Synchronous 4-Bit Up/Down Counters with Mode Control |
| 文件： | 总8页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1989
DM54LS190/DM74LS190, DM54LS191/DM74LS191
Synchronous 4-Bit Up/Down Counters with Mode Control
General Description
These circuits are synchronous, reversible, up/down coun-
ters. The LS191 is a 4-bit binary counter and the LS190 is a
BCD counter. Synchronous operation is provided by having
all flip-flops clocked simultaneously, so that the outputs
change simultaneously when so instructed by the steering
logic. This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple clock)
counters.
Two outputs have been made available to perform the cas-
cading function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accom-
plish look-ahead for high-speed operation.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits count-
ing. Level changes at either the enable input or the down/
up input should be made only when the clock input is high.
The direction of the count is determined by the level of the
down/up input. When low, the counter counts up and when
high, it counts down.
Features
Y
Counts 8-4-2-1 BCD or binary
Y
Single down/up count control line
These counters are fully programmable; that is, the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The
output will change independent of the level of the clock in-
put. This feature allows the counters to be used as modulo-
N dividers by simply modifying the count length with the
preset inputs.
Y
Count enable control input
Y
Ripple clock output for cascading
Y
Asynchronously presettable with load control
Y
Parallel outputs
Y
Cascadable for n-bit applications
Y
Average propagation delay 20 ns
The clock, down/up, and load inputs are buffered to lower
the drive requirement; which significantly reduces the num-
ber of clock drivers, etc., required for long parallel words.
Y
Typical clock frequency 25 MHz
Y
Typical power dissipation 100 mW
Connection Diagram
Dual-In-Line-Package
TL/F/6405-1
Order Number DM54LS190J, DM54LS191J, DM54LS190W,
DM54LS191W, DM74LS190M, DM74LS191M, DM74LS190N, or DM74LS191N
See NS Package Number
J16A, M16A, N16A or W16A
C
1995 National Semiconductor Corporation
TL/F/6405
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
DM54LS
DM74LS
b
b
a
55 C to 125 C
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54LS190, LS191
DM74LS190, LS191
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
Nom
Max
V
V
V
Supply Voltage
5
5.5
4.75
2
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 4)
IH
0.7
0.8
V
IL
b
b
0.4
I
I
0.4
mA
mA
MHz
OH
OL
4
8
f
0
20
0
25
35
20
0
20
CLK
W
t
Pulse Width
(Note 4)
Clock
Load
25
35
20
0
ns
t
t
t
Data Setup Time (Note 4)
Data Hold Time (Note 4)
ns
ns
ns
SU
H
Enable Time to Clock (Note 4)
Free Air Operating Temperature
30
30
0
EN
b
T
A
55
125
70
C
§
’LS190 and ’LS191 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
DM54
DM74
DM54
DM74
DM74
Enable
Others
Enable
Others
Enable
Others
DM54
DM74
2.5
2.7
3.4
3.4
OH
CC
OH
e
e
Max, V
IL
IH
V
V
e
e
e
e
Min
V
OL
Low Level Output
Voltage
V
CC
Min, I
Max
0.25
0.35
0.25
0.4
OL
Max, V
IH
V
IL
0.5
0.4
0.3
0.1
60
e
e
Min
I
4 mA, V
CC
OL
@
Input Current Max
e
CC
I
I
I
I
I
V
Max
I
mA
mA
mA
e
Input Voltage
V
I
7V
e
2.7V
High Level Input
Current
V
V
Max
Max
Max
IH
CC
e
I
20
e
0.4V
b
1.08
Low Level Input
Current
V
V
IL
CC
e
I
b
0.4
100
100
e
(Note 2)
b
b
b
b
Short Circuit
V
CC
20
20
OS
CC
mA
mA
Output Current
e
Supply Current
V
CC
Max (Note 3)
20
35
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
CC
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: is measured with all inputs grounded and all outputs open.
Note 4: T
A
I
CC
e
e
5V.
25 C and V
§
A
CC
2
’LS190 and ’LS191 Switching Characteristics
e
e
at V
CC
5V and T
25 C (See Section 1 for Test Waveforms and Output Load)
§
A
e
R
L
2 kX
From (Input)
e
e
L
Symbol
Parameter
C
15 pF
C
50 pF
Max
Units
To (Output)
L
Min
Max
Min
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Clock
Frequency
MAX
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
20
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay Time
Low to High Level Output
Load to
Any Q
33
50
22
50
20
24
24
36
42
52
45
45
33
33
33
33
43
59
26
62
24
33
29
45
47
65
50
54
36
42
36
42
Propagation Delay Time
High to Low Level Output
Load to
Any Q
Propagation Delay Time
Low to High Level Output
Data to
Any Q
Propagation Delay Time
High to Low Level Output
Data to
Any Q
Propagation Delay Time
Low to High Level Output
Clock to
Ripple Clock
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Clock
Propagation Delay Time
Low to High Level Output
Clock to
Any Q
Propagation Delay Time
High to Low Level Output
Clock to
Any Q
Propagation Delay Time
Low to High Level Output
Clock to
Max/Min
Propagation Delay Time
High to Low Level Output
Clock to
Max/Min
Propagation Delay Time
Low to High Level Output
Up/Down to
Ripple Clock
Propagation Delay Time
High to Low Level Output
Up/Down to
Ripple Clock
Propagation Delay Time
Low to High Level Output
Down/Up to
Max/Min
Propagation Delay Time
High to Low Level Output
Down/Up to
Max/Min
Propagation Delay Time
Low to High Level Output
Enable to
Ripple Clock
Propagation Delay Time
High to Low Level Output
Enable to
Ripple Clock
3
Logic Diagrams
LS190 Decade Counters
e
e
GND
Pin (16)
V
, Pin (8)
CC
TL/F/6405–2
4
Logic Diagrams (Continued)
LS191 Binary Counters
e
e
GND
Pin (16)
V
CC
, Pin (8)
TL/F/6405–3
5
Timing Diagrams
LS190 Decade Counters
Typical Load, Count, and Inhibit Sequences
TL/F/6405–4
LS191 Binary Counters
Typical Load, Count, and Inhibit Sequences
TL/F/6405–5
6
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS190J, DM54LS191J
NS Package Number J16A
16-Lead Small Outline Molded Package (M)
Order Number DM74LS190M, DM74LS191M
NS Package Number M16A
7
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS190N, DM74LS191N
NS Package Number N16E
16-Lead Ceramic Flat Package (W)
Order Number DM54LS190W or DM54LS191W
NS Package Number W16A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
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to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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effectiveness.
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