DM54LS295AW [NSC]
IC LS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14, CERAMIC, FP-14, Shift Register;
| 型号： | DM54LS295AW |
| 厂家： | 
National Semiconductor |
| 描述： | IC LS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14, CERAMIC, FP-14, Shift Register CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1992
DM54LS295A/DM74LS295A
4-Bit Shift Register with TRI-STATE Outputs
É
General Description
Features
Y
Fully synchronous serial or parallel data transfers
Negative edge-triggered clock input
Parallel enable mode control input
The ’LS295A is a 4-bit shift register with serial and parallel
synchronous operating modes, and independent TRI-
STATE output buffers. The Parallel Enable input (PE) con-
trols the shift-right or parallel load operation. All data trans-
fers and shifting occur synchronous with the HIGH-to-LOW
clock transition.
Y
Y
Y
TRI-STATE bussable output buffers
The TRI-STATE output buffers are controlled by an active
HIGH Output Enable input (OE). Disabling the output buffers
does not affect the shifting or loading of input data, but it
does inhibit serial expansion. The device is fabricated with
the Schottky barrier diode process for high speed.
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL/F/10183–2
e
e
V
Pin 14
CC
GND
Pin 7
TL/F/10183–1
Order Number DM54LS295AJ, DM54LS295AW,
DM74LS295AM or DM74LS295AN
See NS Package Number J14A, M14A, N14A or W14B
Pin Names
Description
PE
Parallel Enable Input (Active HIGH)
Serial Data Input
Parallel Data Inputs
D
S
P0–P3
OE
TRI-STATE Output Enable Input (Active HIGH)
Clock Pulse Input (Active Falling Edge)
TRI-STATE Outputs
CP
O0–O3
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/10183
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
DM54LS
DM74LS
b
b
a
55 C to 125 C
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54LS295A
DM74LS295A
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
IH
0.7
0.8
V
IL
b
b
2.6
I
I
1.0
mA
mA
OH
OL
4
8
b
T
A
55
125
0
70
C
§
t
t
(H)
20
20
20
s
ns
ns
ns
(L)
D , P to CP
S n
20
s
t
t
(H)
(L)
Hold Time HIGH or LOW
D , P to CP
10
10
10
10
h
h
S
n
t
t
(H)
(L)
Setup Time HIGH or LOW
PE to CP
20
20
20
20
s
s
t
t
(H)
(L)
Hold Time HIGH or LOW
PE to CP
0
0
0
0
h
ns
ns
h
t
w
(L)
CP Pulse Width LOW
20
20
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
Max,
V
V
I
CC
I
High Level Output
Voltage
V
V
DM54
DM74
DM54
DM74
DM74
2.4
2.4
OH
CC
OH
e
Max
IL
e
e
Max,
V
OL
Low Level Output
Voltage
V
V
Min, I
0.4
CC
OL
e
Min
IH
0.5
0.4
V
e
e
I
4 mA, V
CC
Min
OL
@
Input Current Max
e e
Max, V
I
I
V
V
7V
I
CC
0.1
20
mA
e
Input Voltage
10V (DM54)
I
e
e
e
e
e
I
I
I
High Level Input Current
Low Level Input Current
V
CC
V
CC
V
CC
Max, V
Max, V
Max
2.7V
0.4V
mA
IH
IL
I
I
b
0.4
100
100
mA
b
b
b
b
Short Circuit
DM54
DM74
20
20
OS
mA
Output Current
(Note 2)
e
e
4.5V, CP
I
Supply Current
Outputs ON
V
Max, P
e
GND
CC
CC
PE, DS, OE
n
23
25
mA
mA
e
K
e
P , OE, CP
e
Outputs OFF
V
CC
Max, PE, DS
e
4.5V
GND
n
2
Electrical Characteristics (Continued)
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
I
Off-State Output Current
with High Level Output
Voltage Applied
V
V
Max, V
2.7V
OZH
CC
O
e
e
Min, V
IL
Max
20
mA
IH
e
Max, V
e
I
Off-State Output Current
with Low Level Output
Voltage Applied
V
V
0.4V
OZL
CC
O
e
e
b
20
Min, V
IL
Max
mA
IH
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
CC
A
e a
e a
25 C
Switching Characteristics V
5.0V, T
§
CC
A
e
e
R
C
2 kX,
L
15 pF
Symbol
Parameter
Units
L
Min
30
Max
f
Maximum Shift Frequency
Propagation Delay
MHz
ns
max
t
t
30
26
PLH
CP to Q
PHL
n
t
t
Output Enable Time
Output Disable Time
18
20
PZH
ns
ns
PZL
t
t
24
20
PHZ
PLZ
3
Functional Description
This device is a 4-bit shift register with serial and parallel
synchronous operating modes. It has a Serial Data (D ) and
S
four Parallel Data (P0–P3) inputs and four parallel TRI-
STATE output buffers (O0–O3). When the Parallel Enable
(PE) input is HIGH, data is transferred from the Parallel Data
inputs (P0–P3) into the register synchronous with the HIGH-
to-LOW transition of the Clock (CP). When the PE is LOW, a
HIGH-to-LOW transition on the clock transfers the serial
The TRI-STATE output buffers are controlled by an active
HIGH Output Enable input (OE). When the OE is HIGH, the
four register outputs appear at the O0–O3 outputs. When
OE is LOW, the outputs are forced to a high impedance
OFF state. The TRI-STATE output buffers are completely
independent of the register operation, i.e., the input tran-
sitions on the OE input do not affect the serial or parallel
data transfers of the register. If the outputs are tied togeth-
er, all but one device must be in the high impedance state to
avoid high currents that would exceed the maximum ratings.
Designers should ensure that Output Enable signals to TRI-
STATE devices whose outputs are tied together are de-
signed so there is no overlap.
data on the D input to the register Q0, and shifts data from
S
Q0 to Q1, Q1 to Q2 and Q2 to Q3. The input data and
parallel enable are fully edge-triggered and must be stable
only one setup time before the HIGH-to-LOW clock tran-
sition.
Mode Select Table
Inputs
PE CP
Operating
Mode
Outputs
D
S
P
n
Q0 Q1 Q2 Q3
I
I
K
K
I
X
L
q
q
q
q
q
q
0
1
2
Shift Right
h
X
H
0
1
2
Parallel Load
h
K
X
p
p0 p1 p2 p3
n
*The indicated data appears at the Q outputs when OE is HIGH. When OE is
LOW, the indicated data is loaded into the register, but the outputs are all
forced to the high impedance OFF state.
e
(q )
n
p
Lower case letters indicate the state of the referenced input (or
n
output) one set-up time prior to the HIGH-to-LOW clock transition.
e
transition.
I
LOW Voltage Level one set-up time prior to the HIGH-to-LOW clock
e
transition.
h
HIGH Voltage Level one set-up time prior to the HIGH-to-LOW clock
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
Logic Diagram
TL/F/10183–3
4
Physical Dimensions inches (millimeters)
14-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS295AJ
NS Package Number J14A
14-Lead Small Outline Molded Package (M)
Order Number DM74LS295AM
NS Package Number M14A
5
Physical Dimensions inches (millimeters) (Continued)
14-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS295AN
NS Package Number N14A
14-Lead Ceramic Flat Package (W)
Order Number DM54LS295AW
NS Package Number W14B
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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