DM54LS469 [NSC]
DM54LS469/DM74LS469 8-Bit Up/Down Counter; DM54LS469 / DM74LS469 8位向上/向下计数器
| 型号： | DM54LS469 |
| 厂家： | 
National Semiconductor |
| 描述： | DM54LS469/DM74LS469 8-Bit Up/Down Counter |
| 文件： | 总4页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1989
DM54LS469/DM74LS469 8-Bit Up/Down Counter
General Description
The ‘LS469 is an 8-bit synchronous up/down counter with
parallel load and hold capability. Three function-select in-
puts (LD, UD, CBI) provide one of four operations which
occur synchronously on the rising edge of the clock (CK).
The output register (Q –Q ) is enabled when OE is LOW,
7 0
and disabled (HI-Z) when OE is HIGH. The output drivers
will sink the 24 mA required for many bus-interface stan-
dards. Two or more ‘LS469 octal up/down counters may be
cascaded to provide larger counters.
The LOAD operation loads the inputs (D –D ) into the out-
7
0
put register (Q –Q ). The HOLD operation holds the previ-
7
0
Features/Benefits
Y
ous value regardless of clock transitions. The INCREMENT
operation adds one to the output register when the carry-in
8-bit up/down counter for microprogram-counter, DMA
controller and general-purpose counting applications
e
input is TRUE (CBI LOW), otherwise the operation is a
HOLD. The carry-out (CBO) is TRUE (CBO LOW) when
e
Y
8 bits matches byte boundaries
the output register (Q –Q ) is all HIGHs, otherwise FALSE
0
Y
7
Bus-structured pinout
e
(CBO HIGH). The DECREMENT operation subtracts one
from the output register when the borrow-in input is TRUE
Y
24-pin SKINNYDIP saves space
Y
TRI-STATE outputs drive bus lines
É
Low current PNP inputs reduce loading
e
(CBI LOW), otherwise the operation is a HOLD. The bor-
row-out (CBO) is TRUE (CBO LOW) when the output reg-
Y
e
Y
Expandable in 8-bit increments
e
ister (Q –Q ) is all LOWs, otherwise FALSE (CBO HIGH).
7
0
Connection Diagram
Standard Test Load
Top View
TL/L/8333–3
TL/L/8333–1
Order Number DM54LS469J,
DM74LS469J or DM74LS469N
See NS Package Number J24F or N24C
Function Table
OE CK LD UD CBI D7–D0 Q7–Q0
Operation
H
L
L
L
L
L
X
X
L
X
X
L
X
X
H
L
X
D
X
X
X
X
Z
D
Q
HI-Z
LOAD
HOLD
u
u
u
u
u
H
H
H
H
L
Q plus 1 INCREMENT
HOLD
Q minus 1 DECREMENT
H
H
H
L
Q
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/L/8333
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Off-State Output Voltage
Storage Temperature
5.5V
b
a
65 C to 150 C
§
§
Supply Voltage V
Input Voltage
7V
CC
5.5V
Operating Conditions
Military
Commercial
Symbol
Parameter
Units
Min
Typ
Max
5.5
Min
4.75
0
Typ
Max
5.25
75
V
T
Supply Voltage
4.5
5
5
V
CC
b
Operating Free-Air Temperature
55
125*
C
§
A
Low
40
35
25
50
0
10
t
Width of Clock
ns
W
High
30
60
0
t
t
Set Up Time
Hold Time
SU
ns
b
b
15
15
h
*Case Temperature
Electrical Characteristics Over Operating Conditions
²
Symbol
Parameter
Test Conditions
Min
Typ
Max
0.8
Units
V
V
V
V
Low-Level Input Voltage
High-Level Input Voltage
Input Clamp Voltage
IL
2
V
IH
IC
e
e
e
e
e
eb
I
b
1.5
V
V
V
V
MIN
I
18 mA
V
CC
CC
CC
CC
CC
e
e
e
b
0.25
25
I
I
I
Low-Level Input Current
High-Level Input Current
Maximum Input Current
MAX
MAX
MAX
MIN
V
V
V
0.4V
mA
mA
mA
IL
I
I
I
2.4V
5.5V
IH
I
1
V
V
V
e
e
MIL
I
I
I
I
12 mA
24 mA
OL
OL
OH
OH
e
V
V
Low-Level Output Voltage
High-Level Output Voltage
Off-State Output Current
0.8V
0.5
V
OL
IL
e
2V
IH
COM
MIL
e
V
V
V
MIN
CC
eb
eb
2 mA
e
0.8V
2.4
V
OH
IL
e
2V
IH
COM
3.2 mA
e
V
V
V
MAX
CC
e
b
I
V
0.4V
100
mA
OZL
O
e
0.8V
IL
e
2V
IH
e
e
I
I
I
V
V
2.4V
0V
100
mA
mA
mA
OZH
OS
O
e
b
b
Output Short-Circuit Current*
V
V
5.0V
MAX
30
130
CC
O
e
Supply Current
120
180
CC
CC
*No more than one output should be shorted at a time and duration of the short-circuit should not exceed one second
e
e
25 C.
²
All typical values are V
5V, T
§
CC
A
Switching Characteristics Over Operating Conditions
Test Conditions
Military
Typ
Commercial
Symbol
Parameter
Units
(See Test Load/Waveforms)
Min
Max
Min
12.5
Typ
Max
f
t
t
t
t
t
Maximum Clock Frequency
CBI to CBO Delay
Clock to Q
10.5
MHz
ns
MAX
35
20
55
20
20
60
35
95
45
45
35
20
55
20
20
50
30
80
35
35
PD
e
e
e
C
50 pF
200X
390X
L
ns
PD
R
1
2
Clock to CBO
ns
PD
R
Output Enable Delay
Output Disable Delay
ns
PZX
PXZ
ns
2
Logic Diagram
LS469
TL/L/8333–2
3
Physical Dimensions inches (millimeters)
24-Pin Narrow Ceramic Dual-In-Line Package (J)
Order Number DM54LS469J or DM74LS469J
NS Package Number J24F
24-Pin Narrow Plastic Dual-In-Line Package (N)
Order Number DM74LS469N
NS Package Number N24C
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