DM74165 [NSC]
8-Bit Parallel-to-Serial Converter; 8位并行 - 串行转换器
| 型号： | DM74165 |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit Parallel-to-Serial Converter |
| 文件： | 总7页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1989
54165/DM74165
8-Bit Parallel-to-Serial Converter
General Description
The ’165 is an 8-bit parallel load or serial-in register with
complementary outputs available from the last stage. Paral-
lel inputting occurs asynchronously when the Parallel Load
(PL) input is LOW. With PL HIGH, serial shifting occurs on
the rising edge of the clock; new data enters via the Serial
Data (D ) input. The 2-input OR clock can be used to com-
S
bine two independent clock sources, or one input can act as
an active LOW clock enable.
Connection Diagram
Logic Symbol
Dual-In-Line-Package
TL/F/9782–2
e
e
V
Pin 16
CC
GND
Pin 8
TL/F/9782–1
Order Number 54165DMQB, 54165FMQB or DM74165N
See NS Package Number J16A, N16E or W16A
Pin Names
Description
CP1, CP2
Clock Pulse Inputs (Active Rising Edge)
Serial Data Input
D
S
PL
Asynchronous Parallel Load Input
(Active LOW)
P0–P7
Q7
Parallel Data Inputs
Serial Output from Last Stage
Complementary Output
Q7
C
1995 National Semiconductor Corporation
TL/F/9782
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
5.5V
Operating Free Air Temperature Range
54
DM74
b
b
a
55 C to 125 C
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
54165
DM74165
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
IH
0.8
0.8
V
IL
b
b
I
I
0.8
16
125
0.8
16
70
mA
mA
OH
OL
b
T
A
55
0
C
§
t (H)
10
10
10
s
t (L)
ns
ns
ns
ns
ns
P
to PL
n
10
s
t (H)
h
t (L)
Hold Time HIGH or LOW
P to PL
n
10
10
0
0
h
t (H)
Setup Time HIGH or LOW
D to CP
S
20
20
20
20
s
t (L)
s
n
t (H)
h
t (L)
Hold Time HIGH or LOW
D to CP
S
0
0
0
0
h
n
t (H)
s
Setup Time HIGH
30
30
CP1 to CP2 or CP2 to CP1
t
t
t
(H)
(L)
CP Pulse Width HIGH
n
25
15
45
25
15
45
ns
ns
ns
w
PL Pulse Width LOW
w
Recovery Time, PL to CP
rec
n
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e
e
e b
b
1.5
V
V
V
Input Clamp Voltage
V
V
V
V
Min, I
Min, I
12 mA
Max, V
Min
V
V
V
I
CC
CC
CC
CC
I
e
e
e
High Level Output Voltage
Low Level Output Voltage
Max
PL
2.4
3.4
0.2
OH
OL
OH
IL
Min, V
IH
0.4
@
Input Current Max
e
I
Max, V
5.5V
I
I
1
mA
Input Voltage
e
e
e
e
I
High Level Input Current
V
CC
V
CC
V
CC
Max, V
2.4V
80
40
IH
I
mA
Inputs
e
b
I
I
I
Low Level Input Current
Max, V
Max
0.4V
PL
3.2
1.6
IL
I
mA
mA
mA
b
Inputs
54
b
b
b
Short Circuit
20
18
55
55
OS
CC
Output Current
(Note 2)
b
DM74
e
e
ß
Supply Current
V
P
Max, PL
CC
63
e
e
K, CP , CP
2
4.5V
n
1
2
Switching Characteristics
5.0V, T
e a
e a
25 C (See Section 1 for waveforms and load configurations)
V
CC
§
A
e
e
C
15 pF
L
Symbol
Parameter
R
400X
Units
L
Min
Max
f
Maximum Clock Frequency
20
MHz
ns
max
t
t
Propagation Delay
PL to Q7 or Q7
31
40
PLH
PHL
t
t
Propagation Delay
CP1 to Q7 or Q7
24
31
PLH
PHL
ns
ns
ns
t
t
Propagation Delay
P7 to Q7
17
36
PLH
PHL
t
t
Propagation Delay
P7 to Q7
27
27
PLH
PHL
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time.
CC
A
Functional Description
The ’165 contains eight clocked master/slave RS flip-flops
connected as a shift register with auxiliary gating to provide
overriding asynchronous parallel entry. Parallel data enters
when the PL signal is LOW. The parallel data can change
while PL is LOW provided that the recommended setup and
hold times are observed.
by applying a HIGH signal. To avoid double clocking, how-
ever, the inhibit signal should only go HIGH while the clock
is HIGH. Otherwise, the rising inhibit signal will cause the
same response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data
can change at any time, provided only that the recommend-
ed setup and hold times are observed, with respect to the
rising edge of the clock.
For clocked operation, PL must be HIGH. The two clock
inputs perform identically; one can be used as a clock inhibit
Truth Table
CP
Contents
PL
Response
1
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
H
H
H
H
X
L
X
L
L
L
P0
P1
Q0
Q1
Q0
Q1
P2
Q1
Q2
Q1
Q2
P3
Q2
Q3
Q2
Q3
P4
Q3
Q4
Q3
Q4
P5
Q4
Q5
Q4
Q5
P6
Q5
Q6
Q5
Q6
P7
Q6
Q7
Q6
Q7
Parallel Entry
Right Shift
No Change
Right Shift
No Change
D
S
H
Q0
L
L
D
S
H
Q0
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
e
L
Positive Rising Edge
Logic Diagram
TL/F/9782–3
3
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54165DMQB
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74165N
NS Package Number N16E
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 54165FMQB
NS Package Number W16A
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