DM74191 [NSC]
Synchronous Up/Down 4-Bit Binary Counter with Mode Control; 同步向上/向下4位二进制计数器与模式控制
| 型号： | DM74191 |
| 厂家： | 
National Semiconductor |
| 描述： | Synchronous Up/Down 4-Bit Binary Counter with Mode Control |
| 文件： | 总6页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1989
54191/DM54191/DM74191 Synchronous Up/Down
4-Bit Binary Counter with Mode Control
General Description
This circuit is a synchronous, reversible, up/down counter.
The 191 is a 4-bit binary counter. Synchronous operation is
provided by having all flip-flops clocked simultaneously so
that the outputs change simultaneously when so instructed
by the steering logic. This mode of operation eliminates the
output counting spikes normally associated with asynchro-
nous (ripple clock) counters.
Two outputs have been made available to perform the cas-
cading function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accom-
plish look-ahead for high-speed operation.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits count-
ing. Level changes at either the enable input or the down/
up input should be made only when the clock input is high.
The direction of the count is determined by the level of the
down/up input. When low, the counter counts up and when
high, it counts down.
Features
Y
Single down/up count control line
This counter is fully programmable; that is, the outputs may
be preset to either level by placing a low on the load input
and entering the desired data at the data inputs. The output
will change independent of the level of the clock input. This
feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
Y
Count enable control input
Y
Ripple clock output for cascading
Y
Asynchronously presettable with load control
Y
Parallel outputs
Y
Cascadable for n-bit applications
The clock, down/up, and load inputs are buffered to lower
the drive requirement; which significantly reduces the num-
ber of clock drivers, etc., required for long parallel words.
Y
Alternate Military/Aerospace device (54191) is avail-
able. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6562–1
Order Number 54191DMQB, 54191FMQB,
DM54191J, DM54191W or DM74191N
See NS Package Number J16A, N16E or W16A
C
1995 National Semiconductor Corporation
TL/F/6562
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
5.5V
Operating Free Air Temperature Range
DM54 and 54
DM74
b
b
a
55 C to 125 C
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54191
DM74191
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 4)
IH
0.8
0.8
V
IL
b
0.8
16
b
I
I
0.8
16
20
mA
mA
MHz
OH
OL
f
0
20
0
25
35
28
0
CLK
W
t
Pulse Width
(Note 4)
Clock
Load
25
35
28
0
ns
t
t
t
Data Setup Time (Note 4)
Hold Time (Note 4)
ns
ns
ns
SU
H
Load Release Time (Note 4)
Free Air Operating Temperature
30
30
0
REL
b
T
A
55
125
70
C
§
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
12 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
OH
CC
OH
2.4
3.4
0.2
e
e
Max, V
IL
IH
e
e
V
OL
Low Level Output
Voltage
V
V
Min, I
Max
CC
OL
0.4
V
e
e
Min, V
Max
IH
IL
@
Input Current Max
e
e
I
I
I
V
Max, V
5.5V
I
CC
1
mA
mA
Input Voltage
e
High Level Input
Current
V
V
Max
Enable
120
40
IH
CC
e
2.4V
I
Others
Enable
Others
DM54
DM74
DM54
DM74
e
b
4.8
I
I
I
Low Level Input
Current
V
V
Max
IL
CC
mA
mA
mA
e
0.4V
I
b
1.6
e
(Note 2)
b
b
b
Short Circuit
V
CC
Max
20
18
65
65
OS
CC
Output Current
b
e
(Note 3)
Supply Current
V
CC
Max
65
65
99
105
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
CC
Note 2: Not more than one output should be shorted at a time.
Note 3: I is measured with all inputs grounded and all outputs open.
A
CC
e
e
5V.
Note 4: T
25 C and V
§
A
CC
2
e
e
25 C (See Section 1 for Test Waveforms and Output Load)
Switching Characteristics at V
5V and T
§
CC
A
e
e
L
From (Input)
To (Output)
R
400X, C
15 pF
Max
L
Symbol
Parameter
Units
Min
f
t
Maximum Clock Frequency
20
MHz
ns
MAX
Propagation Delay Time
Low to High Level Output
Load to
Any Q
PLH
33
70
22
70
20
24
24
36
42
52
45
45
33
33
24
24
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay Time
High to Low Level Output
Load to
Any Q
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay Time
Low to High Level Output
Data to
Any Q
Propagation Delay Time
High to Low Level Output
Data to
Any Q
Propagation Delay Time
Low to High Level Output
Clock to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Carry
Propagation Delay Time
Low to High Level Output
Clock to
Any Q
Propagation Delay Time
High to Low Level Output
Clock to
Any Q
Propagation Delay Time
Low to High Level Output
Clock to
Max/Min
Propagation Delay Time
High to Low Level Output
Clock to
Max/Min
Propagation Delay Time
Low to High Level Output
Down/Up to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Down/Up to
Ripple Carry
Propagation Delay Time
Low to High Level Output
Down/Up to
Max/Min
Propagation Delay Time
High to Low Level Output
Down/Up to
Max/Min
Propagation Delay Time
Low to High Level Output
Enable G to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Enable G to
Ripple Carry
3
Logic Diagram
191 Binary Counter
e
e
GND
Pin (16)
V
CC
, Pin (8)
TL/F/6562–2
4
Timing Diagrams
191 Decade Counter
Typical Load, Count, and Inhibit Sequences
TL/F/6562–3
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54191DMQB or DM54191J
NS Package Number J16A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74191N
NS Package Number N16E
16-Lead Ceramic Flat Package (W)
Order Number 54191FMQB or DM54191W
NS Package Number W16A
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
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to the user.
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support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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相关型号：
DM74191N
Binary Counter, TTL/H/L Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, TTL, PDIP16, PLASTIC, DIP-16
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