DM74LS123M [NSC]
Dual Retriggerable One-Shot with Clear and Complementary Outputs; 双可重触发单稳态具有清零和互补输出
| 型号： | DM74LS123M |
| 厂家： | 
National Semiconductor |
| 描述： | Dual Retriggerable One-Shot with Clear and Complementary Outputs |
| 文件： | 总6页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1991
DM74LS123 Dual Retriggerable One-Shot
with Clear and Complementary Outputs
Y
Compensated for V
and temperature variations
CC
General Description
Y
Y
Y
Triggerable from CLEAR input
DTL, TTL compatible
The DM74LS123 is a dual retriggerable monostable multivi-
brator capable of generating output pulses from a few nano-
seconds to extremely long duration up to 100% duty cycle.
Each device has three inputs permitting the choice of either
leading edge or trailing edge triggering. Pin (A) is an active-
low transition trigger input and pin (B) is an active-high tran-
sition trigger input. The clear (CLR) input terminates the out-
put pulse at a predetermined time independent of the timing
components. The clear input also serves as a trigger input
when it is pulsed with a low level pulse transition (ß). To
obtain the best trouble free operation from this device
please read the operating rules as well as the NSC one-shot
application notes carefully and observe recommendations.
Input clamp diodes
Functional Description
The basic output pulse width is determined by selection of
an external resistor (R ) and capacitor (C ). Once triggered,
X
the basic pulse width may be extended by retriggering the
gated active-low transition or active-high transition inputs or
be reduced by use of the active-low or CLEAR input. Retrig-
gering to 100% duty cycle is possible by application of an
input pulse train whose cycle time is shorter than the output
cycle time such that a continuous ‘‘HIGH’’ logic state is
maintained at the ‘‘Q’’ output.
X
Features
Y
DC triggered from active-high transition or active-low
transition inputs
Y
Retriggerable to 100% duty cycle
Connection Diagram
Function Table
Dual-In-Line Package
Inputs
A
Outputs
CLEAR
B
Q
Q
L
X
X
H
X
X
X
L
L
L
H
H
X
L
H
H
H
u
L
É
É
É
ß
ß
ß
u
H
H
v
L
e
e
e
H
L
High Logic Level
Low Logic Level
X
Can Be Either Low or High
e
Positive Going Transition
Negative Going Transition
u
e
v
e
É
A Positive Pulse
A Negative Pulse
e
ß
TL/F/6386–1
Order Number DM74LS123M or DM74LS123N
See NS Package Number M16A or N16E
C
1995 National Semiconductor Corporation
TL/F/6386
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
7V
7V
Input Voltage
a
0 C to 70 C
Operating Free Air Temperature Range
Storage Temperature
§
65 C to 150 C
§
b
a
§
§
Recommended Operating Conditions
Symbol
Parameter
Min
4.75
2
Nom
Max
Units
V
V
V
V
Supply Voltage
5
5.25
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
V
IH
0.8
V
IL
b
I
I
0.4
mA
mA
OH
OL
8
t
Pulse Width
(Note 6)
A or B High
A or B Low
Clear Low
40
40
40
5
W
ns
R
C
C
External Timing Resistor
External Timing Capacitance
Wiring Capacitance
260
kX
mF
EXT
No Restriction
EXT
WIRE
50
70
pF
at R Terminal
/C
EXT EXT
T
A
Free Air Operating Temperature
0
C
§
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
(Note 1)
Symbol
Parameter
Conditions
Min
Max
Units
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
OH
CC
OH
2.7
3.4
e
e
Max, V
IL
IH
e
e
e
V
Low Level Output
Voltage
V
V
Min, I
Max
Min
OL
CC
OL
0.35
0.25
0.5
e
Max, V
IH
V
IL
e
e
I
4 mA, V
CC
Min
0.4
0.1
20
OL
@
Input Current Max
Input Voltage
e
e
I
V
Max, V
7V
I
CC
I
mA
e
e
e
e
e
I
I
I
High Level Input Current
Low Level Input Current
V
CC
V
CC
V
CC
Max, V
Max, V
Max
2.7V
0.4V
mA
IH
IL
I
b
0.4
mA
I
Short Circuit
Output Current
OS
b
b
100
20
mA
mA
(Note 2)
e
V
CC
I
Supply Current
Max (Notes 3,4 and 5)
12
20
CC
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
CC
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Quiescent I is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs open, C
A
e
0.02 mF, and
CC
EXT
e
R
EXT
25 kX.
e
e
25 kX.
Note 4: I is measured in the triggered state with 2.4V applied to all clear and B inputs, A inputs grounded, all outputs open, C
CC
0.02 mF, and R
EXT
EXT
Note 5: With all outputs open and 4.5V applied to all data and clear inputs, I
is measured after a momentary ground, then 4.5V is applied to the clock.
CC
e
e
5V.
Note 6: T
25 C and V
§
A
CC
2
e
e
25 C
Switching Characteristics at V
5V and T
§
CC
A
e
R
L
2 kX
e
e
15pF
e
1000 pF, R 10 KX
EXT
From (Input)
To (Output)
C
15pF
C
L
L
Symbol
Parameters
Units
e
e
e
C
EXT
C
EXT
0 pF, R
EXT
5 kX
Min
Max
Min
Max
t
t
t
t
t
t
t
t
Propagation Delay Time
Low to High Level Output
PLH
A to Q
B to Q
33
ns
ns
ns
ns
ns
ns
Propagation Delay Time
Low to High Level Output
PLH
44
45
Propagation Delay Time
High to Low Level Output
PHL
A to Q
Propagation Delay Time
High to Low Level Output
PHL
B to Q
56
Propagation Delay Time
Low to High Level Output
PLH
Clear to Q
Clear to Q
45
Propagation Delay Time
High to Low Level Output
PHL
27
Minimum Width of Pulse
at Output Q
WQ(Min)
W(out)
A or B to Q
A or B to Q
200
ns
Output Pulse Width
4
5
ms
Operating Rules
1. An external resistor (R ) and an external capacitor (C )
ll
fined as follows:
3. For C
1000 pF the output pulse width (T ) is de-
W
X
X
X
are required for proper operation. The value of C may
X
e
KR C
X X
vary from 0 to any necessary value. For small time con-
stants high-grade mica, glass, polypropylene, polycarbon-
ate, or polystyrene material capacitors may be used. For
large time constants use tantalum or special aluminum
capacitors. If the timing capacitors have leakages ap-
proaching 100 nA or if stray capacitance from either ter-
minal to ground is greater than 50 pF the timing equations
may not represent the pulse width the device generates.
T
W
[
]
R is in kX
X
where
[
]
C
is in pF
X
[
]
T
is in ns
W
&
K
0.37
4. The multiplicative factor K is plotted as a function of C
below for design considerations:
X
2. When an electrolytic capacitor is used for C a switching
X
diode is often required for standard TTL one-shots to pre-
vent high inverse leakage current. This switching diode is
not needed for the ’LS123 one-shot and should not be
used. In general the use of the switching diode is not
recommended with retriggerable operation.
Furthermore, if a polarized timing capacitor is used on the
’LS123 the negative terminal of the capacitor should be
connected to the ‘‘C
’’ pin of the device (Figure 1).
EXT
TL/F/6386–2
FIGURE 2
TL/F/6386–8
FIGURE 1
3
Operating Rules (Continued)
k
5. For C
1000 pF see Figure 3 for T vs C family
X
X
W
curves with R as a parameter:
X
TL/F/6386–7
FIGURE 7
9. Under any operating condition C and R must be kept
as close to the one-shot device pins as possible to mini-
mize stray capacitance, to reduce noise pick-up, and to
reduce I-R and Ldi/dt voltage developed along their
X
X
TL/F/6386–3
FIGURE 3
6. To obtain variable pulse widths by remote trimming, the
following circuit is recommended:
connecting paths. If the lead length from C to pins (6)
X
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations. A
non-inductive and low capacitive path is necessary to
ensure complete discharge of C in each cycle of its
X
operation so that the output pulse width will be accurate.
TL/F/6386–4
10. The C
pins of this device are internally connected to
EXT
FIGURE 4
the internal ground. For optimum system performance
they should be hard wired to the system’s return ground
plane.
Note: ‘‘R
’’ should be as close to the device pin as possible.
remote
7. The retriggerable pulse width is calculated as shown be-
low:
11. V and ground wiring should conform to good high-fre-
CC
quency standards and practices so that switching tran-
e
a
e
c
c
a
C t
X PLH
T
T
W
t
K
R
PLH
X
sients on the V and ground return leads do not cause
CC
interaction between one-shots. A 0.01 mF to 0.10 mF
bypass capacitor (disk ceramic or monolithic type) from
The retriggered pulse width is equal to the pulse width
plus a delay time period (Figure 5).
V
to ground is necessary on each device. Further-
CC
more, the bypass capacitor should be located as close
to the V -pin as space permits.
CC
For further detailed device characteristics and output performance
please refer to the NSC one-shot application note AN-372.
TL/F/6386–5
FIGURE 5
8. Output pulse width variation versus V
and tempera-
CC
tures: Figure 6 depicts the relationship between pulse
width variation versus V , and Figure 7 depicts pulse
CC
width variation versus temperatures.
TL/F/6386–6
FIGURE 6
4
Physical Dimensions inches (millimeters)
16-Lead Small Outline Molded Package
Order Number DM74LS123M
NS Package Number M16A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS123N
NS Package Number N16E
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