DM74LS395WM [NSC]
4-Bit Shift Register with TRI-STATE Outputs; 与三态输出4位的移位寄存器
| 型号： | DM74LS395WM |
| 厂家： | 
National Semiconductor |
| 描述： | 4-Bit Shift Register with TRI-STATE Outputs |
| 文件： | 总6页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1992
DM74LS395
4-Bit Shift Register with TRI-STATE Outputs
É
Features
General Description
Y
Shift right or parallel 4-bit register
The LS395 is a 4-bit shift register with TRI-STATE outputs
and can operate in either a synchronous parallel load or a
serial shift-right mode, as determined by the Select input. An
asynchronous active LOW Master Reset (MR) input over-
rides the synchronous operations and clears the register.
An active LOW Output Enable (OE) input controls the TRI-
STATE output buffers, but does not interfere with the other
operations. The fourth stage also has a conventional output
for linking purposes in multi-stage serial operations.
Y
TRI-STATE outputs
Y
Input clamp diodes limit high speed termination effects
Fully CMOS and TTL compatible
Y
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL/F/9833–2
e
e
V
CC
GND
Pin 16
Pin 8
TL/F/9833–1
Order Number DM74LS395WM or DM74LS395N
See NS Package Number M16B or N16E
Mode Select Table
@
@
t
n
Inputs
MR CP
t
Outputs
a
1
n
Operating Mode
S
D
P
S n
O0 O1 O2 O3
Asynchronous Reset
Shift, SET First Stage
L
X
X
L
X
X
L
L
L
L
H
K
H
X
H
O0 O1 02
n n
n
n
Shift, RESET First Stage
Parallel Load
H
H
K
K
L
L
X
L
O0 O1 02
n n
H
X
Pn P0 P1 P2 P3
e
a
1
t , t
n
Time before and after CP HIGH-to-LOW transition
n
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9833
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Note)
Supply Voltage
7V
7V
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Input Voltage
a
0 C to 70 C
Operating Free Air Temperature Range
Storage Temperature Range
§
65 C to 150 C
§
§
b
a
§
Recommended Operating Conditions
Symbol
Parameter
Supply Voltage
Min
4.75
2
Nom
Max
Units
V
V
V
V
5
5.25
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
V
IH
0.8
V
IL
b
I
I
0.4
mA
mA
OH
OL
8
T
A
0
70
C
§
t
s
t
s
(H)
(L)
20
20
ns
ns
S, D or P to CP
S n
t
h
t
h
(H)
(L)
Hold Time HIGH or LOW
S, D or P to CP
5
5
S
n
t
(L)
(L)
CP Pulse Width LOW
MR Pulse Width LOW
18
20
ns
ns
w
w
t
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Typ
(Note 1)
Symbol
Parameter
Conditions
Min
Max
Units
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
Max
V
V
I
CC
I
High Level Output
Voltage
V
V
OH
CC
OH
2.7
e
Max
IL
e
e
e
Max
V
Low Level Output
Voltage
V
V
Min, I
Min
OL
CC
IH
OL
0.35
0.25
0.5
V
e
e
I
4 mA, V
Min
e
7V
0.4
0.1
20
OL
CC
@
Input Current Max
Input Voltage
e
I
V
CC
Max, V
I
I
mA
e
e
e
e
e
e
I
I
I
I
High Level Input Current
Low Level Input Current
Short Circuit Output Current
V
CC
V
CC
V
CC
V
CC
Max, V
Max, V
2.7V
0.4V
mA
mA
mA
IH
I
b
0.4
IL
I
b
b
100
Max (Note 2)
20
OS
CC
e
Supply Current with
Outputs OFF
Max, OE, D , S
e
4.5V
S
GND
29
25
20
mA
mA
mA
mA
e
CP
K, P
n
e
e
4.5V
Supply Current with
Outputs ON
V
Max, D , S
e
CC
OE, CP, P
S
GND
n
e
I
I
TRI-STATE Output Off
Current HIGH
V
V
V
CCH
2.7V
OZH
OZL
CC
OZH
e
e
V
CCH
TRI-STATE Output Off
Current LOW
V
V
CC
b
20
e
0.4V
OZL
e
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
e
25 C.
Note 1: All typicals are at V
5V, T
§
CC
A
2
Switching Characteristics
5.0V, T
e a
e a
25 C
V
CC
§
A
e
e
2 kX, C
L
R
15 pF
Max
L
Symbol
Parameter
Units
Min
f
Maximum Shift Frequency
Propagation Delay
30
MHz
ns
max
t
t
35
25
PLH
CP to O
PHL
n
t
Propagation Delay
MR to O
PHL
35
ns
ns
ns
n
t
t
Output Enable Time
20
20
PZH
PZL
t
t
Output Disable Time
17
23
PHZ
PLZ
Functional Description
The ‘LS395 contains four D-type edge-triggered flip-flops
served. When the S input is LOW, a CP HIGH-LOW tran-
sition transfers data in O0 to O1, O1 to O2, and O2 to O3. A
left-shift is accomplished by connecting the outputs back to
and auxiliary gating to select a D input either from a Parallel
(P ) input or from the preceding stage. When the Select
n
input is HIGH, the P inputs are enabled. A LOW signal in
n
the P inputs, but offset one place to the left, i.e., O3 to P2,
n
the S input enables the serial inputs for shift-right opera-
tions, as indicated in the Truth Table.
O2 to P1, and O1 to P0, with P3 acting as the linking input
from another package.
State changes are initiated by HIGH-to-LOW transitions on
the Clock Pulse (CP) input. Signals on the P , D and S
inputs can change when the Clock is in either state, provid-
ed that the recommended setup and hold times are ob-
When the OE input is HIGH, the output buffers are disabled
and the O0–O3 outputs are in a high impedance condition.
The shifting, parallel loading or resetting operations can still
be accomplished, however.
n
S
Logic Diagram
TL/F/9833–3
3
4
Physical Dimensions inches (millimeters)
16-Lead Wide Small Outline Molded Package (M)
Order Number DM74LS395WM
NS Package Number M16B
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS395N
NS Package Number N16E
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systems which, (a) are intended for surgical implant
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
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to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
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