DM74LS962N/B+ [NSC]
IC,SHIFT REGISTER,LS-TTL,DIP,18PIN,PLASTIC;
| 型号： | DM74LS962N/B+ |
| 厂家： | 
National Semiconductor |
| 描述： | IC,SHIFT REGISTER,LS-TTL,DIP,18PIN,PLASTIC 移位寄存器 |
| 文件： | 总8页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1991
DM74LS962 (DM86LS62)
Dual Rank 8-Bit TRI-STATE Shift Register
É
General Description
Features
Y
Registers are edge-triggered by the positive transition
of the clock
These circuits are TRI-STATE, edge-triggered, 8-bit I/O reg-
isters in parallel with 8-bit serial shift registers which are
capable of operating in any of the following modes: parallel
load from I/O pins to register ‘‘A’’, parallel transfer down
from register ‘‘A’’ to serial shift register ‘‘B’’, parallel transfer
up from shift register ‘‘B’’ to register ‘‘A’’, serial shift of regis-
ter ‘‘B’’, or exchange data between register ‘‘A’’ and shift
register ‘‘B’’. Since the registers are edge-triggered by the
positive transition of the clock, the control lines which deter-
mine the mode or operation are completely independent of
the logic level applied to the clock. Designed for bus-orient-
ed systems, these circuits have their TRI-STATE inputs and
outputs on the same pins.
Y
Y
Y
All inputs are PNP transistors
Input disable dominates over output disable
Output high impedance state does not impede any oth-
er mode of operation
Y
Y
Y
Y
Y
8-bit I/O pins are TRI-STATE buffers
Typical shift frequency is 36 MHz
Typical power dissipation is 305 mW
All control inputs are active when in an ‘‘L’’ logic state
Devices can be cascaded into N-bit word
Connection Diagram
Dual-In-Line Package
Pin Description
DIS ÐOutput disable
O
I ÐSerial input
S
DIS ÐInput disable
I
DIS ÐTransfer up disable
TU
DIS ÐTransfer down disable
TD
DIS ÐShift disable
S
O ÐSerial output
S
CLKÐClock
GNDÐGround
I/O 1 . . . I/O 8Ð8-bit I/O pins
V ÐSupply Voltage
CC
TL/F/6438–1
Top View
Order Number DM74LS962N or DM86LS62N
See NS Package Number N18A
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/6438
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
Supply Voltage
7V
7V
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Input Voltage
Operating Free Air Temperature Range
DM74LS/DM86LS
a
0 C to 70 C
§
65 C to 150 C
§
§
b
a
Storage Temperature Range
§
Lead Temperature (Soldering, 10 seconds)
300 C
§
Recommended Operating Conditions
Symbol
Parameter
Supply Voltage
Min
4.75
2
Typ
Max
Units
V
V
V
V
5
5.25
CC
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Current
Low-Level Output Current
Clock Frequency (Note 5)
High Pulse Width (Note 5)
Low Pulse Width (Note 5)
Data Set-Up Time (Note 5)
Data Hold Time (Note 5)
Free Air Operating Temperature
V
IH
0.8
V
IL
b
I
I
5.2
16
25
mA
mA
MHz
ns
OH
OL
f
0
25
15
10
0
CLOCK
Clock
Pulse
17
7
ns
t
t
ns
SET-UP
HOLD
ns
T
A
0
70
C
§
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions (1)
Min
Typ (2)
Max
Units
e
e
e b
Min, I
I
b
1.5
V
V
Input Clamp Voltage
High-Level Output Voltage
V
18 mA
2 V,
V
I
CC
e
e b
e b
V
V
Min, V
I
I
I
I
2.6 mA
5.2 mA
OH
CC
IH
OH
OH
OL
OL
V
V
e
V
Max
IL
IL
2.4
e
e
e
e
V
OL
Low-Level Output Voltage
V
V
Min, V
IH
2 V,
8 mA
0.25
0.35
0.4
CC
e
V
Max
IL
IL
16 mA
0.5
0.1
20
e
e
5.5V
I
Input Current at Maximum
Input Voltage
V
CC
Max, V
I
I
mA
e
e
e
e
e
e
e
I
I
I
I
I
High-Level Input Current
Low-Level Input Current
Short-Circuit Output Current
Supply Current
V
CC
V
CC
V
CC
V
CC
V
CC
Max, V
Max, V
2.7V
0.4V
mA
mA
mA
mA
mA
mA
IH
I
b
50
IL
I
b
b
100
99
Max (3)
Max (4)
20
OS
CC
OFF
61
e
e
e
TRI-STATE I/O Current
Max, V
IH
2V
V
V
2.4V
0.4V
20
O
b
20
O
Note 1: For conditions shown as min or max, use the appropriate value specified under recommended operating conditions.
e
e
25 C.
Note 2: All typical values are at V
5V, T
§
CC
Note 3: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Note 4: I is measured with serial output open, the clock and shift disable input at 2.4V. All other control inputs and I/O pins grounded.
A
CC
e
e
5V.
Note 5: T
25 C and V
§
A
CC
2
e
e
Switching Characteristics V
5V and T
25 C
§
CC
A
Symbol
Parameter
Conditions
Min
Max
Units
f
Maximum Clock Frequency
25
MHz
MAX
PLH
t
Propagation Delay Time, Low-to-High-Level
from Clock to Any Outputs
7
33
48
ns
ns
t
Propagation Delay Time, High-to-Low Level
from Clock to Any Outputs
PHL
10
e
e
1 kX
C
L
15 pF, R
L
t
t
t
t
t
t
Enable Time from Any Control Inputs
Disable Time from Any Control Inputs
Output Enable Time to High Level
Output Enable to Low Level
5
6
5
4
5
6
30
30
23
18
23
27
ns
ns
ns
ns
ns
ns
ENABLE
DISABLE
ZH
ZL
Output Disable Time from High Level
Output Disable Time from Low Level
HZ
e
e
1 kX
C
L
5 pF, R
L
LZ
Logic Diagram
TL/F/6438–2
3
4
Timing Diagram
TL/F/6438–3
5
AC Test Circuit and Switching Time Waveforms
All diodes are 1N916 or 1N3064.
includes probe and jig capacitance.
C
L
TL/F/6438–4
TL/F/6438–5
s
s
s
6 ns, PRR 1MHz, Z
&
50X.
All input pulses are supplied by generators having t
15 ns, t
r
f
OUT
Cascading Packages
Cascading Packages for N-Bit Word
TL/F/6438–6
6
7
Physical Dimensions inches (millimeters)
18-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS962N or DM86LS62N
NS Package Number N18A
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