DM9316J [NSC]
Synchronous 4-Bit Counters; 同步4位计数器
| 型号： | DM9316J |
| 厂家： | 
National Semiconductor |
| 描述： | Synchronous 4-Bit Counters |
| 文件： | 总10页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1989
9316/DM9316 Synchronous 4-Bit Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. The 9316 is a 4-bit binary counter. The carry output
is decoded by means of a NOR gate, thus preventing spikes
during the normal counting mode of operation. Synchronous
operation is provided by having all flip-flops clocked simulta-
neously so that the outputs change coincident with each
other when so instructed by the count-enables inputs and
internal gating. This mode of operating eliminates the output
counting spikes which are normally associated with asyn-
chronous (ripple clock) counters. A buffered clock input trig-
gers the four flip-flops on the rising (positive-going) edge of
the clock input waveform.
The carry look-ahead circuitry provides for cascading coun-
ters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output. Both count-
enable inputs (P and T) must be high to count, and input T is
fed-forward to enable the ripple carry output. The ripple car-
ry output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the Q output. This high-level overflow ripple carry pulse
A
can be used to enable successive cascaded stages. High-
to-low level transitions at the enable P or T inputs may occur
regardless of the logic level in the clock.
Features
Y
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable
input. Low-to-high transitions at the load input are perfectly
acceptable regardless of the logic levels on the clock or
enable inputs. The clear function is asynchronous and a low
level at the clear input sets of the flip-flop outputs low re-
gardless of the levels of clock, load, or enable inputs.
Internal look-ahead for fast counting
Y
Carry output for n-bit cascading
Y
Synchronous counting
Y
Load control line
Y
Diode-clamped inputs
Y
Typical clock frequency 35 MHz
Y
Pin-for-pin replacements popular 54/74 counters
5416A/7416A (binary)
Y
Alternate Military/Aerospace device (9316) is available.
Contact a National Semiconductor Sales Office/Distrib-
utor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6606–1
Order Number 9316DMQB, 9316FMQB, DM9316J
DM9316W or DM9316N
See NS Package Number J16A, N16E or W16A
C
1995 National Semiconductor Corporation
TL/F/6606
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
5.5V
Operating Free Air Temperature Range
Military
Commercial
b
b
a
55 C to 125 C
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
Military
Nom
5
Commercial
Symbol
Parameter
Units
Min
4.5
2
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 6)
IH
0.8
0.8
V
IL
b
b
I
I
0.8
0.8
16
25
mA
mA
MHz
OH
OL
16
f
t
0
25
0
CLK
W
Pulse Width
(Note 6)
Clock
Clear
25
20
20
20
25
20
0
25
20
20
20
25
20
0
ns
t
Setup Time
(Note 6)
Data
SU
Enable P
Load
ns
ns
Clear
t
Any Hold Time (Notes 1 & 6)
H
b
T
Free Air Operating Temperature
55
125
0
70
C
§
A
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
(Note 2)
Symbol
Parameter
Conditions
Min
Max
Units
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
12 mA
V
V
I
CC
I
High Level Output
Voltage
V
CC
V
IL
Max
Min
OH
OH
2.4
3.4
0.2
e
e
Max, V
IH
e
e
V
OL
Low Level Output
Voltage
V
CC
V
IH
Min, I
OL
Min, V
Max
Max
0.4
V
e
e
IL
@
Input Current Max
Input Voltage
e
e
I
I
V
Max, V
5.5V
I
CC
I
1
mA
e
2.4 V
High Level Input
Current
V
CC
V
I
Max
Clock
Enable T
Other
Clock
Enable T
Other
MIL
80
80
40
IH
e
mA
mA
e
0.4V
b
I
Low Level Input
Current
V
CC
V
I
Max
3.2
3.2
1.6
IL
e
b
b
e
(Note 3)
b
b
b
b
I
I
I
Short Circuit
Output Current
V
CC
Max
20
18
57
57
OS
mA
mA
mA
COM
MIL
e
V
CC
(Note 4)
Supply Current with
Outputs High
Max
59
59
63
63
85
CCH
CCL
COM
MIL
94
91
e
(Note 5)
Supply Current with
Outputs Low
V
CC
Max
COM
101
Note 1: The minimum HOLD time is as specified or as long as the CLOCK input takes to rise from 0.8V to 2V, whichever is longer.
e
e
25 C.
Note 2: All typicals are at V
5V, T
§
Note 3: Not more than one output should be shorted at a time.
CC
A
Note 4: I
Note 5: I
is measured with the LOAD input high, then again with the LOAD input low, with all other inputs high and all outputs open.
is measured with the CLOCK input high, then again with the CLOCK input low, with all other inputs low and all outputs open.
CCH
CCL
e
e
5V.
Note 6: T
25 C and V
§
A
CC
2
e
e
25 C (See Section 1 for Test Waveforms and Output Load)
Switching Characteristics at V
5V and T
§
CC
A
e
e
L
From (Input)
To (Output)
R
400X, C
15 pF
Max
L
Symbol
Parameter
Units
Min
f
t
Maximum Clock Frequency
25
MHz
ns
MAX
Propagation Delay Time
Low to High Level Output
Clock
to RC
PLH
27
24
20
23
21
25
15
16
36
t
t
t
t
t
t
t
t
Propagation Delay Time
High to Low Level Output
Clock
to RC
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay Time
Low to High Level Output
Clock
to Q
Propagation Delay Time
High to Low Level Output
Clock
to Q
Propagation Delay Time
Low to High Level Output
Clock
to Q
Propagation Delay Time
High to Low Level Output
Clock
to Q
Propagation Delay Time
Low to High Level Output
ENT
to RC
Propagation Delay Time
High to Low Level Output
ENT
to RC
Propagation Delay Time
High to Low Level Output
Clear
to Q
3
Logic Diagram
9316
TL/F/6606–2
4
Timing Diagram
9316 Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
TL/F/6606–3
Sequence:
(1) Clear outputs to zero.
(2) Preset to binary twelve.
(3) Count to thirteen, fourteen, fifteen, zero, one, and two.
(4) Inhibit
5
Parameter Measurement Information
Switching Time Waveforms
TL/F/6606–4
s
Note A: The input pulses are supplied by a generator having the following characteristics: PRR 1 MHz, duty cycle 50%, Z
s
s
s
&
50X, t
10 ns, t
f
10 ns.
OUT
r
Vary PRR to measure f
MAX
.
Note B: Outputs Q and carry are tested at t
D
for 9316/8316, where t is the bit time when all outputs are low.
a
16 n
n
e
Note C: V
REF
1.5V.
6
Parameter Measurement Information (Continued)
Switching Time Waveforms
TL/F/6606–5
s
s
s
s
&
Note A: The input pulses are supplied by generators having the following characteristics: PRR
Note B: Enable P and Enable T setup times are measured at t for 8316/9316.
1 MHz, duty cycle
50%, Z
50X, t
10 ns, t
f
10 ns.
OUT
r
a
n
16
e
Note C: V
REF
1.5V.
7
8
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 9316DMQB or DM9316J
NS Package Number J16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM9316N
NS Package Number N16E
9
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 9316FMQB or DM9316W
NS Package Number W16A
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