DP5380N [NSC]
Asynchronous SCSI Interface (ASI); 异步SCSI接口( ASI )型号: | DP5380N |
厂家: | National Semiconductor |
描述: | Asynchronous SCSI Interface (ASI) |
文件: | 总32页 (文件大小:407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
May 1989
DP5380 Asynchronous SCSI Interface (ASI)
General Description
The DP5380 ASI is a CMOS device designed to provide a
low cost, high performance Small Computer Systems Inter-
face. It complies with the ANS X3.131-1986 SCSI standard
as defined by the ANSI X3T9.2 committee. It can act as
both INITIATOR and TARGET, making it suitable for any
application. The ASI supports selection, reselection, arbitra-
tion and all other bus phases. High-current open-drain driv-
ers on chip reduce application chip count by interfacing di-
rect to the SCSI bus. An on-chip oscillator provides all tim-
ing delays.
to a DMA controller using normal or Block Mode. The ASI
can be used in either a polled or interrupt-driven environ-
ment.
Features
SCSI Interface
Y
Supports TARGET and INITIATOR roles
Y
Parity generation with optional checking
Y
Arbitration support
Y
The DP5380 is pin and program compatible with the NMOS
NCR5380 device. NCR5380 or AM5380 applications can
use it with no changes to hardware or software. The
DP5380 is available in a 40-pin DIP or a 44-pin PCC.
Direct control/monitoring of all SCSI signals
Y
High current outputs drive SCSI bus directly
Y
Faster and improved timing
Y
Very low SCSI bus loading
The ASI is intended to be used in a microprocessor based
application, and achieves maximum performance with a
DMA controller. The device is controlled by reading and
mP Interface
Y
Memory or I/O-mapped control transfers
writing several internal registers. A standard non-multi-
plexed address and data bus easily fits any mP environment.
Y
Programmed-I/O or DMA data transfers
Y
Normal or Block-mode DMA
Data transfers can be performed by programmed-I/O, pseu-
do-DMA or via a DMA controller. The ASI easily interfaces
Y
Fast DMA handshake timing
Connection Diagram
Table of Contents
1.0 FUNCTIONAL DESCRIPTION
2.0 PIN DESCRIPTION
3.0 REGISTER DESCRIPTION
4.0 DEVICE OPERATION
5.0 INTERRUPTS
6.0 RESET CONDITIONS
7.0 APPLICATION GUIDE
8.0 ABSOLUTE MAXIMUM RATINGS
9.0 DC ELECTRICAL CHARACTERISTICS
10.0 AC ELECTRICAL CHARACTERISTICS
A1 FLOWCHARTS
A2 REGISTER CHART
TL/F/9756–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
PALÉ is a registered trademark of and used under license from Monolithic Memories, Inc.
C
1995 National Semiconductor Corporation
TL/F/9756
RRD-B30M115/Printed in U. S. A.
1.0 Functional Description
1.1 OVERVIEW
Individual setting/resetting and monitoring of every SCSI
bus signal.
#
#
#
#
#
The ASI is designed to be used as a peripheral device in a
mP-based application and appears as a number of read/
write registers. Write registers are programmed to select de-
sired functions. Status registers provide indication of operat-
ing conditions.
Automatic release of the bus for BSY loss from a TAR-
GET, SCSI RST, and lost arbitration.
Automatic bus arbitrationÐthe mP has only to check for
highest priority.
For best performance a DMA controller can be easily inter-
faced directly to the ASI. The ASI provides request/ac-
knowledge and wait-state signals for the DMA interface.
Selection or Reselection of any bus device. The ASI will
respond to both Selection and Reselection.
Optional automatic monitoring of the BSY signal from a
TARGET with an interrupt after releasing control of the
bus.
The SCSI bus is easily controlled via the ASI registers. Any
bus signal may be asserted or deasserted via a bit in the
appropriate register, and the state of every signal is avail-
able by reading registers. This direct control over SCSI sig-
nals allows the user to implement all or part of the protocol
in firmware. The ASI provides hardware support for much of
the protocol.
Figure 1 shows an ASI in a typical application, a low cost
embedded SCSI disk controller. In this application the 8051
single-chip mP acts as the controller and the dual DMA
channels in the DP8475 allow one for the disk data and the
other for SCSI data. The PAL provides chip selection as
É
The ASI provides the following SCSI support:
well as determining who has control of the bus. The advan-
tage of using a mP with on-board ROM is that there is more
free time on the external bus.
Programmed-I/O transfers for all eight information trans-
fer types, with or without parity.
#
Data transfers via DMA, in either block or non-block
mode. The DMA interface supports most devices.
#
TL/F/9756–2
FIGURE 1. ASI Application
2
1.0 Functional Description (Continued)
1.2 mP INTERFACE
mode transfers use the READY output to control the speed
(insert wait-states). An End Of Process (EOP) input from the
DMA controller signals the ASI to halt DMA transfers. An
interrupt can be generated for DMA completion or an error
(see Section 5.0). All DMA data passes through the SCSI
data input and output registers, automatically selected dur-
ing DMA cycles.
Figure 2 shows a block diagram of the ASI. Key blocks with-
in the ASI are Read/Write registers with associated decode
and control logic, interrupt and DMA logic, SCSI bus arbitra-
tion logic, SCSI drivers/receivers with parity and the SCSI
data input and output registers. The ASI has three interfac-
es, one to SCSI, one to a DMA controller and the third to a
mP. The internal registers control all operations of the ASI.
1.4 SCSI INTERFACE
The mP interface consists of non-multiplexed address and
data busses with associated control signals. Address de-
code logic selects a register for reading or writing. The ad-
dress lines A0–2 select the register for mP accesses while
for DMA accesses the address lines are ignored.
The ASI contains all logic required to interface directly to the
SCSI bus. Direct control and monitoring of all SCSI signals
is provided. The state of each SCSI signal may be deter-
mined by reading a register which continuously reflects the
state of the bus. Each signal may be asserted by writing a
ONE to the appropriate bit.
The register bank consists of twelve registers mapped into
an address space of eight locations. Upon an external chip
reset the registers are cleared (all zeroes).
The ASI includes logic to automatically handle SCSI timing
sequences too fast for mP control. In particular there is
hardware support for DMA transfers, bus arbitration, selec-
tion/reselection, bus phase monitoring, BSY monitoring for
bus disconnection, bus reset and parity generation and
checking.
1.3 DMA INTERFACE
The DMA logic interfaces to single-cycle, block mode, flow-
through or fly-by controllers. Single byte transfers are ac-
complished via the DRQ/DACK handshake signals. Block
TL/F/9756–3
FIGURE 2. ASI Block Diagram
3
1.0 Functional Description (Continued)
The ASI arbitration logic controls arbitration for use of the
SCSI bus. The mP programs the SCSI device ID into the
ASI, then sets the ARBITRATE bit. The INITIATOR COM-
MAND REGISTER (ICR) is read to determine when arbitra-
tion has started and whether it is won or lost.
The ASI incorporates high-current drivers and SCHMITT
trigger receivers for interfacing directly to the SCSI bus. This
feature reduces the chip count of any SCSI application.
1.5 PARITY
The ASI provides for parity protection on the SCSI interface.
The data bus has eight data bits and one parity bit. The
parity may be enabled via a register bit. A parity error can be
programmed to cause an interrupt.
The BSY signal is continously monitored to detect bus dis-
connection and bus free phases. The ASI incorporates an
on-board oscillator to determine Bus Settle, Bus Free and
Arbitration Delays. The oscillator tolerance guarantees all
timing to be within the SCSI specification.
2.0 Pin Descriptions
Symbol
CS
DIP
PCC
Type
Function
21
24
I
Chip Select: an active low enable for read or write operations, accessing the register
selected by A0 . . . 2.
A0 . . . 2
RD
30, 32, 33 33, 36, 37
I
I
I
I
Address 0 . . . 2: these three signals are used with CS, RD, and WR to address a
register for read or write.
24
29
27
32
Read: an active low enable for reading an internal register selected by A0 . . . 2 and
enabled by CS. It also selects the Input Data Register when used with DACK.
WR
Write: an active low enable for writing an internal register selected by A0 . . . 2 and
enabled by CS. It also selects the Output Data Register when used with DACK.
RESET
D0 . . . 7
INT
28
31
Reset: an active low input with a Schmitt trigger. Clears all internal registers. (SCSI
RST unaffected).
1, 40–34
23
2, 44–38
26
I/O Data 0 . . . 7: bidirectional TRI-STATE signals connecting the active high mP data
É
bus to the internal registers.
O
O
I
Interrupt: an active high output to the mP when an error has occurred, an event
requires service or has completed.
DRQ
22
25
DMA Request: an active high output asserted when the data register is ready to read
or written. DRQ occurs only if DMA mode is enabled. The signal is cleared by DACK.
DACK
26
29
DMA Acknowledge: an active low input that resets DRQ and addresses the data
registers for input or output transfers. DACK is used instead of CS by the DMA
controller.
READY
EOP
25
27
28
30
O
I
Ready: an active high output used to control the speed of block mode DMA transfers.
Ready goes active when the chip is ready to send/receive data and remains inactive
after the transfer until the byte is sent or until the DMA mode bit is reset.
End Of Process: an active low signal that terminates a block of DMA transfers. It
should be asserted during the transfer of the last byte.
DB0 . . . 7 9 . . . 2, 10 10 . . . 3, 11 I/O DB0 . . . 7, DBP: SCSI data bus with parity. DB7 is the MSB and is the highest priority
during arbitration. Parity is ODD. Parity is always generated and can be optionally
checked. Parity is not valid during arbitration.
DBP
RST
BSY
16
13
18
15
I/O Reset: SCSI reset, monitored and can be set by ASI.
I/O Busy: indicates the SCSI bus is being used. Can be driven by TARGET or
INITIATOR.
SEL
ACK
ATN
12
14
15
14
16
17
I/O Select: used by the INITIATOR to select a TARGET or by the TARGET to reselect an
INITIATOR.
I/O Acknowledge: driven by the INITIATOR and received by the TARGET as part of the
REQ/ACK handshake.
I/O Attention: driven by the INITIATOR to indicate an attention condition to the
TARGET.
4
2.0 Pin Descriptions (Continued)
Symbol
DIP
PCC
Type
Function
REQ
20
22
I/O
Request: driven by the TARGET and received by the INITIATOR as part of the REQ/
ACK handshake.
I/O
17
18
19
19
20
21
I/O
I/O
I/O
Ð
Input/Output: driven by the TARGET to control the direction of transfers on the
SCSI bus. This signal also distinguishes between selection and reselection.
C/D
MSG
Command/Data: driven by the TARGET to indicate whether command or data bytes
are being transferred.
Message: driven by the TARGET during message phase to identify message bytes
on the bus.
a
VCC, GND: 5V DC is required. Because of very large switching currents good
decoupling and power distribution is mandatory.
VCC
GND
31
11
35
12, 13
2.1 Connection Diagrams
Order Number DP5380N
See NS Package Number N40A
TL/F/9756–4
Order Number DP5380V
See NS Package Number V44A
TL/F/9756–5
5
3.0 Register Description
3.1 GENERAL
INITIATOR COMMAND REGISTER (ICR)
8 Bits HA 1 Read-Write
The DP5380 ASI is a register-based device with eight ad-
dressable locations. Some addresses have dual functions
depending upon whether they are being read from or written
to. Device operation is described in Section 4.
This register is used to control the INITIATOR and some
other SCSI signals, and to monitor the progress of bus arbi-
tration. Most of the SCSI signals may also be asserted in
TARGET mode. Bits 5 to 0 are reset when BSY is lost (see
MR2 description).
Figure 3.2 summarises the register map. Note that for regis-
ters reading or writing SCSI signals the SCSI name is used
for each bit. Although the SCSI bus is active low the regis-
ters invert the SCSI bus. This means an active SCSI signal
is represented by a ONE in a register and an inactive signal
by a ZERO.
Bit 7
Bit 0
RST TEST LA/DIFF ACK BSY SEL ATN DBUS
3.2 REGISTERS
Initiator Command Register
OUTPUT DATA REGISTER (ODR)
Write-Only
DBUS: Assert Data Bus
Bit 0
8 Bits
HA 0
0
1
Disable SCSI data bus driving.
This is a transparent latch used to send data to the SCSI
bus. The register can be written by mP cycles or via DMA.
DMA writes automatically select the ODR at Hex Address 0
(HA 0). This register is also written with the ID bits required
during arbitration and selection/reselection phases. Data is
latched at the end of the write cycle.
Enable contents of Output Data Register onto the SCSI
data bus. SCSI parity is also generated and driven on
DBP.
This bit should be set when transferring data out of the ASI
in either TARGET or INITIATOR mode, for both DMA or
programmed-I/O. In INITIATOR mode the drivers are only
enabled if: Mode Register 2 TARGET MODE bit is 0, and
I/O is false, and C/D, I/O, MSG match the contents of the
Target Command Register (phasematch is true). In TAR-
GET mode only the MR2 bit needs to be set with this bit.
Bit 7
Bit 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Output Data Register
Reading the ICR reflects the state of this bit.
ATN: Assert Attention
Bit 1
CURRENT SCSI DATA (CSD)
HA 0
8 Bits
Read-Only
0
1
Deassert ATN.
This register enables reading of the current SCSI data bus.
If SCSI parity checking is enabled it will be checked at the
beginning of the read cycle. The register is also used for mP
accesses of SCSI data during programmed-I/O or ID check-
ing during arbitration. Parity is not valid during arbitration.
DMA transfers select the IDR (HA 6) instead of the CSD
register.
Assert SCSI ATN signal. The MR2 TARGET MODE bit
must also be false to assert the signal.
Reading the ICR reflects the state of this bit.
SEL: Assert Select
Bit 2
0
1
Deassert SEL.
Assert SCSI SEL signal. Can be used in INITIATOR or
TARGET mode.
Bit 7
Bit 0
Reading the ICR reflects the state of this bit.
BSY: Assert Busy
Bit 3
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
Deassert BSY.
Current SCSI Data
Assert SCSI BSY signal. Can be used in INITIATOR or
TARGET mode.
Reading the ICR reflects the state of this bit.
Hex
Register
Adr
Mnemonic
Bits
R/W
0
0
1
2
3
4
4
5
5
6
6
7
7
Output Data Register
Current SCSI Data
Initator Command Register
Mode Register 2
Target Command Register
Select Enable Register
Current SCSI Bus Status
Bus and Status
Start DMA Send
Start DMA Target Receive
Input Data Register
ODR
CSD
ICR
8
8
8
8
4
8
8
8
0
0
8
0
0
WO
RO
RW
RW
RW
WO
RO
RO
WO
WO
RO
WO
RO
MR2
TCR
SER
CSB
BSR
SDS
SDT
IDR
Start DMA Initiator Receive
Reset Parity/Interrupts
SDI
RPI
FIGURE 3.2. Registers
6
3.0 Register Description (Continued)
ACK: Assert Acknowledge
Bit 4
the Output Data Register should contain the SCSI de-
vice IDÐa single bit set only. The status of the arbitra-
tion process is given in the AIP and LA bits (6, 5) in the
Initiator Command Register.
0
1
Deassert ACK.
Assert SCSI ACK signal. The MR2 TARGET MODE bit
must also be false to assert the signal.
DMA: DMA Mode
Bit 1
Reading the ICR reflects the state of this bit.
DIFF: Differential Enable Bit 5 Write
0
1
Disable DMA mode.
Enable DMA operation. This bit should be set then one
of address 5 to 7 written to start DMA. The TARGET
MODE bit in the ICR and the phase lines in the TCR
should have been set appropriately. The DBUS bit in
the ICR must be set for DMA operations. BSY must be
active in order to set this bit. The phase lines must
match the contents of the TCR during the actual trans-
fers. In DMA mode ASI logic automatically controls the
REQ/ACK handshakes.
0
1
This bit must be reset to 0.
Do not use. Reserved for future use on a differential
pair device.
LA: Lost Arbitration
Bit 5 Read
0
Normally reset to 0 to show arbitration not lost or not
enabled.
1
Will be set when the ASI loses arbitation, i.e. when SEL
is true during arbitration AND the Assert SEL bit of this
register is false.
This bit should be reset by a mP write to stop any DMA
transfer. An EOP signal will not reset this bit. During
DMA, CS and DACK should not be active simultaneous-
ly.
A 1 in this bit means the ASI has arbitrated for the bus,
asserted BSY and its ID on the data bus and another device
has asserted SEL. The ARBITRATE bit in MR2 must be set
to enable arbitration.
This bit will be reset if BSY is lost during DMA mode.
BSY: Monitor Busy
Bit 2
TEST: Test Mode Enable
Bit 6 Write
0
1
Disable BSY monitor.
0
1
Output drivers are enabled.
Output drivers disabled.
Monitor SCSI BSY signal and interrupt when BSY goes
inactive. When this bit goes active the lower 6 bits of
the ICR are reset and all signals removed from the
SCSI bus. This is used to check for valid TARGET con-
nection.
AIP: Arbitration In Progress
Bit 6 Read
0
1
Normally 0 to show no arbitration in progress.
Set when the ASI has detected BUS FREE phase and
asserted BSY and the Output Data Register contents
onto the SCSI data bus. This bit remains set until arbi-
tration is disabled.
EOP: Enable EOP Interrupt
Bit 3
0
1
No interrupt for EOP.
Interrupt after valid EOP condition.
RST: Assert RST
Bit 7
PINT: Enable SCSI Parity Interrupt
Bit 4
0
1
Deassert RST.
0
1
No interrupt on SCSI parity error.
Assert SCSI RST signal. RST is asserted as long as this
bit is 1, or until a mP Reset (RESET).
When SCSI parity is enabled via the PCHK bit, setting
this bit enables an interrupt upon a SCSI parity error.
After this bit is set the INT pin goes active and internal regis-
ters reset (except for the interrupt latch, MR2 TARGET
MODE bit, and this bit. Reading the ICR reflects the state of
this bit.
PCHK: Enable SCSI Parity Checking
Bit 5
0
1
No SCSI parity checking.
Enable checking of SCSI parity during read operations.
This applies to either programmed I/O or DMA mode.
MODE REGISTER 2 (MR2)
HA2
8 Bits
Read-Write
TARG: Target Mode
Bit 6
This register is used to program basic operating conditions
in the ASI. Operation as TARGET or INITIATOR, DMA
mode and type as well as some interrupt controls are set via
this register. This is a Read/Write register and when read
the value reflects the state of each bit.
0
1
Initiator Mode.
Target Mode.
BLK: Block Mode DMA
Bit 7
0
1
Non-block DMA.
When set along with DMA bit (1) enable block mode
DMA transfers. In block mode the READY line is used
to handshake each byte with the DMA controller in-
stead of the DRQ/DACK handshake used in non-block
mode.
Bit 7
Bit 0
BLK TARG PCHK PINT EOP BSY DMA ARB
Mode Register 2
TARGET COMMAND REGISTER (TCR)
4 Bits HA 3 Read-Write
ARB: Arbitrate
Bit 0
This register is used to control TARGET SCSI signals and to
program the desired phase during INITIATOR mode. During
0
1
Disable arbitration.
Enable arbitration. The ASI will wait for a BUS FREE
phase then arbitrate for the bus. Before setting this bit
7
3.0 Register Description (Continued)
DMA transfers the SCSI phase lines (C/D, MSG, I/O) must
match the contents of the TCR for transfers to occur. A
phase mismatch halts DMA transfers and generates an in-
terrupt.
BUS AND STATUS REGISTER (BSR)
8 Bits HA 5 Read-Only
This read-only register is used to monitor SCSI signals not
included in the CSB, and internal status bits. This register is
read after an interrupt to determine the cause of an inter-
rupt. Bit 0 or 1 are set to 1 if the SCSI signal is active.
Bit 7
Bit 0
x
x
x
x
REQ MSG C/D
I/O
Bit 7
Bit 0
Target Command Register
EDMA DRQ SPER INT PHSM BSY ATN ACK
This is a read/write register and the value read reflects the
state of each bit, except bit 4–7 which always read 0.
Bus & Status Register
I/O: Assert I/O
Bit 0
ACK: Acknowledge
Bit 0
0
1
Deassert I/O.
This bit reflects the state of the SCSI ACK Signal.
Assert SCSI I/O signal. The MR2 TARGET MODE bit
must also be active.
ATN: Attention
Bit 1
This bit reflects the state of the SCSI ATN Signal.
C/D: Assert C/D
Bit 1
BSY: Busy Error
Bit 2
0
1
Deassert C/D.
0
1
No Error.
Assert SCSI C/D signal. The MR2 TARGET MODE bit
must also be active.
This SCSI BSY signal has become inactive while the
MR2 BSY (Monitor BSY) bit is set. This will cause an
interrupt, remove all ASI signals from the SCSI bus and
reset the DMA MODE bit in MR2.
MSG: Assert MSG
Bit 2
0
1
Deassert MSG.
PHSM: Phase Match
Bit 3
Assert SCSI MSG signal. The MR2 TARGET MODE bit
must also be active.
0
Phase Match. The SCSI C/D, I/O and MSG phase lines
are continuously compared with the corresponding bits
in the TCR. The result of this comparison is reflected in
this bit. This bit must be 1 (phase matches) for DMA
transfers. A phase mismatch will stop DMA transfers
and cause an interrupt.
REQ: Assert REQ
Bit 3
0
1
Deassert REQ.
Assert SCSI REQ signal. The MR2 TARGET MODE bit
must also be active. This bit is used to handshake SCSI
data via programmed-I/O.
INT: Interrupt Request
Bit 4
SELECT ENABLE REGISTER (SER)
8 Bits HA 4 Write-Only
0
1
No Interrupt.
Interrupt request active. Set when an enabled interrupt
condition occurs. This bit reflects the state of the INT
pin. INT may be reset by performing a Reset Parity/In-
terrupt (RPI) function.
This write-only register is used to program the SCSI device
ID for the ASI to respond to during Selection or Reselection
Phases. Only one bit in the register should be set. When
SEL is true, BSY false and the SER ID bit active an interrupt
will occur.
SPER: SCSI Parity Error
Bit 5
0
1
No SCSI parity error.
This interrupt is reset or can be disabled by writing zero to
this register. Parity will also be checked during Selection or
Reselection if the PCHK bit in MR2 is set.
SCSI parity error occurred. This bit remains set once an
error occurs until the RPI function clears it. The PCHK
bit in MR2 must be set for a parity error to be checked
and registered.
Bit 7
Bit 0
DRQ: DMA Request
Bit 6
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Select Enable Register
0
1
No DMA request.
DMA request active. This bit reflects the state of the
DRQ pin. DRQ is reset by asserting DACK during a
DMA cycle or by resetting the DMA bit in MR2. A Busy
error will reset the MR2 DMA bit and thus will also clear
DRQ. A phase mismatch will not reset DRQ.
CURRENT SCSI BUS STATUS (CSB)
Read-Only
8 Bits
HA 4
This read-only register is used to monitor SCSI control sig-
nals and the SCSI parity bit. The SCSI lines are monitored
during programmed-I/O transfers and after an interrupt in
order to determine the cause. A bit is 1 if the corresponding
SCSI signal is active.
EDMA: End of DMA
Bit 7
0
1
Not end of DMA.
Set when DACK, EOP and either RD or WR are active
simultaneously. Normally occurs when the last byte is
transferred by the DMA. During DMA send operations
the last byte transferred by the DMA may not have
been transferred on SCSI so REQ and ACK should be
monitored to verify when the last SCSI transfer is com-
plete. This bit is reset when the MR2 DMA bit is reset.
Bit 7
Bit 0
RST BSY REQ MSG C/D I/O SEL DBP
Current SCSI Bus Status
8
3.0 Register Description (Continued)
START DMA SEND (SDS)
HA 5
0 Bits
Write-Only
This write-only register is used to start a DMA send opera-
tion. A write of don’t-care data should be the last thing done
by the mP. The MR2 DMA, BLK and TARG bits must have
been programmed previously.
Bit 7
Bit 0
x
x
x
x
x
x
x
x
Start DMA Send
START DMA TARGET RECEIVE (SDT)
0 Bits HA 6 Write-Only
TL/F/9756–6
This write-only register is used to start a DMA Target Re-
ceive operation. Same comments as SDS apply.
FIGURE 4.2. mP Cycles
Each SCSI signal may be asserted by setting a bit in the
TCR or ICR. Setting the bit to 1 asserts the SCSI signal.
INPUT DATA REGISTER (IDR)
HA 6
8 Bits
Read-Only
The following code demonstrates a byte transferred via pro-
grammed-I/O in INITIATOR mode.
This read-only register contains the SCSI data last latched
during a DMA receive. Each byte from SCSI is latched into
this register automatically by the ASI DMA logic. A DMA
read (DACK and RD) automatically selects this register. Pro-
grammed-I/O SCSI data reads should use the CSD (HA8)
À
/*Transfer one byte as Initiator*/
while (NOT (TCR:REQ));
/* wait till TARGET asserts REQ */
data 4 input (CSD);
START DMA INITIATOR RECEIVE (SDI)
Write-Only
0 Bits
HA 7
/* parity is checked if enabled*/
output (ICR, Assert ACK);
while (TCR:REQ);
This write-only register is used to start a DMA INITIATOR
Receive Operation. Same comments as SDS apply.
RESET PARITY/INTERRUPT (RPI)
Read-Only
/* wait till TARGET deasserts REQ */
output (ICR, 0);
0 Bits
HA 7
This read-only register is used to reset the parity and inter-
rupt latches. Reading this register resets the SCSI parity,
Busy Loss and Interrupt Request latches.
/* deassert ACK, ready for next byte */
Ó
4.0 Device Operation
4.1 GENERAL
4.4 ARBITRATION
This sub-section describes the arbitration support provided
by the ASI and how to program it.
This section describes overall operation of the ASI. More
detailed information of data transfers, interrupts and reset
conditions are covered in later sections. The operation de-
scription covers mP accesses, SCSI bus monitoring, arbitra-
tion, selection, reselection, programmed-I/O, DMA inter-
rupts. Programming and timing details are covered.
Since the SCSI arbitration process requires signal sequenc-
ing too fast for mP’s, hardware support is provided by the
ASI. The arbitration process is enabled by bit 0 MR2 (ARB).
Prior to setting this bit the ODR should be programmed with
the device’s SCSI IDÐa single bit.
The ASI will monitor the bus for a BUS FREE phase. The
BSY signal is continuously monitored. If continuously inac-
tive for at least a SCSI Bus Settle Delay (400 ns) and SEL is
inactive, a valid Bus Free Phase exists. After a period of
SCSI Bus Free Delay (800 ns) the ASI asserts BSY and the
ODR onto the SCSI data bus. The mP should poll the ICR to
determine when arbitration has started. The AIP bit in the
ICR is set when the Bus Free Phase is detected and the
EASI is beginning the Bus Free Delay. Following the Bus
Free Delay a 2.2 ms SCSI Arbitration Delay is required be-
fore examining the data bus to resolve the priorities of the
ID bits. This delay must be implemented in firmware. The
ICR Lost Arbitration (LA) bit must be examined to determine
whether arbitration is lost. The LA bit is set if another
For information regarding interfacing to mP’s and DMA con-
trollers refer to Section 7.0.
In the descriptions following program examples are given in
pseudo-C. This processor-independent approach should be
clearest. These are backed up by flow charts in Appendix
A.1.
4.2 mP ACCESSES
The mP accesses the EASI via the CS, RD, WR and address
and data lines in order to read/write the registers. Figure 4.2
shows typical timing. Note the use of non-multiplexed ad-
dress and data lines.
4.3 SCSI BUS MONITORING/DRIVING
The SCSI bus may be monitored or driven at any time. Each
bus signal is buffered and inverted by the ASI and can be
read via the CSB, BSR and CSD registers. An active SCSI
reads a 1 in the status registers.
9
4.0 Device Operation (Continued)
device asserts SEL during arbitration. If the LA bit is 0 the
data bus is read via the CSD register. The data is examined
to resolve ID priorities. If this device is the highest ID assert
complished by monitoring and setting lines individually. Data
is output via the ODR and read in via the CSD register.
The following code shows INITIATOR and TARGET pro-
gramming for two of these cases. See Appendix A.1 for
flowcharts.
a
SEL by setting ICR bit 2 to a 1. After waiting Bus Clear
Bus Settle Delays (1200 ns) the Selection Phase begins.
These 2 delays must be implemented in firmware.
Initiator Command Send
4.5 SELECTION/RESELECTION
À
The ASI can be used to select or reselect a device. The ASI
will also respond to selection or reselection.
MR2 4 monitor BSY
TCR 4 Command Phase /*02h*/
4.5.1 Selecting/Reselecting
À
while (bytes) to do)
Selection requires programming the ODR with the desired
and own device ID’s; the data bus via ICR DBUS (bit 0);
asserting ATN if required via ICR bit 1; asserting SEL via
ICR bit 2; then resetting the MR2 ARB bit.
while (REQ) inactive)
idle; /*CSB bit 5 4 0*/
if (BSR: phase match 44 0)
phase error;
The SER should have been cleared to zero before Selec-
tion/Reselection to ensure the ASI does not respond. If Re-
selection is desired the I/O line should also be asserted
before SEL via TCR bit 0.
À
else
ODR 4 date byte;
ICR 4 Assert ACK;
Resetting the ARB bit causes the ASI to remove BSY and
the ODR from the data bus. Thus the ICR Assert data bus
bit is required to assert the bits for desired and own device
ID’s.
while (REQ active)
idle; /*CSB bit 5 44 1*/
ICR 4 deassert ACK
/* byte transfer complete */
byte count Ð;
BSY is then monitored to determine when the device has
responded to (re)selection. If the device fails to respond an
error handler should sequence the ASI off the bus. If the
device responds the ICR DBUS and SEL bits should be re-
set to remove these signals. If this is a Reselection the ICR
BSY bit (3) should be set before removing the other signals.
Ó
Ó
goto data phase;
The bus is now ready to handle Information Transfer Phas-
es.
Ó
Target Message Receive
4.5.2 (Re)Selection Response
À
The ASI responds to Selection or Reselection when the
SER is non-zero. A (re)selected interrupt is generated when
BSY is false for at least a Bus Settle Delay (400 ns); and
SEL is true AND any non-zero bit in the SER has its corre-
sponding SCSI data bus bit active. A Selection is disabled
by zeroing the SER. If parity is supported it should be valid
during (re)selection so must be checked via the SPE bit (5)
in the BSR. SCSI specification states that (re)selection is
not valid if more than 2 data bits are active. This condition is
checked by reading the CSD.
/* assumed Assert BSY already set in ICR */
MR2 4 TARG MODE OR PARITY CHECK OR
PARITY INTERRUPT;
TCR 4 Message Out phase; /*06h*/
delay (Bus Settle);
TCR 4 Assert REQ;
while (ACK inactive)
idle; /* BSR bit 0 */
When the selection interrupt occurs it is determined by read-
ing the BSR and CSB registers. There is no dedicated
status bit for (re)selection so it must be determined by the
absence of other interrupts, and the active state of the SEL
signal. Reselection occurs when I/O is also active. See
Section 6.0.
e
data
CSD; /* parity is latched */
if (BSR: parity error)
error routine;
À
else
TCR 4 deassert REQ;
while (ACK active)
idle;
4.6 MONITORING BSY
While an INITIATOR is connected to a TARGET the TAR-
GET must maintain an active BSY signal. During DMA oper-
ations the BSY signal is monitored by the ASI and will halt
operations if it goes inactive. To enable BSY to be moni-
tored at other times the MR2 BSY bit (2) should be set. An
interrupt will be generated if BSY goes inactive while MR2
BSY is set.
Ó
/* message done, can change to next
phase */
Ó
4.8 NON-BLOCK DMA TRANSFERS
This interrupt sets bit 2 in the BSR.
Data transfers may be effected by DMA. This method
should be used for optimum performance. Two methods of
DMA are available-block and non-block mode. This section
describes non-block mode transfers.
4.7 COMMAND/MESSAGE/STATUS TRANSFERS
Command message and status bytes are transferred using
programmed-I/O. The SCSI REQ/ACK handshake is ac-
10
4.0 Device Operation (Continued)
The interface to the DMA controller uses the DRQ, DACK,
EOP lines in non-block mode. Each byte is requested (DRQ)
and ack’d (DACK). Representative timing for a DMA read is
shown in Figure 4.8.1.
if(BSR:Busy error OR NOT
(BSR:End of DMA))
error routine;
À
else
/*DMA End*/
MR2 4 04h;
ICR 4 0;
/*reset DMA bit*/
Ó
Ó
Initiator Receive
/*DATA IN PHASE*/
À
Program DMA Controller;
TCR 4 01h;
MR2 4 3Eh;
SDI 4 0;
/*phase*/
TL/F/9756–7
/*Start DMA Init
Rx*/
FIGURE 4.8.1. Non-Block DMA Timing
4.8.1. NON-BLOCK DMA
while (NOT interrupt)
idle;
DMA operation involves programming the ASI with the set-
up parameters, initiating the DMA cycles and checking for
correct operation when the completion interrupt is received.
The DMA controller should be programmed with the data
byte count and the memory start address. Methods of halt-
ing a DMA operation are covered in Section 4.11.
/*no need to wait for last SCSI handshake
done since DMA done implies it is
checked*/
if(BSR:parity error OR BSR: busy error
or NOT (BSR End of DMA)
Setting up the ASI requires enabling or disabling the follow-
ing: Data bus driving, DMA mode enable, BSY monitoring,
EOP interrupt, parity checking, parity interrupt, TARGET
Mode, bus phase.
do error routines;
À
else
/*End of DMA*/
while (CSD:REQ)
Once set up DMA should be initiated by writing to address 5,
6, or 7 as appropriate. The DMA controller should assert
EOP during the transfer of the last byte, although this may
idle; /*wait for REQ inactive
to deassert ACK*/
b
be done by the mP if the DMA transfers (n
1) bytes and
MR2 4 04h;
the mP transfers the last byte. See the application guide for
more details (Section 7.0).
Ó
Ó
Upon completion the mP should check the following as re-
quired: End of DMA, Parity Error, Phase Match, Busy Error.
The end of DMA occurs as a response to EOP. SCSI trans-
fers may still be underway so REQ and ACK must still be
checked to establish when the final byte is finished.
Target Receive
/*DATA OUT PHASE*/
/*phase*/
À
Program DMA Controller;
The code below shows programming of the ASI in each of
the four DMA cases. One of these cases is shown in a flow
diagram in Appendix A.
TCR 4 0;
ICR 4 08h;
MR2 4 7Ah;
SDT 4 0;
/*check parity*/
/*Start DMA Targ Rx*/
Initiator Send
/*DATA OUT PHASE*/
while (not interrupt)
idle;
À
Program DMA Controller;
/*when End of DMA occurs the last byte
has been read and checked*/
TCR 4 00h;
ICR 4 01h;
MR2 4 0Eh;
SDS 4 00;
/*phase*/
/*Assert DBUS*/
if(BSR:parity error OR NOT(BSR: End of DMA)
error routine;
/*Start DMA Send*/
À
else
/*End of DMA*/
while (NOT interrupt)
idle;
while (BSR:ACK)
idle;
while (CSD:REQ)
idle
/*Not True End of DMA, so wait until SCSI
/*wait for last
SCSI byte
bus inactive before changing phase*/
MR2 4 40h;
transfer so phase
is checked*/
change phase as required;
Ó
Ó
11
4.0 Device Operation (Continued)
Target Send
/*DATA IN PHASE*/
4.9 BLOCK MODE DMA TRANSFERS
À
In Block Mode the DMA interface uses the DRQ, DACK,
EOP and READY lines, DRQ is asserted once at the begin-
ning of transfers and deasserted once DACK is received.
DACK should be asserted continuously for the duration of
all the transfer. EOP should be asserted during the last
DMA byte signal when the next DMA byte transfers. The
ASI asserts the READY signal when the next DMA byte
should be transferred.
Program DMA Controller;
TCR 4 01h;
ICR 4 09h;
MR2 4 4Ah;
SDS 4 0;
/*phase*/
/*Start DMA Send*/
while (NOT interrupt)
As for non-block mode the End of DMA interrupt is just
EOP, also in block mode receive the ASI does not return
READY to an active signal after EOP. This means external
logic must gate off READY if the mP is not to be locked up.
For more details see Section 7.0.
idle;
if(NOT(BSR:End of DMA)
error;
À
else
/*DMA end*/
À
The block mode is intended for systems where the over-
head of handing the system busses to and from the mP and
DMA controller is too great. The block mode handshake is
not necessarily faster than non-block (it may be) but the
overall transfer rate is improved once the bus exchange
overhead is removed. Of course the mP is prevented from
executing for the whole DMA operation.
repeat
while (CSB:REQ OR BSR:ACK)
loop count 4 3;
Ó
loop count Ð; /*decrement*/
until (loop count 44 0);
MR2 4 40h;
If a phase mismatch occurs the READY signal is left in the
inactive state. The DMA controller must hand back the bus
to the mP and the inactive READY signal may need to be
gated off.
Change phase as required;
Ó
Ó
When performing DMA as an INITIATOR the EOP signal
does not deassert ACK on the SCSI bus. Firmware must
determine when REQ is inactive after the last SCSI transfer
then reset the MR2 DMA bit to deassert ACK.
Some explanation of the final part of Target Send is re-
quired. In this type of DMA operation it is very difficult to
exactly determine the True End of DMA simply detecting
REQ and ACK simultaneously inactive is not enough.
Programming the ASI in block mode is the same as non-
block mode except bit 7 in MR2 should also be set.
Reference to Figure 4.8.2 will help to understand the follow-
ing text.
4.10 PSEUDO DMA
The system design can utilize ASI DMA logic for non-data
transfers. This removes the need to poll REQ/ACK and pro-
gram the assertion/deassertion of the handshake signal.
The mP can emulate a DMA controller by asserting DACK
and EOP signals. DRQ may be sampled by reading the
BSR. In most cases the chip decode logic can be adapted
to this use for little or no cost. See Section 7.0 for further
details.
4.11 HALTING A DMA OPERATION
TL/F/9756–8
There are three ways to halt a DMA operation apart from a
chip or SCSI reset. These methods are: EOP, phase mis-
match and resetting the DMA MODE bit in MR2.
FIGURE 4.8.2. Target Send DMA
As shown in Figure 4.8.2 ACK going active causes the DRQ
for the next byte and also REQ to go inactive. ACK going
inactive allows REQ to go active for the next byte. If the
INITIATOR is slow removing ACK the mP may sample the
SCSI bus after the EOP interrupt at point A. Here both REQ
and ACK will be inactive, but there is one more byte to
transfer on SCSI. Due to chip timing delays this condition
will not last more than 200 ns. A safe way to determine the
True End of DMA is to sample REQ and ACK and ONLY
when both are inactive in three successive samples will the
mP be at point B in the figure.
4.11.1 End Of Process
EOP is asserted for a minimum period during the last DMA
cycle. The EOP signal generates the End of DMA interrupt.
EOP does not cause the MR2 DMA mode bit to be reset.
4.11.2 DMA Phase Mismatch
If a REQ goes active while there is a phase mismatch the
DMA will be halted and an interrupt generated. The ASI will
stop driving the SCSI bus when the mismatch occurs. A
phase mismatch is when the TCR phase bits do not match
the SCSI bus values.
4.11.3 DMA Mode Bit
If EOP is not used the best method is to reset the MR2 DMA
Mode bit. This bit may be reset at any time, and should be
reset after an End of DMA interrupt or a phase mismatch.
12
Bit 7
Bit 0
4.0 Device Operation (Continued)
Resetting the bit disables all DMA logic and thus should
only be reset at the True End of DMA condition. Additionally
all DMA logic is reset so this bit must be reset then set again
to carry out the next DMA phase.
0
1
x
x
x
x
0
x
RST BSY REQ MSG C/D
CSD
I/O
SEL DBP
5.5 DMA PHASE MISMATCH
5.0 Interrupts
5.1 OVERVIEW
When the SCSI REQ goes active during a DMA operation
the contents of the TCR are compared with the SCSI phase
lines C/D, MSG and I/O. If the two do not match an inter-
rupt is generated. This interrupt will occur as long as the
MR2 DMA bit is set (bit 1), i.e. it cannot be masked. The
mismatch removes the ASI from driving the SCSI data bus.
The interrupt may reset by reading HA 7. Following an inter-
rupt the BSR and CSD should contain the values shown
below.
Before individually describing each interrupt an explanation
of the use of interrupts is required.
5.2 USING INTERRUPTS
Interrupts are controlled by bits in MR2 if control is provided.
Not all interrupts can be disabled under software control.
When an interrupt occurs both the BSR and CSD register
must be read and analysed to determine the source of inter-
rupt. Since status is NOT provided for each interrupt great
care should be exercised when determining the interrupt
source.
Bit 7
Bit 0
x
0
x
1
0
x
x
x
5.3 SCSI PARITY ERROR
EDMA DRQ SPER INT PHSM BSY ATN ACK
BSR
If SCSI parity checking is enabled via MR2 bit 5 an interrupt
can occur as a result of a read from CSD, a selection/
(re)selection, or a DMA receive operation. The parity error
bit (bit 5) in the BSR will be set if checking is enabled. An
interrupt will occur if Enable Parity Interrupt (bit 4) of MR2 is
set. The interrupt is reset by reading HA7. Following an in-
terrupt the BSR and CSD should contain the values shown
below.
Bit 7
Bit 0
0
x
x
x
x
x
0
x
RST BSY REQ MSG C/D
CSD
I/O
SEL DBP
5.6 BUSY LOSS
Bit 7
Bit 0
If bit 2 MR2 is set the SCSI BSY signal is monitored and an
interrupt is generated if BSY is continuously inactive for at
least a BUS SETTLE DELAY (400 ns). This interrupt may be
reset by reading HA 7. Following an interrupt the BSR and
CSD should contain the values shown below, where usually
x
x
1
1
x
x
x
x
EDMA DRQ SPER INT PHSM BSY ATN ACK
BSR
e
CSD
00.
Bit 7
Bit 0
Bit 7
Bit 0
0
1
x
x
x
x
0
x
x
x
x
1
x
1
0
x
RST BSY REQ MSG C/D
CSD
I/O
SEL DBP
EDMA DRQ SPER INT PHSM BSY ATN ACK
BSR
5.4 END OF DMA
If EOP is asserted during a DMA transfer bit 7 of the BSR
will be set and an interrupt generated if bit 3 of MR2 is 1.
EOP is recognized when EOP, DACK and either IOR or IOW
are all simultaneously active for a minimum period. The in-
terrupt may be reset by reading HA 7. Following an interrupt
the BSR and CSD should contain the values shown below.
Bit 7
Bit 0
0
0
x
x
x
x
x
x
RST BSY REQ MSG C/D
CSD
I/O
SEL DBP
5.7 (RE)SELECTION
Bit 7
Bit 0
An interrupt will be generated when: SEL is active, BSY is
inactive, and the device ID is true. The device ID is deter-
mined by the value in the SER. If ANY non-zero bit in the
SER has its corresponding SCSI data bit active during se-
lection the device ID is true. If I/O is active this is a reselec-
tion. The interrupt is disabled by writing all zeros to the SER,
and reset by reading HA 7.
1
x
x
1
x
x
0
x
EDMA DRQ SPER INT PHSM BSY ATN ACK
BSR
13
sets all logic. This action does not create an interrupt or
generate a SCSI reset.
5.0 Interrupts (Continued)
If SCSI parity checking is enabled it will be checked and
should be valid. Following an interrupt the BSR and CSD
should contain the values shown below.
6.3 EXTERNAL SCSI RESET
When a SCSI RST is applied externally the ASI resets all
registers and logic and issues an interrupt. The only register
bits not affected are the Assert RST bit (bit 7) in the ICR and
the TARGET Mode bit (bit 6) in MR2.
Bit 7
Bit 0
0
0
0
1
x
0
x
0
6.4 SCSI RESET ISSUED
When the mP sets the Assert RST bit in the ICR the RST
signal goes active. Since the ASI monitors RST also the
same reset actions as in 6.3 apply. The SCSI RST signal will
remain active as long as bit 7 in the ICR is setÐi.e. until
programmed 0 or a chip RESET occurs.
EDMA DRQ SPER INT PHSM BSY ATN ACK
BSR
Bit 7
Bit 0
0
0
0
0
0
0
1
x
7.0 Application Guide
This section is intended to show the interface between the
mP, ASI and DMA controller (DMAC). Figure 7.1 shows a
general interface when the ASI and DMAC are I/O-mapped
RST BSY REQ MSG C/D
CSD
I/O
SEL DBP
6.0 Reset Conditions
6.1 GENERAL
devices. This configuration will implement a 2 to 2.5M
Bytes/sec SCSI port using 2 cycle compressed timing from
the 5 MHz DMAC.
There are three ways to reset the ASI; mP chip RESET,
SCSI bus reset applied externally, SCSI bus reset issued by
the ASI.
Using a faster DMAC and memory may allow the ASI to
operate at a higher rateÐbut of course any system will be
limited by the available DMA rate from the SCSI device cur-
rently connected to. The interface shown has several fea-
tures that are examined more closely in the following text.
6.2 CHIP RESET
When the RESET signal is asserted for the required dura-
tion the ASI clears ALL internal registers and therefore re-
TL/F/9756–9
FIGURE 7.1. mP/ASI/DMA Interface
14
7.0 Application Guide (Continued)
All the interface signal requirements are satisfied by a PAL
device. The memory interface is not shown, only the rele-
vant DMAC and mP lines are included.
In DMA mode the ASI generates all SCSI handshakes. At all
other times the mP is responsible for REQ/ACK hand-
shakes. Using pseudo-DMA may reduce mP overhead.
The ASI data and address lines connect directly to the mP/
DMAC busses. The DRQ output from the ASI goes direct to
the DMAC. The EOP output from the DMAC goes to the ASI
input, but can also be asserted via the PAL since the DMAC
output is open-drain.
When doing DMA transfers via BLOCK MODE and an error
occurs, the ASI may not deassert the READY signal. For
some DMA controllers this may lock the bus, so the PAL
asserts READY and EOP to the DMA if an interrupt occurs
while READY is false. This completes the current DMA cy-
cle and prevents further DMA for the rest of the block thus
allowing the bus to be handed back to the mP for servicing.
The PAL is programmed so that the mP can access the ASI
in three ways. The three access types are: Register R/W,
DMA R/W, DMA with EOP. Examination of the PAL equa-
tions below shows how the mP may perform any of the three
basic access types simply by accessing the ASI at different
I/O address slots. This enables the mP to simulate a DMAC
(pseudo-DMA). DMA mode may then be used for all infor-
mation transfer phases.
The PAL generates RD and WR strobes while the mP is bus
master, but the DMAC provides the strobes while it is bus
master so the PAL outputs are TRI-STATE.
The PAL details are shown in Figure 7.2 with the signal
definitions and equations following.
TL/F/9756–10
FIGURE 7.2. Interface PAL
15
7.0 Application Guide (Continued)
CSASI 4 IORQ*A7*A6*A5*A4*AEN; ASI reg R/W chip select
ADACK 4 IORQ*A7*A6*A5*A4*RD; mP pseudo-DMA cycle
IORQ*A7*A6*A5*A4*WR
0IORQ*A7*A6*A5*A4*RD; mP pseudo-DMA with EOP
0IORQ*A7*A6*A5*A4*WR
0DDACK;
; DMAC DMA cycle
IF(AEN)AEOP 4 I0RQ*A7*A6*A5*A4*RD; mP pseudo-DMA with EOP
a
0IORQ*A7*A6*A5*A4*WR
IF(DDACK*AREADY*INT)DEOP 4 DDACK*AREADY*INT
;DMA cycle with error
;DMAC register R/W
DEOP* AREADY
CSDMA 4 I0RQ*A7*A6*A5*A4
DREADY 4 AREADY*INT
0AREADY*DDACK
;ASI not READY and not INT
;ASI not READY and DMA cycle active
;mP I/O Read cycle
IF(AEN)I0R 4 I0RQ*RD
IF(AEN)I0W 4 I0RQ*WR
IF(AEN)MEMR 4 I0RQ*RD
IF(AEN)MEMW 4 I0RQ*WR
;mP I/O Write cycle
;mP memory Read cycle
;mP memory Write cycle
FIGURE 7.3. PAL Equations
The mP and DMA signals are defined below
A7–A4
I0RQ
Address bus
Memory I/O cycle select
Read Strobe
RD
WR
Write Strobe
AEN
High DMA address enable asserted by DMAC
DDACK
CSDMA
DREADY
IOR, IOW
DMAC DMA Acknowledge
DMA Chip Select
Ready signal to DMACÐinserts wait-states when low
I/O data strobes to/from DMAC
Memory data strobe from DMAC
MEMR, MEMW
16
8.0 Absolute Maximum Ratings*
b
a
65 C to 150 C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature Range (T
)
§
§
500 mW
STG
Power Dissipation (P )
D
Lead Temperature (T ) (Soldering, 10 sec)
L
260 C
§
2 kV
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
Electro-Static Discharge Rating
b
b
a
a
DC Input Voltage (V
)
0.5V to V
0.5V
0.5V
IN
CC
CC
*Absolute maximum ratings are those values beyond which damage to the
device may occur.
DC Output Voltage (V
)
0.5V to V
OUT
e
e
A
a
0 C to 70 C
g
5.0V 10% unless otherwise specified) T
9.0 DC Electrical Characteristics (V
§
§
CC
Symbol
Parameter
Conditions
Typ
Limit
Units
V
Minimum High Level
Input Voltage
IH
IL
2.0
V
V
V
Maximum Low Level
Input Voltage
0.8
e
e
b
0.1
V
V
Minimum High Level
Output Voltage
I
I
20 mA
V
CC
V
V
OH1
l
l
OUT
4.0 mA
2.4
OH2
OUT
l
e
V
OL1
V
OL2
V
OL3
Maximum Low Level
Output Voltage
SCSI Bus Pins: I
48 mA
0.5
0.1
0.4
V
V
V
l
OL
e
e
l
Other Pins: I
20 mA
l
l
OL
OL
l
l
I
8.0 mA
e
g
I
I
Maximum Input Current
V
V
V
or GND
1
mA
mA
IN
IN
CC
e
Maximum TRI-STATE Output
Leakage Current
V
or GND
OZ
OUT
CC
g
10
e
SCSI Inputs
I
Supply Current
V
V
or GND
e
CC
IN
CC
2.5
4
mA
3V
e
e
Capacitance T
25 C, f
§
1 MHz
Typ
A
Symbol
Parameter (Note 3)
Input Capacitance
Output Capacitance
Units
C
C
5
7
pF
pF
IN
OUT
AC Test Conditions
Input Pulse Level
GND to 3.0V
6 ns
Input Rise and Fall Times
Input/Output Reference Levels
1.3V
TL/F/9756–11
a
0.5V
b
Active High 0.5V
TRI-STATE Reference Levels
(Note 2)
Active Low
e
e
e
e
Note 1: C
50 pF including jig and scope capacitance.
Open for push-pull outputs.
for active low to TRI-STATE.
L
Note 2: S1
S1
S1
V
CC
GND for active high to TRI-STATE.
Note 3: This parameter is not 100% tested.
17
10.0 AC Electrical Characteristics all parameters are preliminary and subject to change without notice
DP5380
Symbol
Parameter
Units
Min
Typ
Max
2200
800
bfas
bfbc
rst
BSY False to Arbitrate Start
BSY False to Bus Clear
RESET Pulse Width
1200
ns
ns
ns
ns
150
stbc
SEL True to Bus Clear
500
10.1 ARBITRATION
TL/F/9756–12
10.2 mP RESET
TL/F/9756–13
18
10.0 AC Electrical Characteristics
all parameters are preliminary and subject to change without notice (Continued)
DP5380
Typ
Symbol
Parameter
Units
Min
10
10
10
0
Max
ahr
ahw
as
Address Hold from End of Read Enable (Note 1)
Address Hold from End of Write Enable (Note 2)
Address Setup to Read or Write Enable (Notes 1, 2)
CS Hold from End of RD or WR
ns
ns
ns
ns
ns
ns
ns
ns
ns
csh
dhr
dhw
dsw
rdv
Data Hold from End of Read Enable (Notes 1, 3)
mP Data Hold Time from End of WR
10
20
50
60
Data Setup to End of Write Enable
Data Valid from Read Enable (Note 1)
Write Enable Width (Note 2)
100
ww
60
Note 1: Read enable (mP) is CS and RD active.
Note 2: Write enable (mP) is CS and WR active.
Note 3: This includes the RC delay inherent in the tests’ method. These signals typically turn off after 25 ns enabling other devices to drive these lines with no
contention.
10.3 mP WRITE
TL/F/9756–14
10.4 mP READ
TL/F/9756–15
19
10.0 AC Electrical Characteristics (Continued)
10.5 DMA WRITE (NON-BLOCK MODE) TARGET SEND
TL/F/9756–16
DP5380
Typ
Symbol
Parameter
Units
Min
Max
120
90
afrt
ACK False to REQ True (DACK or WR False)
ACK True to DRQ True (Target)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
atdt
atrf
ACK True to REQ False (Target)
115
dfdt
dfrt
DACK False to DRQ True
30
90
DACK False to REQ True (ACK False)
DMA Data Hold Time from End of WR
DACK Hold from End of WR
110
dhwr
dkhw
dsrt
dswd
dtdf
eop
wwn
30
0
SCSI Data Setup to REQ True (Target Send) (Note 1)
Data Setup to End of DMA Write Enable
DACK True to DRQ False
40
50
100
Width of EOP Pulse (Note 2)
40
60
DMA Non-Block Mode Write Enable Width (Note 3)
Note 1: EOP, DACK, RD/WR must all be true for recognition of EOP.
Note 2: Write enable (DMA) is DACK and WR active.
20
10.0 AC Electrical Characteristics (Continued)
10.6 DMA WRITE (NON-BLOCK MODE) INITIATOR SEND
TL/F/9756–17
DP5380
Typ
Symbol
Parameter
Units
Min
Max
dfaf
dfdt
dhi
DACK False to ACK False (Non-Block Initiator Send)
DACK False to DRQ True
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
15
30
0
90
SCSI Data Hold from Write EnableÐInitiator
DMA Data Hold Time from End of WR
DACK Hold from End of WR
dhwr
dkhw
dswd
dtdf
eop
rfdt
Data Setup to End of DMA Write Enable
DACK True to DRQ False
50
100
Width of EOP Pulse (Note 1)
40
60
REQ False to DRQ True
100
100
rtat
REQ True to ACK True (Initiator Send)
DMA Non-Block Mode Write Enable Width (Note 2)
wwn
Note 1: EOP, DACK, RD/WR must all be true for recognition of EOP.
Note 2: Write enable (DMA) is DACK and WR active.
21
10.0 AC Electrical Characteristics (Continued)
10.7 DMA READ (NON-BLOCK MODE) TARGET RECEIVE
TL/F/9756–18
DP5380
Typ
Symbol
Parameter
Units
Min
Max
120
90
afrt
ACK False to REQ True (DACK or WR False)
ACK True to DRQ True (Target)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
atdt
atrf
ACK True to REQ False (Target)
115
90
ddv
dfdt
dfrt
DMA Data Valid from Read Enable (Note 1)
DACK False to DRQ True
30
90
DACK False to REQ True (ACK False)
Data Hold from End of Read Enable (Notes 1, 2)
SCSI Data Hold from REQ or ACK True (Receive)
DACK Hold from End of RD
110
60
dhr
10
30
0
dhra
dkhr
dsra
dtdf
eop
SCSI Data Setup Time to REQ or ACK True (Receive)
DACK True to DRQ False
20
100
Width of EOP Pulse (Note 4)
40
Note 1: Read enable (DMA) is DACK and RD active.
Note 2: This includes the RC delay inherent in the tests’ method. These signals typically turn off after 25 ns enabling other devices to drive these lines with no
contention.
Note 3: EOP, DACK, RD/WR must all be true for recognition of EOP.
22
10.0 AC Electrical Characteristics (Continued)
10.8 DMA READ (NON-BLOCK MODE) INITIATOR RECEIVE
TL/F/9756–19
DP5380
Typ
Symbol
Parameter
Units
Min
Max
90
ddv
dfaf
dfdt
dhr
DMA Data Valid from Read Enable (Note 1)
DACK False to ACK False (REQ False, Non-block, In rx)
DACK False to DRQ True
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
30
10
30
0
90
Data Hold from End of Read Enable (Notes 1, 2)
SCSI Data Hold from REQ or ACK True (Receive)
DACK Hold from End of RD
60
dhra
dkhr
dsra
dtdf
eop
rfaf
SCSI Data Setup Time to REQ or ACK True (Receive)
DACK True to DRQ False
20
100
Width of EOP Pulse (Note 3)
40
REQ False to ACK False (DACK False)
REQ True to ACK True (Initiator Receive)
REQ True to DRQ True
100
100
120
rtat
rtdt
Note 1: Read enable (DMA) is DACK and RD active.
Note 2: This includes the RC delay inherent in the tests’ method. These signals typically turn off after 25 ns enabling other devices to drive these lines with no
contention.
Note 3: EOP, DACK, RD/WR must all be true for recognition of EOP.
23
10.0 AC Electrical Characteristics (Continued)
10.9 DMA WRITE (BLOCK MODE) TARGET SEND
TL/F/9756–20
DP5380
Typ
Symbol
Parameter
Units
Min
Max
120
115
110
afrt
ACK False to REQ True (DACK or WR False)
ACK True to REQ False (Target)
ACK True to READY True (Block Mode Target Send)
SCSI Data Hold from ACK True
DMA Data Hold Time from End of WR
SCSI Data Setup to REQ True
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
atrf
atrt
dhat
dhwr
dsrt
dswd
dtdf
eop
rtwf
wfrf
wfrt
wwb
40
30
50
50
Data Setup to End of DMA Write Enable
DACK True to DRQ False
100
Width of EOP Pulse (Note 1)
40
60
READY true to WR False
WR False to READY False
100
120
WR False to REQ True (ACK False)
DMA Write Enable Width (Note 2)
60
Note 1: EOP, DACK, RD, WR must all be true for recognition of EOP.
Note 2: Write enable (DMA) is DACK and WR active.
24
10.0 AC Electrical Characteristics (Continued)
10.10 DMA WRITE (BLOCK MODE) INITIATOR SEND
TL/F/9756–21
DP5380
Typ
Symbol
Parameter
Units
Min
15
Max
dhi
SCSI Data Hold from Write EnableÐInitiator
DMA Data Hold Time from End of WR
Data Setup to End of DMA Write Enable
DACK True to DRQ False
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
dhwr
dswd
dtdf
eop
rfyt
30
50
100
Width of EOP Pulse (Note 2)
40
60
60
REQ False to READY True
80
rtat
REQ True to ACK True
100
rtwf
wfaf
wfrf
wwb
READY True to WR False
WR False to ACK False (REQ False)
WR False to READY False
120
100
DMA Write Enable Width (Note 1)
Note 1: Write enable (DMA) is DACK and WR active.
Note 2: EOP, DACK, RD/WR must all be true for recognition of EOP.
25
10.0 AC Electrical Characteristics (Continued)
10.11 DMA READ (BLOCK MODE) TARGET RECEIVE
TL/F/9756–22
DP5380
Typ
Symbol
Parameter
Units
Min
Max
120
115
110
90
afrt
ACK False to REQ True (DACK or WR False)
ACK True to REQ False
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
atrf
atyt
ddv
dhr
ACK True to READY True
DMA Data Valid from Read Enable (Note 1)
Data Hold from End of Read Enable (Notes 1, 2)
SCSI Data Hold from REQ or ACK True
SCSI Data Setup Time to REQ or ACK True
DACK True to DRQ False
10
30
20
60
dhra
dsra
dtdf
eop
rfrt
100
Width of EOP Pulse (Note 3)
40
RD False to REQ True (ACK False)
RD False to READY False
100
110
35
rfyf
rydv
READY True to Data Valid
Note 1: Read enable (DMA) is DACK and RD active.
Note 2: This includes the RC delay inherent in the tests’ method. These signals typically turn off after 25 ns enabling other devices to drive these lines with no
contention.
Note 3: EOP, DACK, RD/WR must all be active for recognition of EOP.
26
10.0 AC Electrical Characteristics (Continued)
10.12 DMA READ (BLOCK MODE) INITIATOR RECEIVE
TL/F/9756–23
DP5380
Typ
Symbol
Parameter
Units
Min
Max
90
ddv
dhr
DMA Data Valid from Read Enable (Note 1)
Data Hold from End of Read Enable (Notes 1, 2)
SCSI Data Hold from REQ or ACK True
SCSI Data Setup Time to REQ or ACK True
DACK True to DRQ False
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
30
20
60
dhra
dsra
dtdf
eop
rdaf
rfaf
100
Width of EOP Pulse (Note 3)
40
RD False to ACK False (REQ False)
REQ False to ACK False (DACK False)
RD False to READY True False
REQ True to ACK True
125
100
110
100
75
rfyf
rtat2
rtyt
REQ True to READY True
rydv
READY True to Data Valid
35
Note 1: Read enable (DMA) is DACK and RD active.
Note 2: This includes the RC delay inherent in the tests’ method. These signals typically turn off after 25 ns enabling other devices to drive these lines with no
contention.
Note 3: EOP, DACK, RD/WR must all be active for recognition of EOP.
27
Appendix A1
Arbitration and (Re)Selection
TL/F/9756–25
*Only set ATN if Select with ATN is desired.
TL/F/9756–24
28
Appendix A1 (Continued)
Command Transfer (Initiator)
Command Transfer (Target)
TL/F/9756–26
TL/F/9756–27
29
Appendix A2
Register Chart
READ
Current SCSI Data (CSD)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
WRITE
Bit 7
Bit 0
Bit 7
Output Data Register (ODR)
Bit 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Bit 7
Initiator Command Register (ICR)
Bit 0
Bit 7
Initiator Command Register (ICR)
Bit 0
RST
AIP LA ACK BSY SEL ATN DBUS
RST TEST DIFF EN ACK BSY SEL ATN DBUS
Bit 7
Mode Register 2 (MR2)
Bit 0
Bit 7
Mode Register 2 (MR2)
Bit 0
BLK TARG PCHK PINT EOP BSY DMA ARB
BLK TARG PCHK PINT EOP BSY DMA ARB
Bit 7
Target Command Register (TCR)
REQ MSG C/D
Bit 0
Bit 7
Target Command Register (TCR)
REQ MSG C/D
Bit 0
0
0
0
0
I/O
x
x
x
x
I/O
Bit 7
Current SCSI Bus Status (CSB)
I/O
Bit 0
Bit 7
Select Enable Register (SER)
Bit 0
RST BSY REQ MSG C/D
SEL DBP
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Bit 7
Bus and Status Register (BSR)
Bit 0
Bit 7
Start DMA Send (SDS)
Bit 0
EDMA DRQ SPER INT PHSM BSY ATN ACK
x
x
x
x
x
x
x
x
x
x
Bit 7
Input Data Register (IDR)
Bit 0
Bit 7
Start DMA Target Receive (SDT)
Bit 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
x
x
x
x
x
x
Bit 7
Reset Parity/Interrupt (RPI)ÐMode N
Bit 0
Bit 7 Start DMA Initiator Receive (SDI)ÐMode N Bit 0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
e
e
Don’t Care
X
Unknown
X
30
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number DP5380N
NS Package Number N40A
31
Ý
Lit. 102926
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number DP5380V
NS Package Number V44A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
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Hong Kong Ltd.
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a
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Tel: 1(800) 272-9959
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