DP8228J [NSC]
System Controller and Bus Driver; 系统控制器和总线驱动器
| 型号： | DP8228J |
| 厂家： | 
National Semiconductor |
| 描述： | System Controller and Bus Driver |
| 文件： | 总6页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1988
DP8228/DP8228M/DP8238/DP8238M
System Controller and Bus Driver
General Description
The DP8228/DP8228M, DP8238/DP8238M are system
controller/bus drivers contained in a standard, 28-pin dual-
in-line package. The chip, which is fabricated using Schottky
Bipolar technology, generates all the read and write control
signals required to directly interface the memory and input/
output components of the 8080A microcomputer family. The
chip also provides drive and isolation for the bidirectional
data bus of the 8080A microprocessor. Data bus isolation
enables the use of slower memory and input/output compo-
nents in a system, and provides for enhanced system noise
immunity.
when an interrupt is acknowledged by the 8080A. This fea-
ture permits the use of a multilevel priority interrupt structure
in large, interrupt-driven systems.
Features
Y
Single chip system controller and bus driver for 8080A
Microcomputer Systems
Y
Allows use of multibyte CALL instructions for Interrupt
Acknowledge
Y
Provides user-selected single-level interrupt vector
(RST 7)
A user-selected signal-level interrupt vector (RST 7) is pro-
vided by the device for use in the interrupt structure of small
systems that need only one basic vector. No additional
components (such as an interrupt instruction port) are re-
quired to use the single interrupt vector in these systems.
The devices also generate an Interrupt Acknowledge (INTA)
control signal for each byte of a multibyte CALL instruction
Y
Provides isolation of data bus
Y
Supports a wide variety of system bus structures
Y
Reduces system component count
Y
DP8238/DP8238M provides advanced Input/Output
Write and Memory Write control signals for large sys-
tem timing control
8080A Microcomputer Family Block Diagram
TL/F/6825–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/6825
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
)
CC
DP8228M, DP8238M
DP8228, DP8238
4.50
4.75
5.50
5.25
V
V
DC
b
a
65 C to 150 C
§
Storage Temperature
§
DC
b
a
0.5 to 7V
Operating Temperature (T )
A
Supply Voltage, V
CC
b
a
125
DP8228M, DP8238M
DP8228, DP8238
55
C
§
§
b
a
1.5V to 7V
Input Voltage
a
0
70
C
Output Current
100 mA
Note: Maximum ratings indicate limits beyond which perma-
nent damage may occur. Continuous operation at these lim-
its is not intended and should be limited to those conditions
specified under DC electrical characteristics.
Maximum Power Dissipation* at 25 C
§
Cavity Package
2179 mW
2361 mW
Molded Package
*Derate cavity package 14.5 mW/ C above 25 C; derate molded package
§
§
18.9 mW/ C above 25 C.
§
§
s
s
s
s
Electrical Characteristics Min
T
A
Max, Min
V
CC
Max, unless otherwise noted
Typ
Symbol
Parameter
Conditions
e b
C
Min
Max
Units
(Note 1)
e
e
e
e
b
1.0
V
C
Input Clamp Voltage, All Inputs
V
Min, I
Max
5 mA
0.6
V
CC
I
Input Load
Current
STSTB
V
V
V
500
750
mA
mA
F
CC
0.45V for DP8228, DP8238
F
F
D2 and D6
0.40V for DP8228M, DP8238M
D0, D1, D4,
D5 and D7
250
mA
All Other
Inputs
250
20
mA
mA
mA
e
e
V
I
Input Leakage
Current
DB0–DB7
V
CC
Max, V
R
R
CC
All Other
Inputs
100
e
e
V
Input Threshold Voltage,
All Inputs
V
V
5V
TH
CC
0.8
2.0
V
I
Power Supply Current
Max
DP8228, DP8238
185
160
230
230
mA
mA
V
CC
CC
DP8228M, DP8238M
DP8228M, DP8238M
DP8228, DP8238
e
V
V
Output Low
Voltage
D0–D7
V
CC
Min,
0.50
0.45
0.50
0.45
OL
e
I
2 mA
OL
V
e
All Other
Outputs
V
CC
Min,
DP8228M, DP8238M
DP8228, DP8238
V
e
I
10 mA
OL
V
e
Output High
D0–D7
V
C
Min,
DP8228M, DP8238M
DP8228, DP8238
3.3
3.6
3.8
3.8
V
OH
e b
I
10 mA
OL
V
e
e b
1 mA
All Other
Outputs
V
Min, I
CC
OH
2.4
15
3.8
V
e
e
e
e
0V
I
I
Short Circuit Current, All Outputs
V
CC
V
CC
V
CC
5V, V
90
mA
mA
mA
mA
OS
O
e
OFF State Output Current
All Control Outputs
Max, V
V
CC
100
O (OFF)
O
O
e
b
Max, V
0.45V
100
5
I
INTA Current
(See Test Conditions,Figure 3)
INT
e
Note 1: Typical values are for T
25 C and typical supply voltages.
§
A
2
e
e
e
5.0V, T
A
e
25 C, f 1 MHz
§
Capacitance* V
2.5V, V
CC
BIAS
Typ
Symbol
Parameter
Min
Max
Units
(Note 1)
C
C
Input Capacitance
8
7
8
12
15
15
pF
pF
pF
IN
Output Capacitance Control Signals
I/O Capacitance (D or DB)
OUT
I/O
*This parameter is periodically sampled and not 100% tested.
s
s
s
s
T Max
A
Switching Characteristics Min
V
CC
Max, Min
DP8228M,
DP8238M
DP8228,
DP8238
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
t
t
t
t
t
t
Width of Status Strobe
25
8
22
8
ns
ns
ns
ns
ns
PW
SS
SH
DC
RR
RE
Set-Up Time, Status Inputs D0–D7
Hold Time, Status Inuts D0–D7
5
5
Delay from STSTB to Any Control Signal
Delay from DBIN to Control Outputs
(Figure 2)
(Figure 2)
(Figure 1)
20
75
30
20
60
30
Delay from DBIN to Enable/
Disable 8080 Bus
45
45
ns
t
Delay from System Bus to 8080
Bus During Read
(Figure 1)
RD
45
60
30
30
45
30
ns
ns
ns
t
t
Delay from WR to Control Outputs
(Figure 2)
(Figure 2)
5
5
5
5
WR
Delay to Enable System Bus
DB0–DB7 after STSTB
WE
t
t
Delay from 8080 Bus D0–D7 to
(Figure 2)
(Figure 2)
(Figure 2)
WD
E
40
40
ns
ns
System Bus DB0–DB7 During Write
Delay from System Bus Enable to
System Bus DB0–DB7
30
25
30
25
t
t
t
HLDA to Read Status Outputs
ns
ns
ns
HD
DS
DH
Set-Up Time, System Bus Inputs to HLDA
Hold Time, System Bus Inputs to HLDA
10
20
10
20
Test Conditions
TL/F/6825–4
TL/F/6825–3
TL/F/6825–2
FIGURE 1. Test Load
FIGURE 2. Test Load
FIGURE 3. INTA Test Circuit
(For RST 7)
3
Timing Diagram
TL/F/6825–5
e
e
e
0.8V, Logic ‘‘1’’ 3.0V. All other signals measured at 1.5V.
VOLTAGE MEASUREMENT POINTS: D –D (when outputs) Logic ‘‘0’’
7
0.8V, Logic ‘‘0’’
0
*Advanced I/OW MEMW for 8238 only.
Functional Pin Definitions
The following describes the function of all of the DP8228/
DP8228M, DP8238/DP8238M pinouts. Some of these de-
scriptions reference internal circuits.
OUTPUT SIGNALS
Memory Read (MEMR): When low, signals data to be load-
ed in from memory. The MEMR signal is generated by strob-
ing in status word 1, 2, or 4. (Refer to status word chart.)
INPUT SIGNALS
Status Strobe (STSTB): Activated (low) at the start of each
new machine cycle. The STSTB input is used to store a
status word (refer to chart) from the 8080A microprocessor
into the internal status latch of the DP8228, DP8238. The
status word is latched when the STSTB returns to the high
state. The 8080A outputs this status word onto its data bus
during the first state (SYNC interval) of each machine cycle.
Memory Write (MEMW): When low, signals data to be
stored in memory. The MEMW signal is generated for the
DP8238 by strobing in status word 3 or 5. (Refer to status
word chart.) For the DP8228, the MEMW signal is generated
by gating a low-level WR input with the strobed in status
word 3 or 5.
Input/Output Read (I/OR): When low, signals data to be
loaded in from an addressed input/output device. The I/OR
signal is generated by strobing in status word 6.
Data Bus In (DBIN): When high, indicates that the 8080A
data bus is in the input mode. The DBIN signal is used to
gate data from memory or an input/output device onto the
data bus.
Input/Output Write (I/OW): When low, signals data to be
transferred to an addressed input/output device. The I/OW
signal for the DP8238 is generated by strobing in status
word 7. For the DP8238 the I/OW signal is generated by
gating in a low-level WR input with the strobed in status
word 7.
Write (WR): When low, indicates that the data on the
8080A data bus are stable for WRITE memory or output
operation.
Hold Acknowledge (HLDA): When high, indicates that the
8080A data and address buses will go to their high imped-
ance state. When in the data bus read mode, DBIN input in
the high state, a high HLDA input will latch the data bus
information into the driver circuits and gate off the applica-
ble control signal I/OR, MEMR, or INTA (return to the out-
put high state).
Interrupt Acknowledge (INTA): When low, indicates that
an interrupt has been acknowledged by the 8080A micro-
processor. The INTA signal is generated by strobing in
staus word 8 or 10.
Signal Level Interrupt (RST 7): When the INTA output is
tied to 12V through a 1 kX resistor, strobing in status word 8
or 10 will cause the CPU data bus outputs, when active, to
go to the high state.
Bus Enable (BUSEN): Asynchronous DMA input to the in-
ternal gating array. When low, normal operation of the inter-
nal bidirectional bus driver and gating array occurs. When
high, the bus driver and gating array are driven to their high
impedance state.
INPUT/OUTPUT SIGNALS
CPU Data (D –D ) Bus: This bus comprises eight
7
0
TRI-STATE input/output lines that connect to the 8080A
É
microprocessor. The bus provides bidirectional communica-
a
Supply: 5V.
V
CC
Ground: 0V reference.
4
Functional Pin Definitions (Continued)
tion between the CPU, memory, and input/output devices
for instructions and data transfers. A status word (which de-
scribes the current machine cycle) is also outputted on this
data bus during the first microcycle of each machine cycle
System Data (DB –DB ) Bus: This bus comprises eight
7 0
TRI-STATE input/output lines that connect to the memory
and input/output components of the system. The internal
bidirectional bus driver isolates the DB –DB Data Bus from
7
0
e
(SYNC
logic 1).
the D –D Data Bus.
0
7
Status Word Chart
Status
Word
Data Bus Bit
Control
Signal
Machine Cycle
D
7
D
6
D
D
4
D
3
D
D
1
D
0
5
2
Instruction Fetch
Memory Read
1
2
1
0
1
0
0
0
1
0
MEMR
MEMR
MEMW
MEMR
MEMW
I/OR
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
1
0
1
Memory Write
3
Stack Read
4
Stack Write
5
Input Read
6
Output Write
7
I/OW
Interrupt Acknowledge
Halt Acknowledge
Interrupt Acknowledge While Halt
8
INTA
9
(none)
INTA
10
Block and Connection Diagrams
Dual-In-Line Package
TL/F/6825–7
Order Number DP8228J, DP8228MJ,
DP8228N, DP8238J, DP8238MJ or
DP8238N
TL/F/6825–6
See NS Package Number J28A or N28B
5
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number DP8228J, DP8228MJ, DP8238J or DP8238MJ
NS Package Number J28A
Molded Dual-In-Line Package (N)
Order Number DP8228N or DP8238N
NS Package Number N28B
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