DS15BR400 [NSC]
4-Channel LVDS Buffer/Repeater with Pre-Emphasis; 4通道LVDS缓冲器/中继器带预加重
| 型号： | DS15BR400 |
| 厂家： | 
National Semiconductor |
| 描述： | 4-Channel LVDS Buffer/Repeater with Pre-Emphasis |
| 文件： | 总11页 (文件大小：645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2006
DS15BR400/DS15BR401
4-Channel LVDS Buffer/Repeater with Pre-Emphasis
General Description
Features
n DC to 2 Gbps low jitter, high noise immunity, low power
operation
The DS15BR400/DS15BR401 are four channel LVDS buffer/
repeaters capable of datarates of up to 2 Gbps. High speed
data paths and flow-through pinout minimize internal device
jitter and simplify board layout, while pre-emphasis over-
comes ISI jitter effects from lossy backplanes and cables.
The differential inputs interface to LVDS, and Bus LVDS
signals such as those on National’s 10-, 16-, and 18- bit Bus
LVDS SerDes, as well as CML and LVPECL. The differential
inputs and outputs of the DS15BR400 are internally termi-
nated with 100Ω resistors to improve performance and mini-
mize board space. The DS15BR401 does not have input
termination resistors. The repeater function is especially
useful for boosting signals for longer distance transmission
over lossy cables and backplanes.
n 6 dB of pre-emphasis drives lossy backplanes and
cables
n LVDS/CML/LVPECL compatible input, LVDS output
n On-chip 100 Ω output termination, optional 100 Ω input
termination
n 15 kV ESD protection on LVDS inputs and outputs
n Single 3.3V supply
n Industrial -40 to +85˚C temperature range
n Space saving LLP-32 or TQFP-48 packages
n Evaluation Kit Available
Applications
The DS15BR400/DS15BR401 are powered from a single
3.3V supply and consume 578 mW (typ). They operate over
the full -40˚C to +85˚C industrial temperature range and are
available in space saving LLP-32 and TQFP-48 packages.
n Cable extention applications
n Signal repeating and buffering
n Digital routers
Typical Application
20188950
© 2006 National Semiconductor Corporation
DS201889
www.national.com
Block and Connection Diagrams
20188901
20188903
DS15BR400 Block Diagram
DS15BR401 Block Diagram
20188912
20188902
LLP Pinout - Top View
TQFP Pinout - Top View
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2
Pin Descriptions
Pin
Name
TQFP Pin
Number
LLP Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS
IN0+
IN0−
IN1+
IN1−
IN2+
IN2−
IN3+
IN3−
13
14
15
16
19
20
21
22
9
I, LVDS
I, LVDS
I, LVDS
I, LVDS
Channel 0 inverting and non-inverting differential inputs.
Channel 1 inverting and non-inverting differential inputs.
Channel 2 inverting and non-inverting differential inputs.
Channel 3 inverting and non-inverting differential inputs.
10
11
12
13
14
15
16
DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
OUT1+
OUT1−
OUT2+
OUT2−
OUT3+
OUT3-
48
47
46
45
42
41
40
39
32
31
30
29
28
27
26
25
O, LVDS Channel 0 inverting and non-inverting differential outputs. (Note 2)
O, LVDS Channel 1 inverting and non-inverting differential outputs. (Note 2)
O, LVDS Channel 2 inverting and non-inverting differential outputs. (Note 2)
O, LVDS Channel 3 inverting and non-inverting differential outputs. (Note 2)
DIGITAL CONTROL INTERFACE
PWDN
12
8
I, LVTTL A logic low at PWDN activates the hardware power down mode (all
channels).
PEM
2
2
I, LVTTL Pre-emphasis Control Input (affects all Channels)
POWER
VDD
3, 4, 5, 7, 10,
11, 28, 29, 32,
33
3, 4, 6, 7,
20, 21
I, Power VDD = 3.3V, 10%
GND
N/C
8, 9, 17, 18, 23, 5 (Note 1)
I, Ground Ground reference for LVDS and CMOS circuitry. For the LLP package, the
DAP is used as the primary GND connection to the device in addition to the
pin numbers listed. The DAP is the exposed metal contact at the bottom of
the LLP-32 package. It should be connected to the ground plane with at
least 4 vias for optimal AC and thermal performance.
24, 37, 38, 43,
44
1,6, 25, 26, 27,
30, 31, 34, 35,
36
1, 17,
18,19,22,
23, 24
No Connect
Note 1: Note that for the LLP package the GND is connected thru the DAP on the back side of the LLP package in addition to the actual pin numbers listed.
Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and DS15BR401 are optimized
for point-to-point backplane and cable applications.
3
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Absolute Maximum Ratings (Note 3)
LVDS pins to GND only
EIAJ, 0Ω, 200pF
15 kV
250V
Supply Voltage (VDD
)
−0.3V to +4.0V
−0.3V to (VDD+0.3V)
−0.3V to (VDD+0.3V)
−0.3V to (VDD+0.3V)
+40 mA
Charged Device Model
1000V
CMOS Input Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Current
Junction Temperature
Recommended Operating
Conditions
+150˚C
Supply Voltage (VCC
)
3.0V to 3.6V
0V to VCC
0V to VCC
Storage Temperature
−65˚C to +150˚C
260˚C
Input Voltage (VI) (Note 4)
Output Voltage (VO)
Operating Temperature (TA)
Industrial
Lead Temperature (Solder, 4sec)
@
Max Pkg Power Capacity 25˚C
TQFP
LLP
1.64W
4.16W
−40˚C to +85˚C
Note 3: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of products outside of recommended operation conditions.
Thermal Resistance (θJA
TQFP
)
76˚C/W
30˚C/W
LLP
Package Derating above +25˚C
TQFP
<
Note 4: V max 2.4V
ID
13.2mW/˚C
33.3mW/˚C
LLP
ESD Last Passing Voltage
HBM, 1.5kΩ, 100pF
8 kV
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions
LVCMOS DC SPECIFICATIONS (PWDN, PEM)
Typ
(Note
5)
Min
Max Units
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
High Level Input Current
Low Level Input Current
2.0
GND
−10
40
VDD
0.8
V
V
VIN = VDD = 3.6V (PWDN pin)
+10
200
+10
µA
µA
µA
pF
V
IIHR
IIL
VIN = VDD = 3.6V (PEM pin)
VIN = VSS, VDD = 3.6V
−10
CIN1
VCL
LVCMOS Input Capacitance Any Digital Input Pin to VSS
Input Clamp Voltage ICL = −18 mA, VDD = 0V
5.5
−1.5
−0.8
LVDS INPUT DC SPECIFICATIONS (INn )
VTH
Differential Input High
Threshold (Note 6)
Differential Input Low
Threshold (Note 6)
Differential Input Voltage
Common Mode Voltage
Range
VCM = 0.8V to 3.55V,
VDD = 3.6V
0
0
100
mV
VTL
VCM = 0.8V to 3.55V,
VDD = 3.6V
−100
100
mV
mV
V
VID
VCM = 0.8V to 3.55V, VDD = 3.6V
VID = 150 mV, VDD = 3.6V
2400
3.55
VCMR
0.05
CIN2
IIN
LVDS Input Capacitance
Input Current
IN+ or IN− to VSS
3.0
pF
µA
µA
VIN = 3.6V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
−10
−10
+10
+10
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4
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless other specified.
Typ
(Note
5)
Symbol
Parameter
Conditions
Min
Max Units
LVDS OUTPUT DC SPECIFICATIONS (OUTn )
VOD
Differential Output Voltage, RL = 100Ω external resistor between OUT+ and OUT−
250
360
500
35
mV
0% Pre-emphasis (Note 6)
Change in VOD between
Complementary States
Offset Voltage (Note 7)
Change in VOS between
Complementary States
LVDS Output Capacitance
Figure 1
∆VOD
−35
1.05
−35
mV
V
VOS
1.18 1.475
∆VOS
35
mV
COUT
IOS
OUT+ or OUT− to VSS
2.5
pF
mA
mA
Output Short Circuit Current OUT+ or OUT− Short to GND
OUT+ or OUT− Short to VDD
−21
6
−40
40
SUPPLY CURRENT (Static)
ICC
Supply Current
All inputs and outputs enabled and active, terminated
with differential load of 100Ω between OUT+ and OUT-.
PEM = L
175
20
215
200
mA
µA
ICCZ
Supply Current - Power
Down Mode
PWDN = L, PEM = L
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
tLHT
Differential Low to High
Transition Time (Note 12)
Differential High to Low
Transition Time (Note 12)
Differential Low to High
Propagation Delay
Use an alternating 1 and 0 pattern at 200 Mbps, measure
170
170
1.0
250
250
2.0
ps
ps
ns
between 20% and 80% of VOD
.
Figures 2, 4
tHLT
tPLHD
tPHLD
Use an alternating 1 and 0 pattern at 200 Mbps, measure
at 50% VOD between input to output.
Figures 2, 3
Differential High to Low
Propagation Delay
1.0
10
25
2.0
60
75
ns
ps
ps
tSKD1
tSKCC
Pulse Skew (Note 12)
|tPLHD–tPHLD|
Output Channel to Channel Difference in propagation delay (tPLHD or tPHLD) among
Skew (Note 12) all output channels.
Part to Part Skew (Note 12) Common edge, parts at same temp and VCC
tSKP
tJIT
550
1.5
30
ps
ps
ps
ps
Jitter (0% Pre-emphasis)
(Note 8)
RJ - Alternating 1 and 0 at 750 MHz (Note 9)
DJ - K28.5 Pattern, 1.5 Gbps (Note 10)
TJ - PRBS 223-1 Pattern, 1.5 Gbps (Note 11)
Time from PWDN to OUT change from TRI-STATE to
active.
0.5
14
14
31
tON
LVDS Output Enable Time
20
12
µs
ns
Figures 5, 6
tOFF
LVDS Output Disable Time Time from PWDN to OUT change from active to
TRI-STATE.
Figures 5, 6
Note 5: Typical parameters are measured at V
= 3.3V, T = 25˚C. They are for reference purposes, and are not production-tested.
A
DD
Note 6: Differential output voltage V
is defined as ABS(OUT+–OUT−). Differential input voltage V is defined as ABS(IN+–IN−).
ID
OD
Note 7: Output offset voltage V
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
OS
Note 8: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 9: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been subtracted. The input
voltage = V = 500 mV, input common mode voltage = V = 1.2V, 50% duty cycle at 750 MHz, t = t = 50 ps (20% to 80%).
ID
ICM
r
f
Note 10: Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = V = 500 mV, input common mode
ID
voltage = V
= 1.2V, K28.5 pattern at 1.5 Gbps, t = t = 50 ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
ICM
r f
Note 11: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage
23
= V = 500 mV, input common mode voltage = V
= 1.2V, 2 -1 PRBS pattern at 1.5 Gbps, t = t = 50 ps (20% to 80%).
ID
ICM
r f
Note 12: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization.
5
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DC Test Circuits
20188925
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
20188926
FIGURE 2. Differential Driver AC Test Circuit
20188927
FIGURE 3. Propagation Delay Timing Diagram
20188928
FIGURE 4. LVDS Output Transition Times
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6
AC Test Circuits and Timing Diagrams (Continued)
20188929
FIGURE 5. Enable/Disable Time Test Circuit
20188930
FIGURE 6. Enable/Disable Time Diagram
7
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INPUT FAILSAFE BIASING
Application Information
External pull up and pull down resistors may be used to
provide enough of an offset to enable an input failsafe under
open-circuit conditions. This configuration ties the positive
LVDS input pin to VDD thru a pull up resistor and the negative
LVDS input pin is tied to GND by a pull down resistor. The
pull up and pull down resistors should be in the 5kΩ to 15kΩ
range to minimize loading and waveform distortion to the
driver. The common-mode bias point ideally should be set to
approximately 1.2V. Please refer to application note AN-
1194 “Failsafe Biasing of LVDS Interfaces” for more informa-
tion.
INTERNAL TERMINATIONS
The DS15BR400 has integrated termination resistors on
both the input and outputs. The inputs have a 100Ω resistor
across the differential pair, placing the receiver termination
as close as possible to the input stage of the device. The
LVDS outputs also contain an integrated 100Ω ohm termi-
nation resistor, this resistor is used to minimize the output
return loss and does not take the place of the 100 ohm
termination at the inputs to the receiving device. The inte-
grated terminations improve signal integrity and decrease
the external component count resulting in space savings.
The DS15BR401 has 100Ω output terminations only.
DECOUPLING
Each power or ground lead of the DS15BR400 should be
connected to the PCB through a low inductance path. For
best results, one or more vias are used to connect a power
or ground pin to the nearby plane. Ideally, via placement is
immediately adjacent to the pin to avoid adding trace induc-
tance. Placing power plane closer to the top of the board
reduces effective via length and its associated inductance.
OUTPUT CHARACTERISTICS
The output characteristics of the DS15BRB400/DS15BR401
have been optimized for point-to-point backplane and cable
applications, and are not intended for multipoint or multidrop
signaling.
Bypass capacitors should be placed close to VDD pins.
Small physical size capacitors, such as 0402, X7R, surface
mount capacitors should be used to minimize body induc-
tance of capacitors. Each bypass capacitor is connected to
the power and ground plane through vias tangent to the pads
of the capacitor. An X7R surface mount capacitor of size
0402 has about 0.5 nH of body inductance. At frequencies
above 30 MHz or so, X7R capacitors behave as low imped-
ance inductors. To extend the operating frequency range to a
few hundred MHz, an array of different capacitor values like
100 pF, 1 nF, 0.03 µF, and 0.1 µF are commonly used in
parallel. The most effective bypass capacitor can be built
using sandwiched layers of power and ground at a separa-
tion of 2–3 mils. With a 2 mil FR4 dielectric, there is approxi-
mately 500 pF per square inch of PCB.
POWERDOWN MODE
The PWDN input activates a hardware powerdown mode.
When the powerdown mode is active (PWDN=L), all input
and output buffers and internal bias circuitry are powered off.
When exiting powerdown mode, there is a delay associated
with turning on bandgap references and input/output buffer
circuits as indicated in the LVDS Output Switching Charac-
teristics
PRE-EMPHASIS
Pre-emphasis dramatically reduces ISI jitter from long or
lossy transmission media. One pin is used to select the
pre-emphasis level for all outputs, off or on. The pre-
emphasis boost is approximately 6 dB at 750 MHz.
The center dap of the LLP package housing the DS15BR400
should be connected to a ground plane through an array of
vias. The via array reduces the effective inductance to
ground and enhances the thermal performance of the LLP
package.
Pre-emphasis Control Selection Table
PEM
Pre-Emphasis
0
1
Off
On
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8
Typical Performance Characteristics
Data Rate vs. Cable Length (0.25 UI Criteria)
Power Supply Current vs. Data Rate
20188920
20188923
Data presented in this graph was collected using the DS15BR400EVK, a pair
of RJ-45 to SMA adapter boards and various length Belden 1700a cables.
The maximum data rate was determined based on total jitter (0.25 UI criteria)
measured after the cable. The total jitter was a peak to peak value measured
with a histogram including 3000 window hits.
Total Jitter vs. Ambient Temperature
Data Rate vs. Cable Length (0.5 UI Criteria)
20188921
Total Jitter vs. Data Rate
20188924
Data presented in this graph was collected using the DS15BR400EVK, a pair
of RJ-45 to SMA adapter boards and various length Belden 1700a cables.
The maximum data rate was determined based on total jitter (0.5 UI criteria)
measured after the cable. The total jitter was a peak to peak value measured
with a histogram including 3000 window hits.
20188922
9
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Physical Dimensions inches (millimeters) unless otherwise noted
48-TQFP
NS Package Number VBC48a
Order Number DS15BR400TVS, DS15BR401TVS (250 piece Tray)
Order Number DS15BR400TVSX, DS15BR401TVSX (1000 piece Tape and Reel)
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
32-LLP
(See AN-1187 for PCB Design and Assembly Recommendations)
NS Package Number SQA32A
Order Number DS15BR400TSQ, DS15BR401TSQ (1000 piece Tape and Reel)
DS15BR400TSQX, DS15BR401TSQX (4500 piece Tape and Reel)
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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