DS22EV5110SQX [NSC]
DVI, HDMI Extended Reach Equalizer with Retimer and Output De-Emphasis; DVI ， HDMI延长关爱均衡器重定时器和输出去加重
| 型号： | DS22EV5110SQX |
| 厂家： | 
National Semiconductor |
| 描述： | DVI, HDMI Extended Reach Equalizer with Retimer and Output De-Emphasis |
| 文件： | 总18页 (文件大小：1387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
May 11, 2009
DS22EV5110
DVI, HDMI Extended Reach Equalizer with Retimer and
Output De-Emphasis
General Description
Features
The DS22EV5110 is a 6.75 Gbps (3 x 2.25 Gbps) extended
reach equalizer optimized for DVI™and HDMI™ cable exten-
sion applications with a high performance re-clocking feature.
It supports 3 Transition Minimized Differential Signaling
(TMDS®) data channels and a single clock channel over
DVI™ v1.0, and HDMI™ v1.3a data rates up to 2.25 Gbps for
each data channel. The device incorporates a configurable
receive equalizer, a clock and data recovery (CDR) circuit and
a de-emphasis driver on each data channel over DVI v1.0,
and HDMI v1.3a data rates up to 2.25 Gbps for each data
channel. The device incorporates a configurable receive
equalizer with a clock and data recovery (CDR) circuit on each
data channel. The clock channel feeds a high-perfromance
phase locked loop (PLL) that regenerates a low jitter output
clock for data recovery, enabling the extended reach of driv-
ing capability feature for repeater application.
Optimized for HDMI/DVI source and repeater applications
■
■
TMDS compatible inputs with configurable receive
equalization supporting data rates up to 2.25 Gbps
TMDS compatible outputs with configurable transmit de-
emphasis
■
Dedicated CDR on each data channel reduces jitter
transfer
■
Resistor adjustable differential output voltage for AC
coupled Cat5e and Cat6 extension applications
■
2 equalizer settings for a wide range of cable reaches up
to 2.25 Gbps
■
Total Output Jitter of 0.09 UI at 2.25 Gbps
■
■
DVI 1.0 and HDMI v1.3a compatible TMDS source and
sink interface
7 mm x 7 mm 48 pin LLP package
■
■
■
The DS22EV5110 equalizes greater than 25 meters 28 AWG
of HDMI cable, enabling 1080p resolution with 12 bit deep
color depth (2.25 Gbps), to a low jitter version of the clock and
data signal outputs, reducing both deterministic and random
jitter. Obtaining total jitter is 0.09 UI or less over the supported
data rates. This extremely low level of output jitter provides
system designers with extra margin and flexibility when work-
ing with stringent timing budgets. It is ideal for the DVI and
HDMI source and repeater applications.
>8 kV HBM ESD protection
0 °C to +70 °C operating temperature
Applications
Repeater Applications
■
HDMI / DVI Extender
—
Source Applications
■
Video Cards
—
—
—
The transmitter supports configurable transmit de-emphasis
so the output can be optimized for driving additional lengths
of cables or FR4 traces.
Blu-ray DVD Players
Game Consoles
Sink Applications
■
High Definition Displays
Projectors
—
—
Application Diagram
30094953
© 2009 National Semiconductor Corporation
300949
www.national.com
Pin Descriptions
Pin Name Pin Number I/O, Type
High Speed Differential I/O
Description
C_IN−
C_IN+
1
2
I, CML
I, CML
I, CML
I, CML
Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50 Ω terminating
resistor connects C_IN+ to VDD and C_IN- to VDD
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
resistor connects D_IN0+ to VDD and D_IN0- to VDD
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
resistor connects D_IN1+ to VDD and D_IN1- to VDD
Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
resistor connects D_IN2+ to VDD and D_IN2- to VDD
.
D_IN0−
D_IN0+
4
5
.
D_IN1−
D_IN1+
8
9
.
D_IN2−
D_IN2+
11
12
.
C_OUT-
C_OUT+
36
35
O, CML
O, CML
O, CML
O, CML
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
D_OUT0−
D_OUT0+
33
32
D_OUT1–
D_OUT1+
29
28
D_OUT2−
D_OUT2+
26
25
Equalization Control
EQ2
EQ1
EQ0
37
38
39
I, LVCMOS EQ2, EQ1 and EQ0 select the equalizer boost level for EQ channels. Internally pulled LOW
as default. See Table 1.
De-Emphasis Control
DE1
DE0
42
43
I,
DE1, DE0 select the DE-emphasis level for output drivers. Internally pulled low as default.
LVCMOS Refer to Table 2.
Device Control
BYPASS
47
44
45
14
48
I,
Reclocker enable control. Internally pulled low as default.
LVCMOS H = Reclock and De-Emphasis function is bypassed.
L = Normal operation.
EN
I, LVCMOS Enable Output Drivers. Internally pulled HIGH as default.
H = normal operation (enabled).
L = standby mode.
SD
O, LVCMOS Signal Detect Output pin.
H = signal detected on all channels.
L = no signal detected on one or more channels.
LOCK
VOD_CRL
O, LVCMOS Lock Indicator Output pin.
H = PLL is locked.
L = PLL is not locked.
I,
VOD control pin. Refer to Table 3. See Functional Description.
External resistance = 24 kΩ to GND, Output DC Coupled Application.
External resistance = 12 kΩ to GND, Output AC Coupled Application.
Analog
LFp
LFn
40
41
I,
Loop filter capacitor pins.
See Functional Description.
Analog
Power
VDD
3, 6, 7,
10, 13,
15, 46
Power
VDD = 3.3 V ±5%. VDD pins should be tied to the VDD plane through a low inductance path.
A 0.1 µF bypass capacitor should be connected between each VDD pin to the GND planes.
See Power Supply Bypassing for additional details.
GND
22, 24,
27, 30,
31, 34
GND
GND
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Exposed
DAP
DAP
Ground reference. The exposed pad at the center of the package must be connected to the
ground plane.
www.national.com
2
Pin Name Pin Number I/O, Type
Other
Description
Reserved. Do not connect. Leave open.
Reserv
16, 17,
18, 19,
20,21,
23
Note: I = Input, O = Output, IO =Input/Output,
Connection Diagram
30094952
TOP VIEW — Not to Scale
Ordering Information
NSID
Package
Tape & Reel QTY
Package Number
SQA48A
DS22EV5110SQE
DS22EV5110SQ
DS22EV5110SQX
48 Lead LLP
48 Lead LLP
48 Lead LLP
250
1000
2,500
SQA48A
SQA48A
3
www.national.com
ESD Rating
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
>8 kV
HBM, 1.5 kΩ, 100 pF
Thermal Resistance
ꢀθJA, No Airflow
33°C/W
Supply Voltage (VDD
)
-0.5V to 4.0 V
-0.5V to (VDD+ 0.5) V
-0.5V to (VDD+ 0.5) V
-0.5V to (VDD+ 0.5) V
+125°C
Recommended Operating
LVCMOS Input Voltage
LVCMOS Output Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
Lead Temp. (Soldering, 5 sec.)
Conditions (Notes 3, 4)
Min
Typ
Max
Units
V
Supply Voltage
(VDD to GND)
3.135
3.3 3.465
-65°C to +150°C
+260°C
Supply Noise Tolerance
(100 Hz to 50 MHz)
100
mVp-p
°C
Ambient Temperature
0
25
+70
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. All parameters are guaranteed by test,
statistical analysis, or design unless otherwise specified. (Note 3)
Symbol
Power
Parameter
Condition
Min
Typ
Max
Unit
EN = H, Device Enabled
PRBS15 pattern, fCLK=225
MHz
1000
750
1150
900
mW
RT= 50Ω to AVCC, Figure 2
Power Supply
Consumption
P
EN = L, Standby Mode
PRBS15 pattern, fCLK=225
MHz
mW
RT= 50Ω to AVCC, Figure 2
LVCMOS / LVTTL DC Specifications
High level input
voltage
VDD
0.8
VIH
2
V
V
V
V
Low level input
voltage
VIL
GND
2.4
High level output
voltage
VOH
VOL
IOH = -3 mA
Low level output
voltage
IOL = 3 mA
0.4
60
VIN = VDD, EQ2, EQ1, EQ0,
DE1, DE0, BYPASS pins
(pull down)
mA
mA
μA
IIH
IIL
Input HighCurrent
Input Low Current
VIN = VDD, EN pin (pull up)
-15
-20
VIN = 0 V, EQ2, EQ1, EQ0,
DE1, DE0, BYPASS pins
(pull down)
15
VIN = 0 V, EN pin (pull up)
μA
Signal Detect
SDH
Default Input signal level to
Signal Detect High assert SD pin
Default Input signal level to
Signal Detect Low deassert SD
80
20
mVp-p
mVp-p
SDL
www.national.com
4
Symbol
Parameter
Condition
Min
Typ
Max
Unit
CML Inputs
Input Voltage
Swing (Launch
Amplitude)
Measured differentially at
TPA, Figure 1, note 4
VTX
800
1000
1560
mVp-p
DC-Coupled requirement
Measured at TPB,
VINmin=800mV,
Input Common-
Mode Voltage
VDD-0.3
VDD-0.2
VICMDC
V
VINmax=1200mV, Figure 1
Measured differentially at
TPB, Figure 1
2.25 Gbps, Clock Pattern
Input Voltage
Sensitivity
VIN
150
40
1560
60
mVp-p
IN+ to VDD and IN- to VDD
RIN
Input resistance
50
10
Ohms
dB
Differential output
return loss
RLI
100 MHz — 1125 MHz
CML Outputs
Measured DC outputs at
TPC, RT = 50Ω when DUT
VDD is off with OUT+ and
OUT- terminated by RT=
50Ω to AVCC, Figure 2
Standby Output
Voltage
AVCC- 10
AVCC+ 10
VOFF
mV
External resistor = 24 kΩ at
VOD_CRL pin.Measured
differentially with OUT+ and
OUT- terminated by
RT=50Ω to AVCC,Figures 2,
3
Differential Output
voltage swing
VO
800
1200
mVp-p
Output common- Measured single-ended,
AVCC- 0.35
AVCC- 0.2
VOCM
tR, tF
V
mode Voltage
> 1.65 Gbps, Figure 2
20% to 80% of differential
output voltage, measured
within 1” from output pins,
Figure 3
Transition time
85
2
ps
Inter Pair Data
Channel-to-
Difference in 50% crossing
between channels
tCCSK
tPPSK
3
ps
ps
Channel Skew (all 2.25 Gbps, Clock Pattern
3 data channels) (Note 4)
Difference in 50% crossing
Inter Pair Data
between channels of any two
Channels Part-
50
devices
2.25 Gbps, Clock Pattern
toPart Skew
Data Channels
Latency
2.25 Gbps, Clock Pattern,
Figure 4
tDD
tCD
400
600
ps
ps
Clock Channel
Latency
2.25 Gbps, Clock Pattern,
Figure 4
LVCMOS Outputs
tSL
SD to LOCK time Figure 4
4
ms
Bit Rate
Clock Path
(Note 4)
fCLK
bR
Clock Frequency
Bit Rate
25
250
MHz
Data Paths
(Note 4)
0.25
2.25
Gbps
5
www.national.com
Symbol
Data Channel Random Jitter
RJ Random Jitter
Parameter
Condition
Min
Typ
Max
Unit
(Notes 4, 5, 6)
3
psrms
Data Channel CDR Jitter Generation
Data Paths, measured at
TPC PRBS7, EQ [2:0] = 000
Figure 1, (Notes 4, 5, 6)
Total Output Jitter
0.25 Gbps
TROJ1
TROJ2
TROJ3
0.03
0.08
0.09
0.05
0.14
0.16
UIp-p
UIp-p
UIp-p
Data Paths, measured at
TPC PRBS7, EQ [2:0] = 000
Figure 1, (Notes 4, 5, 6)
Total Output Jitter
1.65 Gbps
Data Paths, measured at
TPC PRBS7, EQ [2:0] = 000
Figure 1, (Notes 4, 5, 6)
Total Output Jitter
2.25 Gbps
0.25 Gbps data rate
1.65 Gbps data rate
2.25 Gbps data rate
0.25
1.65
2.25
MHz
MHz
MHz
CDR Loop
Bandwidth
BWLOOP
Clock Channel PLL Jitter Generation
Clock Path, measured at
Total Output Jitter TPC
25 MHz Figure 1
TROJ4
TROJ5
TROJ6
0.03
0.07
0.08
0.045
0.13
UIp-p
UIp-p
UIp-p
(Notes 4, 5, 6)
Clock Path, measured at
Total Output Jitter TPC
165 MHz Figure 1
(Notes 4, 5, 6)
Clock Path, measured at
Total Output Jitter TPC
225 MHz Figure 1
(Notes 4, 5, 6)
0.135
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Allowed supply noise (mVp-p sine wave) at typical condition.
Note 3: Typical parameters are measured at VDD = 3.3 V, TA = 25 °C. They are for reference purposes, and are not production-tested.
Note 4: Parameter is guaranteed by statistical analysis and/or design.
Note 5: Deterministic jitter is measured at the differential outputs (TPC of Figure 1), minus the deterministic jitter before the test channel (TPA of Figure 1). Random
jitter is removed through the use of averaging or similar means.
Note 6: Total Jitter is defined as peak-to-peak deterministic jitter from + 12 times random jitter (ps).
Note 7: Random jitter contributed by the equalizer is defined as sq rt (JOUT2 − JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see TPC of Figure
1; JIN is the random jitter at the input of the equalizer in ps-rms, see TPA of Figure 1.
www.national.com
6
Setup and Timing Diagrams
30094910
FIGURE 1. Test Setup Diagram
30094912
FIGURE 2. CML Output Swings at A/B (VOD_CRL = 24 kΩ
7
www.national.com
30094911
FIGURE 3. CML Output Transition Times
30094913
FIGURE 4. CML Latency Delay Time
30094914
FIGURE 5. SD – LOCK Delay Time
www.national.com
8
channels and a clock channel. Each data channel consists of
a TMDS compatible receiver with a power efficient equalizer,
a dedicated clock-data recovery (CDR) unit, and a TMDS
compatible transmitter.
Functional Description
The DS22EV5110 DVI, HDMI Extended Reach Equalizer with
Retimer and Output De-Emphasis consists of three data
30094915
FIGURE 6. Block Diagram
PHASE-LOCKED-LOCKED LOOP (PLL)
pins (EQ [2:0]). The range of boost settings provided enables
the DS22EV5110 to address a wide range of transmission line
path loss scenarios, enabling support for a variety of data
rates and formats. See Applications Information for recom-
mended EQ settings.
The clock channel has a high-performance PLL that creates
a low jitter sampling clock for the clock and data recovery units
in the data channels. An external loop filter, composed of 2.2
nF (+ 5% tolerance) capacitor and a 3.3 kΩ (+ 5% tolerance)
resistor in series, are required between the LFp and the LFn
pins.
OUTPUT DE-EMPHASIS
De-emphasis is the conditioning function for use in compen-
sating against backplane and cable transmission loss. The
DS22EV5110 provides four steps of de-emphasis ranging
from 0, 3, 6 and 9 dB, user-selectable dependent on the loss
profile of output channels. Table 2. shows the De-emphasis
control with default VO = 1000 mVp-p, and Figure 7. shows a
driver de-emphasis waveform.
CLOCK-DATA RECOVERY UNIT (CDR)
Each TMDS data channel has a CDR that operates indepen-
dently from other TMDS data channels. Each CDR aligns the
sampling clock edges by digitally interpolating the clock from
PLL of the TMDS clock channel. The device is designed to
connect to DVI/HDMI compatible transmitter and receiver at
any data rate between 250 Mbps to 2.25 Gbps. The loop
bandwidth of the CDR is approximately baud_rate/1000, i.e.
2.25 MHz for 2.25 Gbps data.
OUTPUT VO CONTROL
Output differential voltage (VO) is controlled through
VOD_CRL pin ties an external resistor to the ground as shown
in Table 3. Users should restrict the external resistor values
used to be 12 kΩ to 24 kΩ. +5% tolerance is recommended.
INPUT EQUALIZATION
The input data channel equalizers support eight pro-
grammable levels of equalization boost Table 1 by the EQ
9
www.national.com
TABLE 1. Equalization Control
INPUTS
RESULT
EQ2
0
EQ1
0
EQ0
0
Equalization in dB (1.125 GHz)
0 (default)
0
0
1
12
18
21
24
26
28
30
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TABLE 2. De-Emphasis Control
INPUTS
RESULT
VO De-Emphasis level in mVp-
p
DE1
DE0
VO De-Emphasis in dB
(VODE w/VOD_CRL = 24 kΩ
0
0
1
1
0
1
0
1
1000 (default)
0 (default)
710
500
355
-3
-6
-9
TABLE 3. VO Control
External Resistor Value
(VOD_CRL pin)
Applications
VO Level (mVp-p)
DC Coupled
AC Coupled
1000
1000
24 kΩ
12 kΩ
30094916
FIGURE 7. Output De-Emphasis Differential Waveform (showing all de-emphasis steps)
www.national.com
10
RETIMING AND DE-EMPHASIS BYPASS
SIGNAL DETECT
The retiming and De-emphasis BYPASS pin provides the
flexibility to configure the device to an equalizer only mode.
The device is in normal operation, when holding a LOW state
on the BYPASS pin. The retiming and De-emphasis features
are disabled, when a HIGH state is applied.
The DS22EV5110 features a signal detect circuit on all chan-
nels. The status of the input signals can be determined by the
state of the SD pin. A logic HIGH indicates the presence of
signals that have exceeded a specified maximum threshold
value (called SD_ON) on all channels. A logic LOW means
that the signals have fallen below a minimum threshold value
(called SD_OFF) on one or more channels.
DEVICE STATE AND ENABLE CONTROL
The DS22EV5110 has an Enable feature which provides the
ability to control device power consumption. This feature can
be controlled via the Enable Pin (EN Pin). If Enable is acti-
vated, the data channels and clock channel are placed in the
ACTIVE state and all device blocks function as described.
The DS22EV5110 can also be placed in STANDBY mode to
save power. In this mode, the output drivers of the device are
disabled. The CML outputs are in the HIGH (AVCC) state. All
LVCMOS outputs are in the HiZ state.
AUTOMATIC ENABLE FEATURE
During normal operation (i.e. BYPASS pin is LOW), the
DS22EV5110 can be configured to automatically enter
STANDBY mode, if the PLL of the DS22EV5110 is not locked.
The STANDBY mode can be implemented by connecting the
LOCK DETECT (LOCK) pin to the external (LVCMOS) En-
able (EN) pin. If the LOCK pin is connected to the EN pin, a
logic HIGH on the LOCK pin will enable the device; thus the
DS22EV5110 will automatically enter the ACTIVE state. If the
PLL is unlocked, then the LOCK pin will be asserted LOW,
causing the aforementioned blocks to be placed in the
STANDBY state.
LOCK DETECT
When the PLL of the DS22EV5110 is locked, and the gener-
ated reference phases are successfully interpolated by the
CDR, this status is indicated by a logic HIGH on the LOCK
pin. The LOCK pin may be connected to the Enable (EN) pin
input to disable the data channels and clock channel when no
data signal is being received.
11
www.national.com
vice, the output de-emphasis setting should be configured
based on the driving cable length. When used as the sink de-
vice, the levels of the equalization boost of the input data
channels should be optimized based on the receiving cable
length. The DS22EV5110 can also be used as a repeater in
an external extender box with the equalization and de-em-
phasis level settings optimized to provide the maximum cable
reach.
Application Information
The DS22EV5110 is a DVI/HDMI video signal reconditioning
device. The device conforms to DVI v1.0 and HDMI v1.3a
standards supporting up to 6.75 Gbps total throughput TMDS
data for 1080p with 36 bit deep color depth.
TYPICAL APPLICATION
The DS22EV5110 is used as a DVI/HDMI source device, sink
device, or a repeater device, see Figure 8. As the source de-
30094953
FIGURE 8. Typical Application Diagram
DC AND AC COUPLED APPLICATIONS
ground potential difference, or to use one CAT5/6 cable be-
tween two chassis. To optimize the DS22EV5110 perfor-
mance, the external resistance of 12 kΩ at the VOD_CRL pin
should be used on the Source DS22EV5110, and a pair of 50
Ω pull-up resistors should be placed close to the outputs of
the Source DS22EV5110, in order to DC bias the output driv-
er. Meanwhile, 622Ω pull-down resistors should be placed at
the inputs of the Sink DS22EV5110 device, in order to set the
input common mode to a 3.05 V. Note AC coupled configu-
ration is not compliant to the HDMI specification of Source
requirement (See Figure 10).
The DS22EV5110 is designed to support TMDS differential
pairs with DC coupled transmission lines. It contains integrat-
ed termination resistors (50Ω), pulled up to VDD at the input
stage, and open collector outputs for DVI / HDMI signaling.
Figure 9 shows the DC coupled connection between the HD-
MI Source (ie. DS22EV5110) and HDMI Sink (ie.
DS22EV5110) devices. In the DC coupled application, the
external resistance of 24 kΩ at VOD_CRL pin is used at the
Source to ensure the VO level of 1000 mVp-p. The AC cou-
pled method connecting between the Source and the Sink
devices may be preferred to eliminate the impact of the
30094920
FIGURE 9. DC Coupled Application
www.national.com
12
30094921
FIGURE 10. AC Coupled Application
24 AWG UTP (LOW SKEW UNSHIELDED TWIST PAIRS)
CABLES
CABLE SELECTION AND INTER-PAIR SKEW
DVI v1.0 and HDMI v1.3a specify Inter-Pair Skew require-
ments for the system. The DS22EV5110 intends to extend the
longer cable reach with STP (DVI / HDMI) cable, or UTP
(Cat5 / Cat5e / Cat6) cable, and it does not have a de-skew
function to compensate any cable Inter-Pair Skews. Long ca-
ble with Inter-Pair Skew exceeding the DVI / HDMI standard
limit tolerance could cause system distortion. Therefore, Na-
tional suggests the consideration of Inter-Pair Skew budget
during the system design, and recommends Low-Skew Video
grade cables for cable extending applications.
The DS22EV5110 can be used to extend the length of low
skew grade UTP cables, such as Cat5e and Cat6 to distances
greater than 30 meters at 1.65 Gbps with < 0.20 UI of jitter.
Note that for non-standard DVI/HDMI cables, the user must
ensure the inter pair skew requirements are met. Table 5
shows the recommended EQ control settings for various data
rates and cable lengths for UTP configurations.
TABLE 5. EQ Control Setting for UTP Cable
Format (Data Rate)
0 ~ 10m
> 10m
28 AWG STP (SHIELDED TWIST PAIRS) DVI / HDMI
CABLES RECOMMENDED EQ SETTINGS
1080P 36-bit (2.25 Gbps) Setting 0x01
Setting 0x05
Setting 0x05
Setting 0x05
1080P (1.65 Gbps)
1080I (750 Mbps)
Setting 0x01
Setting 0x05
Table 4 provides the recommended EQ control settings for
various data rates and cable lengths for 28 AWG DVI/HDMI
compliant configurations. The EQ setting is made via three
EQ [2:0] pins.
TABLE 4. EQ Control Setting for STP Cable
Format (Data Rate)
1080P 36-bit (2.25 Gbps)
1080P (1.65 Gbps)
0 ~ 10m
> 10m
Setting 0x01
Setting 0x01
Setting 0x06
Setting 0x06
Setting 0x06
Setting 0x06
1080I (750 Mbps)
13
www.national.com
POWER SUPPLY BYPASSING
General Recommendations
Two approaches are recommended to ensure the
DS22EV5110 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so the VDD and GND planes create a
low inductance supply with distributed capacitance. Second,
careful attention to supply bypassing through the proper use
of bypass capacitors is required. A 0.1 μF bypass capacitor
should be connected to each VDD pin such that the capacitor
is placed as close as possible to the DS22EV5110. Smaller
body size capacitors can help facilitate proper component
placement. Additionally, two capacitors with capacitance in
the range of 2.2 μF to 10 μF should be incorporated in the
power supply bypassing design as well. These capacitors can
be either tantalum or an ultra-low ESR ceramic and should be
placed as close as possible to the DS22EV5110.
The DS22EV5110 is a high performance circuit capable of
delivering excellent performance. To achieve optimal perfor-
mance, careful attention must be paid to the details associ-
ated with high-speed design as well as providing a clean
power supply. Refer to the LVDS Owner’s Manual for more
detailed information on high-speed design tips as well as
many other available resources addressing signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The TMDS differential inputs and outputs must have a con-
trolled differential impedance of 100 Ω. It is preferable to route
TMDS lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if pos-
sible. If vias must be used, they should be used sparingly and
must be placed symmetrically for each side of a given differ-
ential pair. Route the TMDS signals away from other signals
and noise sources on the printed circuit board. All traces of
TMDS differential inputs and outputs must be equal in length
to minimize intra-pair skew.
EQUIVALENT I/O STRUCTURES
Figure 14 shows the DS22EV5110 CML output structure and
ESD protection circuitry.
Figure 15 shows the DS22EV5110 CML input structure and
ESD protection circuitry.
LLP FOOTPRINT RECOMMENDATIONS
See National application note: AN-1187, “Leadless Lead-
frame Package (LLP)” for additional information on LLP pack-
ages footprint and soldering information.
30094922
FIGURE 11. Equivalent Output Structure
30094923
FIGURE 12. Equivalent Input Structure
www.national.com
14
Typical Performance Characteristics as a Repeater
30094909
FIGURE 13. Simplified Test Setup as a Single Repeater
30094960
30094961
FIGURE 14. System Source Eye Diagram at TPA
(2.25 Gbps)
FIGURE 15. Device Sink Eye Diagram at TPB
(2.25 Gbps, Cable A = 25m 28 AWG HDMI)
30094963
30094962
FIGURE 17. Device Source Eye Diagram at TPC
FIGURE 16. Device Source Eye Diagram at TPC
(2.25 Gbps, Cable A = 25m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = -3dB)
(2.25 Gbps, Cable A = 25m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = 0dB)
30094964
FIGURE 18. System Sink Eye Diagram at TPD
(2.25 Gbps, Cable A = 25m 28 AWG HDMI, Cable B = 7.5m
28AWG HDMI, EQ = 0x05, BYPASS = 0, DE = -3dB)
15
www.national.com
FIGURE 19. System Source Eye Diagra3m009a49t65TPA
(1.65 Gbps)
FIGURE 20. Device Sink Eye Diagram30a0t94T96P6 B
(1.65 Gbps, Cable A = 35m 28 AWG HDMI)
30094967
30094968
FIGURE 21. Device Source Eye Diagram at TPC
FIGURE 22. Device Source Eye Diagram at TPC
(1.65 Gbps, Cable A = 35m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = 0dB)
(1.65 Gbps, Cable A = 35m 28 AWG HDMI,
EQ = 0x05, BYPASS = 0, DE = -6dB)
FIGURE 23. System Sink Eye Diagram 3a0t09T49P69D
(1.65 Gbps, Cable A = 35m 28 AWG HDMI, Cable B = 10m
28AWG HDMI, EQ = 0x05, BYPASS = 0, DE = -6dB)
www.national.com
16
Physical Dimensions inches (millimeters) unless otherwise noted
7mm x 7mm 48-pin LLP Package
Order Number DS22EV5110SQ
Package Number SQA48A
17
www.national.com
Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
Products
www.national.com/amplifiers
Design Support
www.national.com/webench
Amplifiers
WEBENCH® Tools
App Notes
Audio
www.national.com/audio
www.national.com/timing
www.national.com/adc
www.national.com/interface
www.national.com/lvds
www.national.com/power
www.national.com/appnotes
www.national.com/refdesigns
www.national.com/samples
www.national.com/evalboards
www.national.com/packaging
www.national.com/quality/green
www.national.com/contacts
www.national.com/quality
www.national.com/feedback
www.national.com/easy
Clock and Timing
Data Converters
Interface
Reference Designs
Samples
Eval Boards
LVDS
Packaging
Power Management
Green Compliance
Distributors
Switching Regulators www.national.com/switchers
LDOs
www.national.com/ldo
www.national.com/led
www.national.com/vref
www.national.com/powerwise
Quality and Reliability
Feedback/Support
Design Made Easy
Solutions
LED Lighting
Voltage Reference
PowerWise® Solutions
www.national.com/solutions
www.national.com/milaero
www.national.com/solarmagic
www.national.com/training
Serial Digital Interface (SDI) www.national.com/sdi
Mil/Aero
Temperature Sensors
Wireless (PLL/VCO)
www.national.com/tempsensors SolarMagic™
www.national.com/wireless
PowerWise® Design
University
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2009 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
National Semiconductor Europe
Technical Support Center
Email: europe.support@nsc.com
National Semiconductor Asia
Pacific Technical Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Technical Support Center
Email: jpn.feedback@nsc.com
Email: support@nsc.com
Tel: 1-800-272-9959
www.national.com
相关型号：
©2020 ICPDF网 联系我们和版权申明