DS64EV400/NOPB [NSC]
IC TELECOM-LINE EQUALIZER, PQCC48, 7 X 7 MM, LEAD FREE, LLP-48, Analog Transmission Interface;
| 型号： | DS64EV400/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC TELECOM-LINE EQUALIZER, PQCC48, 7 X 7 MM, LEAD FREE, LLP-48, Analog Transmission Interface |
| 文件： | 总18页 (文件大小：1493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 18, 2008
DS64EV400
Programmable Quad Equalizer
General Description
Features
The DS64EV400 programmable quad equalizer provides
compensation for transmission medium losses and reduces
the medium-induced deterministic jitter for four NRZ data
channels. The DS64EV400 is optimized for operation up to
10 Gbps for both cables and FR4 traces. Each equalizer
channel has eight levels of input equalization that can be pro-
grammed by three control pins, or individually through a Serial
Management Bus (SMBus) interface.
Equalizes up to 24 dB loss at 10 Gbps
Equalizes up to 22 dB loss at 6.4 Gbps
8 levels of programmable equalization
■
■
■
■
■
■
■
Settable through control pins or SMBus interface
Operates up to 10 Gbps with 30” FR4 traces
Operates up to 6.4 Gbps with 40” FR4 traces
0.175 UI residual deterministic jitter at 6.4 Gbps with 40”
FR4 traces
The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and bal-
anced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs. The
DS64EV400 is available in a 7 mm x 7 mm 48-pin leadless
LLP package. Power is supplied from either a 2.5V or 3.3V
supply.
Single 2.5V or 3.3V power supply
Signal Detect for individual channels
Standby mode for individual channels
■
■
■
■
Supports AC or DC-Coupling with wide input common-
mode
Low power consumption: 375 mW Typ at 2.5V
Small 7 mm x 7 mm 48-pin LLP package
9 kV HBM ESD Rating
■
■
■
■
-40 to 85°C operating temperature range
Simplified Application Diagram
30032024
© 2008 National Semiconductor Corporation
300320
www.national.com
Pin Descriptions
Pin Name
Pin #
I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0–
1
2
I, CML
I, CML
I, CML
I, CML
O, CML
O, CML
O, CML
O, CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_0+ and IN_0-. Refer to Figure 6.
IN_1+
IN_1–
4
5
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_1+ and IN_1-. Refer to Figure 6.
IN_2+
IN_2–
8
9
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_2+ and IN_2-. Refer to Figure 6.
IN_3+
IN_3–
11
12
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω
terminating resistor is connected between IN_3+ and IN_3-. Refer to Figure 6.
OUT_0+
OUT_0–
36
35
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to VDD and OUT_0- to VDD
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to VDD and OUT_1- to VDD
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to VDD and OUT_2- to VDD
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to VDD and OUT_3- to VDD
.
OUT_1+
OUT_1–
33
32
.
OUT_2+
OUT_2–
29
28
.
OUT_3+
OUT_3–
26
25
.
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
37
14
23
I, LVCMOS BST_2, BST_1, and BST_0 select the equalizer strength for all EQ channels. BST_2 is
internally pulled high. BST_1 and BST_0 are internally pulled low.
DEVICE CONTROL
EN0
EN1
EN2
EN3
FEB
44
42
40
38
21
I, LVCMOS Enable Equalizer Channel 0 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
I, LVCMOS Enable Equalizer Channel 1 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
I, LVCMOS Enable Equalizer Channel 2 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
I, LVCMOS Enable Equalizer Channel 3 input. When held High, normal operation is selected. When held
Low, standby mode is selected. EN is internally pulled High.
I, LVCMOS Force External Boost. When held high, the equalizer boost setting is controlled by BST_[2:0]
pins. When held low, the equalizer boost setting is controlled by SMBus (see Table 1) register
bits. FEB is internally pulled High.
SD0
45
43
41
39
O, LVCMOS Equalizer Ch0 Signal Detect Output. Produces a High when signal is detected.
O, LVCMOS Equalizer Ch1 Signal Detect Output. Produces a High when signal is detected.
O, LVCMOS Equalizer Ch2 Signal Detect Output. Produces a High when signal is detected.
O, LVCMOS Equalizer Ch3 Signal Detect Output. Produces a High when signal is detected.
SD1
SD2
SD3
POWER
VDD
3, 6, 7,
10, 13,
15, 46
Power
Power
Power
VDD = 2.5V ± 5% or 3.3V ± 10%. VDD pins should be tied to VDD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each VDD pin to GND planes.
GND
DAP
22, 24,
27, 30,
31, 34
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
PAD
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
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2
Pin Name
Pin #
I/O, Type
Description
SERIAL MANAGEMENT BUS (SMBus) INTERFACE CONTROL PINS
SDA
SDC
CS
18
17
16
I/O, LVCMOS Data input/output (bi-directional). Internally pulled high.
I, LVCMOS Clock input. Internally pulled high.
I, LVCMOS Chip select. When pulled high, access to the equalizer SMBus registers are enabled. When
pulled low, access to the equalizer SMBus registers are disabled. Please refer to “SMBus
configuration Registers” section for detail information.
Other
Reserv
19, 20
47,48
Reserved. Do not connect.
Note: I = Input O = Output
Connection Diagram
30032026
Ordering Information
NSID
Package Type, Qty Size
Package ID
DS64EV400SQ
DS64EV400SQX
48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 250
48–pin LLP (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch, reel of 2500
SQA48D
SQA48D
3
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ESD Rating
Absolute Maximum Ratings (Note 1)
> 9 kV
HBM, 1.5 kΩ, 100 pF
CML Inputs
Thermal Resistance
ꢀθJA, No Airflow
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
> 250V
30°C/W
Supply Voltage (VDD
)
−0.5V to +4.0V
−0.5V + 4.0V
−0.5V to 4.0V
−0.5V to 4.0V
CMOS Input Voltage
Recommended Operating
Conditions
CMOS Output Voltage
CML Input/Output Voltage
Min
Typ
Max Units
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4
Seconds)
+150°C
−65°C to +150°C
+260°C
Supply Voltage (note 9)
VDD2.5 to GND
2.375
3.0
2.5 2.625
V
V
VDD3.3 to GND
3.3
25
3.6
Ambient Temperature
−40
+85
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Typ
(note 2)
Symbol
POWER
Parameter
Conditions
Min
Max
Units
P
P
N
Power Supply Consumption
Device Output Enabled
(EN [0–3] = High), VDD3.3
490
700
100
490
mW
mW
mW
Device Output Disable
(EN [0–3] = Low), VDD3.3
Power Supply Consumption
Device Output Enabled
(EN [0–3] = High), VDD2.5
360
30
Device Output Disable
(EN [0–3] = Low), VDD2.5
Supply Noise Tolerance (Note 4) 50 Hz — 100 Hz
100 Hz — 10 MHz
mVP-P
mVP-P
mVP-P
100
40
10
10 MHz — 1.6 GHz
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
VDD3.3
VDD2.5
2.0
1.6
-0.3
2.4
2.0
VDD3.3
VDD2.5
0.8
V
V
V
V
VIL
Low Level Input Voltage
High Level Output Voltage
VOH
IOH = -3mA, VDD3.3
IOH = -3mA, VDD2.5
IOL = 3mA
VOL
IIN
Low Level Output Voltage
Input Leakage Current
0.4
V
VIN = VDD
+15
μA
μA
μA
VIN = GND
-15
-20
IIN-P
Input Leakage Current with
Internal Pull-Down/Up Resistors
VIN = VDD, with internal pull-down
resistors
+120
VIN = GND, with internal pull-up
resistors
μA
SIGNAL DETECT
SDH
Signal Detect ON Threshold Level Default input signal level to assert
SD pin, 6.4 Gbps
70
40
mVp-p
mVp-p
SDI
Signal Detect OFF Threshold
Level
Default input signal level to de-
assert SD, 6.4 Gbps
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4
Typ
(note 2)
Symbol
Parameter
Conditions
Min
Max
Units
CML RECEIVER INPUTS (IN_n+, IN_n-)
VTX
Source Transmit Launch Signal
Level (IN diff)
AC-Coupled or DC-Coupled
Requirement, Differential
measurement at point A.
Figure 1
mVP-P
400
1600
VINTRE
VDDTX
VICMDC
Input Threshold Voltage
Differential measurement at
point B. Figure 1
mVP-P
V
120
Supply Voltage of Transmitter to DC-Coupled Requirement
EQ
VDD
1.6
(Note 10)
Input Common Mode Voltage
DC-Coupled Requirement,
Differential measurement at point
A. Figure 1, (Note 7)
VDDTX
0.8
–
VDDTX
0.2
–
V
RLI
RIN
Differential Input Return Loss
Input Resistance
100 MHz – 3.2 GHz, with fixture’s
effect de-embedded
10
dB
Differential across IN+ and IN-,
Figure 6.
85
100
115
725
Ω
CML OUTPUTS (OUT_n+, OUT_n-)
VOD
Output Differential Voltage Level Differential measurement with
(OUT diff)
OUT+ and OUT- terminated by
50Ω to GND, AC-Coupled
Figure 2
mVP-P
500
620
VOCM
Output Common Mode Voltage
Transition Time
Single-ended measurement DC-
Coupled with 50Ω terminations
(Note 7)
VDD– 0.2
VDD– 0.1
V
tR, tF
20% to 80% of differential output
voltage, measured within 1” from
output pins. Figure 2, (Note 7)
20
42
60
58
ps
RO
Output Resistance
Single ended to VDD
50
10
Ω
RLO
Differential Output Return Loss
100 MHz – 1.6 GHz, with fixture’s
effect de-embedded. IN+ = static
high.
dB
tPLHD
tPHLD
tCCSK
tPPSK
Differential Low to High
Propagation Delay
Propagation delay measurement
at 50% VO between input to
output, 100 Mbps. Figure 3,
(Note 7)
240
240
7
ps
ps
ps
ps
Differential High to Low
Propagation Delay
Inter Pair Channel to Channel
Skew
Difference in 50% crossing
between channels
Part to Part Output Skew
Difference in 50% crossing
between outputs
20
EQUALIZATION
DJ1
DJ2
DJ3
DJ4
RJ
Residual Deterministic Jitter
at 10 Gbps
30” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (27-1)
pattern. (Note 6)
UIP-P
UIP-P
UIP-P
0.20
0.17
0.12
Residual Deterministic Jitter
at 6.4 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x06, PRBS-7 (27-1)
pattern. (Note 5, 6)
0.26
0.20
0.16
Residual Deterministic Jitter
at 5 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)
pattern. (Note 5, 6)
Residual Deterministic Jitter
at 2.5 Gbps
40” of 6 mil microstrip FR4,
EQ Setting 0x07, PRBS-7 (27-1)
pattern. (Note 5, 6)
UIP-P
0.1
0.5
Random Jitter
(Note 7, 8)
psrms
5
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Typ
(note 2)
Symbol
Parameter
Conditions
Min
Max
Units
SIGNAL DETECT and ENABLE TIMING
tZISD
tIZSD
Input OFF to ON detect — SD
Output High Response Time
Response time measurement at
VIN to SD output, VIN = 800 mVP-P
100 Mbps, 40” of 6 mil microstrip
FR4
35
400
150
5
ns
ns
ns
ns
,
Input ON to OFF detect — SD
Output Low Response Time
(Figure 1, 4), (Note 7)
tOZOED
tZOED
EN High to Output ON Response Response time measurement at
Time
EN input to VO, VIN = 800 mVP-P,
100 Mbps, 40” of 6 mil microstrip
FR4
EN Low to Output OFF Response
Time
(Figure 1, 5), (Note 7)
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 3.3V or 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization at optimal boost setting and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 7: Measured with clock-like {11111 00000} pattern.
Note 8: Random jitter contributed by the equalizer is defined as sqrt (JOUT2 – JIN2). JOUT is the random jitter at equalizer outputs in ps-rms, see point C of Figure
1; JIN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
Note 9: The VDD2.5 is VDD = 2.5V ± 5% and VDD3.3 is VDD = 3.3V ± 10%.
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6
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
0.8
V
V
VIH
2.1
4
VDD
IPULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
mA
VDD
Nominal Bus Voltage
2.375
-200
3.6
V
ILEAK-Bus
ILEAK-Pin
CI
Input Leakage Per Bus Segment (Note 10)
Input Leakage Per Device Pin
+200
µA
µA
pF
-15
Capacitance for SDA and SDC
(Note 10, 11)
10
RTERM
External Termination Resistance VDD3.3
,
2000
1000
Ω
Ω
pull to VDD = 2.5V ± 5% OR 3.3V ±
10%
(Note 10, 11, 12)
VDD2.5
(Note 10, 11, 12)
SERIAL BUS INTERFACE TIMING SPECIFICATIONS (Figure 7)
,
FSMB
TBUF
Bus Operating Frequency
(Note 13)
10
100
kHz
µs
Bus Free Time Between Stop and
Start Condition
4.7
THD:STA
TSU:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
At IPULLUP, Max
4.0
4.7
µs
µs
Repeated Start Condition Setup
Time
TSU:STO
THD:DAT
TSU:DAT
TTIMEOUT
TLOW
Stop Condition Setup Time
Data Hold Time
4.0
300
250
25
µs
ns
ns
ms
µs
µs
Data Setup Time
Detect Clock Low Timeout
Clock Low Period
(Note 13)
35
4.7
4.0
THIGH
Clock High Period
(Note 13)
(Note 13)
50
2
TLOW:SEXT
Cumulative Clock Low Extend
Time (Slave Device)
ms
tF
Clock/Data Fall Time
Clock/Data Rise Time
(Note 13)
(Note 13)
(Note 13)
300
ns
ns
tR
1000
tPOR
Time in which a device must be
operational after power-on reset
500
ms
Note 10: Recommended value. Parameter not tested in production.
Note 11: Recommended maximum capacitance load per bus segment is 400pF.
Note 12: Maximum termination voltage should be identical to the device supply voltage.
Note 13: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common
AC specifications for details.
7
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SMBus Transactions
System Management Bus (SMBus)
and Configuration Registers
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
The System Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification. The use of the Chip
Select signal is required. Holding the CS pin High enables
the SMBus port allowing access to the configuration registers.
Holding the CS pin Low disables the device's SMBus allowing
communication from the host to other slave devices on the
bus. In the STANDBY state, the System Management Bus
remains active. When communication to other devices on the
SMBus is active, the CS signal for the DS32EV400s must be
driven Low.
Writing a Register
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
The address byte for all DS64EV400s is AC'h. Based on the
SMBus 2.0 specification, the DS64EV400 has a 7-bit slave
address of 1010110'b. The LSB is set to 0'b (for a WRITE),
thus the 8-bit value is 1010 1100'b or AC'h.
6.
The Host drive the 8-bit data byte.
7. The Device drives an ACK bit (“0”).
8. The Host drives a STOP condition.
The SDC and SDA pins are 3.3V LVCMOS signaling and in-
clude high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon
SMBus loading and speed. Note, these pins are not 5V tol-
erant.
9. The Host de-selects the device by driving its SMBus CS
signal Low.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SDC is High.
Reading a Register
To read a register, the following protocol is used (see SMBus
2.0 specification).
There are three unique states for the SMBus:
1. The Host (Master) selects the device by driving its
SMBus Chip Select (CS) signal High.
START: A High-to-Low transition on SDA while SDC is High
indicates a message START condition.
2. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
STOP: A Low-to-High transition on SDA while SDC is High
indicates a message STOP condition.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
IDLE: If SDC and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
6. The Host drives a START condition.
7. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
8. The Device drives an ACK bit “0”.
9. The Device drives the 8-bit data value (register contents).
10. The Host drives a NACK bit “1”indicating end of the
READ transfer.
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS
signal Low.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Please see Table 1 for more information.
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TABLE 1. SMBus Register Address
Name
Status
Status
Status
Address Default Type Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SD3
EN0
EN2
Bit 2
Bit 1
Bit 0
0x00
0x01
0x02
0x03
0x00
0x00
0x00
0x44
RO
RO
RO
RW
ID Revision
EN1
SD2
SD1
SD0
Boost 1
Boost 3
Boost 0
Boost 2
EN3
Enable/
Boost
(CH 0, 1)
EN1 Output Boost Control for CH1
EN0 Output Boost Control for CH0
0:Enable
1:Disable
0:Enable
1:Disable
000 (Min Boost)
001
000 (Min Boost)
001
010
010
011
011
100 (Default)
101
100 (Default)
101
110
110
111 (Max Boost)
111 (Max Boost)
Enable/
Boost
(CH 2, 3)
0x04
0x44
RW
EN3 Output Boost Control for CH3
EN2 Output Boost Control for CH2
0:Enable
1:Disable
000 (Min Boost)
001
0:Enable
1:Disable
000 (Min Boost)
001
010
010
011
011
100 (Default)
101
100 (Default)
101
110
110
111 (Max Boost)
111 (Max Boost)
Signal
Detect
0x05
0x06
0x00
0x00
RW
RW
SD3 ON Threshold
Select
00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
SD2 ON Threshold SD1 ON Threshold SD0 ON Threshold
Select Select Select
00: 70 mV (Default) 00: 70 mV (Default) 00: 70 mV (Default)
01: 55 mV
10: 90 mV
11: 75 mV
01: 55 mV
10: 90 mV
11: 75 mV
01: 55 mV
10: 90 mV
11: 75 mV
Signal
Detect
SD3 OFF Threshold SD2 OFF Threshold SD1 OFF Threshold SD0 OFF Threshold
Select
Select
Select
Select
00: 40 mV (Default)
01: 30 mV
10: 55 mV
00: 40 mV (Default) 00: 40 mV (Default) 00: 40 mV (Default)
01: 30 mV
10: 55 mV
11: 45 mV
01: 30 mV
10: 55 mV
11: 45 mV
01: 30 mV
10: 55 mV
11: 45 mV
11: 45 mV
SMBus
Control
0x07
0x08
0x00
0x78
RW
RW
Reserved
SMBus
Enable
Control
0: Disable
1: Enable
Output
Level
Reserved
Output Level:
00: 400 mVP-P
01: 540 mVP-P
10: 620 mVP-P
(Default)
Reserved
11: 760 mVP-P
Note: RO = Read Only, RW = Read/Write
9
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30032027
FIGURE 1. Test Setup Diagram
30032002
FIGURE 2. CML Output Transition Times
30032003
FIGURE 3. Propagation Delay Timing Diagram
30032004
FIGURE 4. Signal Detect (SD) Delay Timing Diagram
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10
30032005
FIGURE 5. Enable (EN) Delay Timing Diagram
300320017
FIGURE 6. Simplified Receiver Input Termination Circuit
300320018
FIGURE 7. SMBus Timing Parameters
11
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DATA CHANNELS
DS64EV400 Functional
Descriptions
The DS64EV400 is a programmable quad equalizer opti-
mized for operation up to 10 Gbps for backplane and cable
applications.
The DS64EV400 provides four data channels. Each data
channel consists of an equalizer stage, a limiting amplifier, a
DC offset correction block, and a CML driver as shown in Fig-
ure 8.
30032006
FIGURE 8. Simplified Block Diagram
EQUALIZER BOOST CONTROL
DEVICE STATE AND ENABLE CONTROL
Each data channel support eight programmable levels of
equalization boost. The state of the FEB pin determines how
the boost settings are controlled. If the FEB pin is held High,
then the equalizer boost setting is controlled by the Boost Set
pins (BST_[2:0]) in accordance with Table 2. If this program-
ming method is chosen, then the boost setting selected on the
Boost Set pins is applied to all channels. When the FEB pin
is held Low, the equalizer boost level is controlled through the
SMBus. This programming method is accessed via the ap-
propriate SMBus registers (see Table 1). Using this approach,
equalizer boost settings can be programmed for each channel
individually. FEB is internally pulled High (default setting);
therefore if left unconnected, the boost settings are controlled
by the Boost Set pins (BST_[0:2]). The eight levels of boost
settings enables the DS64EV400 to address a wide range of
media loss and data rates.
The DS64EV400 has an enable feature on each data channel
which provides the ability to control device power consump-
tion. This feature can be controlled either an Enable Pin
(EN_n) with Reg 07 = 00'h (default value), or by the Enable
Control Bit register which can be configured through the SM-
Bus port (see Table 1 and Table 3 for detail register informa-
tion), which require setting Reg 07 = 01'h and changing
register value of Reg 03, 04. If the Enable is activated using
either the external EN_n pin or SMBUS register, the corre-
sponding data channel is placed in the ACTIVE state and all
device blocks function as described. The DS64EV400 can al-
so be placed in STANDBY mode to save power. In the
STANDBY mode only the control interface including the SM-
Bus port, as well as the signal detection circuit remain active.
TABLE 3. Controlling Device State
Register 07[0] ENn Pin
CH 0:
Device State
TABLE 2. EQ Boost Control Table
(SMBus)
(CMOS) Reg. 03 bit 3
CH 1:
6 mil
24 AWG Channel Channel
BST_N
Loss at Loss at 5 [2, 1, 0]
3.2 GHz GHz (dB)
(dB)
Microstri Twin-AX
Reg. 03 bit 7
CH 2:
Reg. 04 bit 3
CH 3:
Reg. 04 bit 7
(EN Control)
p FR4
Trace
Length
(m)
cable
length (m)
0
0
2
3
4
5
0
5
0
0 0 0
0 0 1
0 1 0
0 1 1
5
6
0 : Disable
0 : Disable
1 : Enable
1 : Enable
1
0
X
X
0
1
ACTIVE
STANDBY
ACTIVE
10
15
20
7.5
10
10
14
18
X
X
12.5
1 0 0
STANDBY
(Default)
SIGNAL DETECT
25
30
40
6
7
15
17
22
21
24
30
1 0 1
1 1 0
1 1 1
The DS64EV400 features a signal detect circuit on each data
channel. The status of the signal of each channel can be de-
termined by either reading the Signal Detect bit (SDn) in the
SMBus registers (see Table 1) or by the state of each SDn
10
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12
pin. An output logic high indicates the presence of a signal
that has exceeded the ON threshold value (called SD_ON).
An output logic Low means that the input signal has fallen
below the OFF threshold value (called SD_OFF). These val-
ues are programmed via the SMBus (Table 1). If not pro-
grammed via the SMBus, the thresholds take on the default
values as shown in Table 4. The Signal Detect threshold val-
ues can be changed through the SMBus. All threshold values
specified are DC peak-to-peak differential signals (positive
signal minus negative signal) at the input of the device.
level is 620 mVp-p. The following Table presents the output
level values supported:
TABLE 5. Output Level Control Settings
All Channels : Bit All Channels : Bit
Output Level
Register 08
3
2
(mVP-P
)
0
0
1
1
0
1
0
1
400
540
620 (Default)
760
TABLE 4. Signal Detect Threshold Values
Channel 0: Channel 0:
Bit 1 Bit 0
Channel 1: Channel 1: Register 06
SD_OFF
Threshold
SD_ON
Threshold
Register 05
(mV)
AUTOMATIC ENABLE FEATURE
It may be desirable to place unused channels in power-saving
Standby mode. This can be accomplished by connecting the
Signal detect (SDn) pin to the Enable (ENn) pin for each
channel (See Figure 9). In order for this option to function
properly, the register value for Reg. 07 should be 00'h (default
value). If an input signal swing applied to a data channel is
above the voltage level threshold as shown in Table 4, then
the SDn output pin is asserted High. If the SDn pin is con-
nected to the ENn pin, this will enable the equalizer, limiting
amplifier, and output buffer on the data channels; thus the
DS64EV400 will automatically enter the ACTIVE state. If the
input signal swing falls below the SD_OFF threshold level,
then the SDn output will be asserted Low, causing the channel
to be placed in the STANDBY state.
Bit 3
Channel 2: Channel 2:
Bit 5 Bit 4
Channel 3: Channel 3:
Bit 2
(mV)
Bit 7
Bit 6
0
0
1
1
0
1
0
1
40 (Default)
70 (Default)
30
55
45
55
90
75
OUTPUT LEVEL CONTROL
The output amplitude of the CML drivers for each channel can
be controlled via the SMBus (see Table 1). The default output
13
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DS64EV400 Applications
Information
30032007
FIGURE 9. Automatic Enable Configuration
UNUSED EQUALIZER CHANNELS
First, the supply (VDD) and ground (GND) pins should be con-
nected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01μF bypass ca-
pacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the DS64EV400.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, three capacitors with capac-
itance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capac-
itors can be either tantalum or an ultra-low ESR ceramic and
should be placed as close as possible to the DS64EV400.
It is recommended to put all unused channels into standby
mode.
GENERAL RECOMMENDATIONS
The DS64EV400 is a high performance circuit capable of de-
livering excellent performance. Careful attention must be paid
to the details associated with high-speed design as well as
providing a clean power supply. Refer to the LVDS Owner's
Manual for more detailed information on high speed design
tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and outputs must have a controlled differen-
tial impedance of 100Ω. It is preferable to route CML lines
exclusively on one layer of the board, particularly for the input
traces. The use of vias should be avoided if possible. If vias
must be used, they should be used sparingly and must be
placed symmetrically for each side of a given differential pair.
Route the CML signals away from other signals and noise
sources on the printed circuit board. See AN-1187 for addi-
tional information on LLP packages.
DC COUPLING
The DS64EV400 supports both AC coupling with external ac
coupling capacitor, and DC coupling to its upstream driver, or
downstream receiver. With DC coupling, users must ensure
the input signal common mode is within the range of the elec-
trical specification VICMDC and the device output is terminated
with 50 Ω to VDD
.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS64EV400 is provided with an adequate power supply.
www.national.com
14
Typical Performance Eye Diagrams and Curves
30032009
30032008
Figure 9. Equalized Signal
(40 In FR4, 5Gbps, PRBS7, 0x07 Setting)
Figure 8. Equalized Signal
(40 In FR4, 2.5Gbps, PRBS7, 0x07 Setting)
30032011
30032010
Figure 11. Equalized Signal
Figure 10. Equalized Signal
(40 In FR4, 6.4 Gbps, PRBS31, 0x06 Setting)
(40 In FR4, 6.4 Gbps, PRBS7, 0x06 Setting)
30032013
30032012
Figure 13. Equalized Signal
(10m 24 AWG Twin-Ax Cable, 6.4 Gbps, PRBS7, 0x07 Setting)
Figure 12. Equalized Signal
(30 In FR4, 10 Gbps, PRBS7, 0x06 Setting)
15
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30032014
Figure 14. Equalized Signal
(32 In Tyco XAUI Backplane, 6.25 Gbps, PRBS7, 0x06 Setting)
30032015
30032016
Figure 15. DJ vs. EQ Setting (10 Gbps)
Figure 16. DJ vs EQ Setting (6.4 Gbps)
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16
Physical Dimensions inches (millimeters) unless otherwise noted
48-pin LLP Package (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch)
Order Number DS64EV400SQ
Package Number SQA48D
17
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