DS75162AN [NSC]
IEEE-488 GPIB Transceivers; IEEE-488 GPIB收发器
| 型号： | DS75162AN |
| 厂家： | 
National Semiconductor |
| 描述： | IEEE-488 GPIB Transceivers |
| 文件： | 总10页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1996
DS75160A/DS75161A/DS75162A
IEEE-488 GPIB Transceivers
General Description
Features
Y
8-channel bi-directional non-inverting transceivers
This family of high-speed-Schottky 8-channel bi-directional
transceivers is designed to interface TTL/MOS logic to the
IEEE Standard 488-1978 General Purpose Interface Bus
(GPIB). PNP inputs are used at all driver inputs for minimum
loading, and hysteresis is provided at all receiver inputs for
added noise margin. The IEEE-488 required bus termination
is provided internally with an active turn-off feature which
Y
Bi-directional control implemented with TRI-STATE
output design
É
Y
Y
Y
Y
Y
Y
Y
Y
Meets IEEE Standard 488-1978
High-speed Schottky design
Low power consumption
High impedance PNP inputs (drivers)
500 mV (typ) input hysteresis (receivers)
On-chip bus terminators
disconnects the termination from the bus when V
moved.
is re-
CC
The General Purpose Interface Bus is comprised of 16 sig-
nal lines Ð 8 for data and 8 for interface management. The
data lines are always implemented with DS75160A, and the
management lines are either implemented with DS75161A
in a single-controller system, or with DS75162A in a multi-
controller system.
No bus loading when V
is removed
CC
Pin selectable open collector mode on DS75160A driv-
er outputs
Y
Accommodates multi-controller systems
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/5804–15
Order Number DS75162AWM, DS75162AN
See NS Package Number M24B or N24B
Dual In-Line Package
TL/F/5804–1
Top View
Order Number DS75160AN or DS75160AWM
See NS Package Number M20B or N20A
TL/F/5804–16
Order Number DS75161AN or DS75161AWM
See NS Package Number M20B or N20B
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/F/5804
RRD-B30M36/Printed in U. S. A.
http://www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
5.25
Units
V
V
, Supply Voltage
CC
4.75
T , Ambient Temperature
A
0
70
C
§
Supply Voltage, V
Input Voltage
7.0V
5.5V
I
, Output Low Current
OL
Bus
CC
48
16
mA
mA
Terminal
b
a
65 C to 150 C
Storage Temperature Range
§
§
Lead Temperature (Soldering, 4 sec.)
260 C
§
Maximum Power Dissipation* at 25 C
Molded Package
§
1897 mW
*Derate molded package 15.2 mW/ C above 25 C.
§
§
Electrical Characteristics (Notes 2 and 3)
Symbol
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Voltage
Conditions
Min
Typ
Max
Units
V
V
V
V
V
2
V
V
IH
0.8
IL
e b
I
b
b
1.5
I
18 mA
0.8
500
3.5
3.4
0.3
0.4
0.2
0.1
V
IK
Input Hysteresis
Bus
400
2.7
2.5
mV
HYS
OH
e b
High-Level
Terminal
Bus (Note 5)
Terminal
Bus
I
I
I
I
800 mA
OH
OH
OL
OH
V
V
Output Voltage
e b
5.2 mA
e
e
V
OL
Low-Level
16 mA
48 mA
0.5
Output Voltage
0.5
100
20
e
5.5V
I
I
High-Level
V
I
V
I
V
I
IH
Terminal and
mA
Input Current
e
e
2.7V
0.5V
TE, PE, DC,
SC Inputs
Low-Level
IL
b
b
100
10
mA
Input Current
V
BIAS
Terminator Bias
Driver
e
I
0 (No Load)
2.5
3.0
3.7
V
I(bus)
Voltage at Bus Port
Disabled
e b
b
I
Terminator
V
V
1.5V to 0.4V
1.3
LOAD
I(bus)
Bus Loading
e
b
0.4V to 2.5V
0
3.2
I(bus)
Current
Bus
Driver
2.5
e
V
I(bus)
2.5V to 3.7V
mA
b
Disabled
3.2
e
e
V
V
3.7V to 5V
5V to 5.5V
0
2.5
2.5
40
I(bus)
0.7
I(bus)
e
e
0V to 2.5V
V
V
0V, V
mA
CC
I(bus)
e
e
b
b
b
b
75
I
I
Short-Circuit
Terminal
2V, V
O
0V (Note 4)
15
35
35
75
OS
CC
I
mA
Output Current
b
b
150
125
Bus (Note 5)
e
e
e
e
2V, V 0.8V
I
Supply Current
Transmit, TE
Receive, TE
2V, PE
85
DS75160A
e
e
0.8V
0.8V, PE
2V, V
70
84
85
100
125
125
I
mA
pF
e
e
e
e
e
0.8V, V 0.8V
I
DS75161A
DS75162A
Bus
TE
TE
0.8V, DC
0.8V, DC
e
e
0.8V
0.8V, SC
2V, V
I
e
e
0V to 2V,
C
IN
Bus-Port
V
CC
5V or 0V, V
I
20
30
e
1 MHz
Capacitance
f
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
a
Note 2: Unless otherwise specified, min/max limits apply across the 0 C to 70 C temperature range and the 4.75V to 5.25V power supply range. All typical
§
§
e
e
5.0V.
values are for T
25 C and V
§
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
A
CC
otherwise specified. All values shown as max or min are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: This characteristic does not apply to outputs on DS75161A and DS75162A that are open collector.
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2
e
e
g
5.0V 5%, T
A
Switching Characteristics V
0 C to 70 C (Note 1)
§ §
CC
DS75160A
DS75161A
DS75162A
Symbol
Parameter
From
To
Conditions
Units
Min Typ Max Min Typ Max Min Typ Max
e
e
e
t
t
t
t
t
t
Propagation Delay Time,
Low to High Level Output
V
2.3V
PLH
PHL
PLH
PHL
PZH
PHZ
L
10
14
14
10
19
15
20
20
20
20
32
22
10
14
14
10
23
15
20
20
20
20
40
25
10
14
14
10
23
15
20
20
20
20
40
25
ns
ns
ns
ns
ns
ns
R
38.3X
30 pF
L
Terminal Bus
C
L
Propagation Delay Time,
High to Low Level Output
Figure 1
e
e
e
Propagation Delay Time,
Low to High Level Output
V
L
5.0V
R
240X
30 pF
L
Bus
Terminal
C
L
Propagation Delay Time,
High to Low Level Output
Figure 2
e
e
Output Enable Time
to High Level
V
V
3.0V
0V
I
L
e
e
R
480X
15 pF
L
L
Output Disable Time
From High Level
TE, DC,
or SC
C
Figure 1
e
e
t
t
Output Enable Time
to Low Level
Bus
V
V
0V
(Note 2)
(Note 3)
PZL
I
24
17
35
25
28
17
48
27
28
17
48
27
ns
ns
2.3V
38.3X
15 pF
L
e
e
R
L
Output Disable Time
From Low Level
PLZ
C
L
Figure 1
e
e
t
t
Output Enable Time
to High Level
V
V
3.0V
0V
PZH
I
17
15
33
25
18
22
40
33
18
22
40
33
ns
ns
L
e
e
R
3 kX
15 pF
L
L
Output Disable Time
From High Level
PHZ
TE, DC,
or SC
C
Terminal
Figure 1
e
e
t
t
Output Enable Time
to Low Level
V
V
0V
(Note 2)
(Note 3)
PZL
I
25
15
39
27
28
20
52
35
28
20
52
35
ns
ns
5V
L
e
e
R
280X
15 pF
L
Output Disable Time
From Low Level
PLZ
C
L
Figure 1
e
e
t
t
Output Pull-Up Enable
Time (DS75160A Only)
V
V
3V
PZH
I
10
10
17
15
NA
NA
NA
NA
ns
ns
PE
0V
L
Bus
e
e
(Note 2)
R
480X
15 pF
L
L
Output Pull-UP Disable
Time (DS75160A Only)
PHZ
C
Figure 1
e
e
25 C and are meant for reference only.
Note 1: Typical values are for V
5.0V and T
§
Note 2: Refer to Functional Truth Tables for control input definition.
CC
A
Note 3: Test configuration should be connected to only one transceiver at a time due to the high current stress caused by the V voltage source when the output
I
connected to that input becomes active.
Switching Load Configurations
TL/F/5804–8
e
V
logic high
3.0V
0V
C
e
V
logic low
C
*C includes jig and probe capacitance
L
FIGURE 1
TL/F/5804–9
*C includes jig and probe capacitance
L
FIGURE 2
3
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Connection Diagrams (Continued)
Dual-In-Line Package
TL/F/5804–2
Top View
Dual-In-Line Package
TL/F/5804–3
Top View
Order Number DS75161AN, DS75162AN or DS75161AWM
See NS Package Number M20B, N20A or N22A
http://www.national.com
4
Functional Description
DS75160A
Logic Diagrams
DS75160A
This device is an 8-channel bi-directional transceiver with
one common direction control input, denoted TE. When
used to implement the IEEE-488 bus, this device is connect-
ed to the eight data bus lines, designated DIO –DIO . The
8
1
port connections to the bus lines have internal terminators,
in accordance with the IEEE-488 Standard, that are deacti-
vated when the device is powered down. This feature guar-
e
antees no bus loading when V
CC
0V. The bus port out-
puts also have a control mode that either enables or dis-
ables the active upper stage of the totem-pole configura-
tion. When this control input, denoted PE, is in the high
state, the bus outputs operate in the high-speed totem-pole
mode. When PE is in the low state, the bus outputs operate
as open collector outputs which are necessary for parallel
polling.
DS75161A
This device is also an 8-channel bi-directional transceiver
which is specifically configured to implement the eight man-
agement signal lines of the IEEE-488 bus. This device,
paired with the DS75160A, forms the complete 16-line inter-
face between the IEEE-488 bus and a single controller in-
strumentation system. In compliance with the system orga-
nization of the management signal lines, the SRQ, NDAC,
and NRFD bus port outputs are open collector. In contrast
to the DS75160A, these open collector outputs are a fixed
configuration. The direction control is divided into three
groups. The DAV, NDAC, and NRFD transceiver directions
are controlled by the TE input. The ATN, SRQ, REN, and
IFC transceiver directions are controlled by the DC input.
The EOI transceiver direction is a function of both the TE
and DC inputs, as well as the logic level present on the ATN
channel. The port connections to the bus lines have internal
terminators identical to the DS75160A.
DS75162A
This device is identical to the DS75161A, except that an
additional direction control input is provided, denoted SC.
The SC input controls the direction of the REN and IFC
transceivers that are normally controlled by the DC input on
the DS75161A. This additional control function is instrumen-
tal in implementing multiple controller systems.
Table of Signal Line Abbreviations
Signal Line
Mne-
monic
Classi-
fication
Definition
Device
DC
Direction Control
DS75161A/
DS75162A
Control
Signals
PE
TE
SC
Pull-Up Enable
Talk Enable
DS75160A
All
System Controller
DS75162A
TL/F/5804–4
Data
I/O Ports
B1–B8 Bus Side of Device
DS75160A
D1–D8 Terminal Side
of Device
ATN
DAV
EOI
IFC
Attention
Data Valid
End or Identify
Interface Clear
Management
Signals
DS75161A/
DS75162A
NDAC Not Data Accepted
NRFD Not Ready for Data
REN
Remote Enable
SRQ Service Request
5
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Logic Diagrams (Continued)
DS75161A
DS75162A
TL/F/5804–5
TL/F/5804–6
TL/F/5804–7
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6
Switching Waveforms
Transmit Propagation Delays
Receive Propagation Delays
Terminal Enable/Disable Times
TL/F/5804–10
TL/F/5804–11
TL/F/5804–12
Bus Enable/Disable Times
TL/F/5804–13
s
5 ns
e
e
t
f
*Input signal: f
1.0 MHz, 50% duty cycle, t
r
Performance Characteristics
Bus Port Load Characteristics
TL/F/5804–14
Refer to Electrical Characteristics table
7
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Functional Truth Tables
DS75160A
Data Transceivers
Direction Bus Port Configuration
Control Input
Level
TE
PE
H
H
L
H
L
T
T
R
Totem-Pole Output
Open Collector Output
Input
X
DS75161A
Control Input Level
Transceiver Signal Direction
TE
DC
ATN*
EOI REN IFC SRQ NRFD NDAC DAV
H
H
L
H
L
R
T
R
T
R
T
R
T
R
T
R
T
T
R
T
R
R
T
T
R
R
T
T
T
T
H
L
R
R
L
R
H
L
X
X
H
L
H
H
L
T
R
R
T
X
X
L
DS75162A
Transceiver Signal Direction
ATN* EOI REN IFC SRQ NRFD NDAC DAV
Control Input Level
SC
TE
DC
H
H
H
H
L
H
H
L
H
L
R
T
R
T
R
T
R
T
T
T
T
T
T
R
T
R
R
T
T
R
R
T
T
R
R
T
T
R
R
T
T
T
T
H
L
T
T
R
R
T
L
T
T
R
T
H
H
L
H
L
R
R
R
R
R
R
R
R
L
R
T
T
L
H
L
R
R
L
L
R
X
X
X
X
H
L
X
X
H
L
H
H
L
T
R
R
T
X
X
L
e
e
e
e
e
H
L
High level input
Low level input
Don’t care
X
T
R
Transmit, i.e., signal outputted to bus
Receive, i.e., signal outputted to terminal
*The ATN signal level is sensed for internal multiplex control of EOI transmission direction logic.
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8
Physical Dimensions inches (millimeters)
Order Number DS75160AWM
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number DS75160AN or DS75161AN
NS Package Number N20A
9
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Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number DS75162AN
NS Package Number N22A
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