DS75208 [NSC]
Dual Line Receivers; 双线路接收器
| 型号： | DS75208 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual Line Receivers |
| 文件： | 总10页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1996
DS55107/DS75107/DS75108/DS75208
Dual Line Receivers
General Description
a
sup-
The products described herein are TTL compatible dual
high speed circuits intended for sensing in a broad range of
system applications. While the primary usage will be for line
receivers of MOS sensing, any of the products may effec-
tively be used as voltage comparators, level translators,
window detectors, transducer preamplifiers, and in other
sensing applications. As digital line receivers the products
are applicable with the SN55109/SN75109 and mA75110/
DS75110 companion drivers, or may be used in other bal-
anced or unbalanced party-line data transmission systems.
The improved input sensitivity and delay specifications of
the DS75208 make it ideal for sensing high performance
MOS memories as well as high sensitivity line receivers and
voltage comparators.
useful in certain applications that have multiple V
CC
a
plies or V
supplies that are turned off.
CC
Features
Y
Diode protected input stage for power ‘‘OFF’’ condition
Y
Y
Y
Y
Y
Y
Y
Y
Y
17 ns typ high speed
TTL compatible
g
g
g
10 mV or 25 mV input sensitivity
3V input common-mode range
e
High input impedance with normal V , or V
CC
0V
CC
Strobes for channel selection
Dual circuits
Sensitivity gntd. over full common-mode range
Input protection diodes are incorporated in series with the
collectors of the differential input stage. These diodes are
Logic input clamp diodesÐmeets both ‘‘A’’ and ‘‘B’’
version specifications
Y
g
5V standard supply voltages
Connection Diagram
Dual-In-Line Package
TL/F/9446–1
Top View
Order Number DS75107M, DS75107N, DS75107AM, DS75107AN,
DS75108M, DS75108N or DS75208N
See NS Package Number M14A or N14A
For Complete Military 883 Specifications, see RETS Datasheet.
Order Number DS55107AJ/883
See NS Package Number J14A
Selection Guide
s
Cavity Dip
s
s
s
a
T
A
b
a
55 C
§
T
A
125 C
§
0 C
§
70 C
§
TempPearcaktaugreex
x
Input Sensitivityx
Cavity or Molded Dip
g
g
g
10 mV
25 mV
25 mV
Output Logic
v
TTL Active Pull-Up
TTL Open Collector
DS55107
DS75107
DS75108 DS75208
C
1996 National Semiconductor Corporation
TL/F/9446
RRD-B30M36/Printed in U. S. A.
http://www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
a
Strobe Input Voltage
5.5V
b
a
65 C to 150 C
Storage Temperature Range
§
§
Maximum Power Dissipation* at 25 C
Cavity Package
Molded Package
§
Supply Voltage, V
Supply Voltage, V
7V
7V
6V
5V
CC
1308 mW
1207 mW
b
b
g
g
CC
Differential Input Voltage
Lead Temperature (Soldering, 4 sec)
260 C
§
*Derate cavity package 8.7 mW/ C above 25 C; derate molded package 9.7
§
§
Common Mode Input Voltage
mW/ C above 25 C.
§
§
Operating Conditions
DS75107,
DS75108, DS75208
DS55107
Min
Nom
Max
Min
4.75V
Nom
Max
a
Supply Voltage V
Supply Voltage V
4.5V
5V
5.5V
5V
5.25V
CC
b
b
b
5V
to
b
b
b
5V
to
b
5.25V
4.5V
5.5V
4.75V
CC
b
a
a
70 C
Operating Temperature Range
55 C
§
125 C
§
0 C
§
§
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
b
e
a
a
Note 2. Unless otherwise specified min/max limits apply across the 55 C to 125 C temperature range for the DS55107 and across the 0 C to 70 C range for
§
25 C and V
§
CC
§
§
e
5V.
the DS75107, DS75108 and DS75208. All typical values are for T
§
A
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
DS55107/DS75107, DS75108
Electrical Characteristics T
s
s
T
T
A
(Notes 2, 3)
MAX
MIN
Symbol
Parameter
Conditions
Min
Typ
Max Units
e
0.5V, V
e
b
I
High Level Input Current
into A1, B1, A2 or B2
V
V
Max, V
Max,
e b
3V to 3V
a
IH
CC
ID
CC
30
75
mA
mA
e
IC
e
e
Max,
3V to 3V
I
Low Level Input Current
into A1, B1, A2 or B2
V
CC
V
ID
Max, V
2V, V
a
b
CC
e b
IL
b
10
e b
IC
e
a
b
e
I
High Level Input Current
into G1 or G2
V
CC
V
CC
Max,
Max
V
V
2.4V
40
1
mA
IH
IH(S)
IH(S)
e
Max V
mA
a
CC
e
a
e
Max,
I
Low Level Input Current
into G1 or G2
V
V
Max, V
0.4V
b
IL
CC
CC
b
1.6
mA
e
IL(S)
e
e
e
e
I
High Level Input Current into S
V
CC
V
CC
Max,
Max
V
V
2.4V
Max V
80
2
mA
a
b
IH
IH(S)
IH(S)
mA
a
CC
e
e
e
I
Low Level Input Current into S
High Level Output Voltage
V
V
Max, V
0.4V
Max,
Min,
a
b
IL
CC
CC
b
3.2
mA
V
IL(S)
e
e b
e b
e
b
V
V
I
Min, V
CC
400 mA, V
a
LOAD
OH
CC
e
3V to 3V, (Note 3)
25 mV,
2.4
ID
V
IC
e
a
e
V
Low Level Output Voltage
V
I
Min, V
CC
16 mA, V
3V to 3V
Min, V
b
CC
Min,
e b
b
OL
CC
e
25 mV,
0.4
V
SINK
ID
e b
V
IC
e
a
e
I
High Level Output Current
Short Circuit Output Current
High Logic Level Supply
V
V
Min
, (Note 4)
OH
CC
OH
250
mA
mA
mA
mA
V
e
Max V
a
CC
e
(Notes 2 and 3)
e
I
V
CC
Max, V
Max,
a
b
b
OS
CC
b
b
70
18
e
Max, V
CC
25 mV, T
e
I
I
V
CC
V
ID
Max,
a
b
a
e
CCH
CCH
18
30
e
25 C
Current from V
CC
§
A
e
Max, V
25 mV, T
e
High Logic Level Supply
Current from V
CC
V
CC
V
ID
Max,
e
25 C
a
e
b
CC
b
b
15
8.4
§
A
e
e
V
I
Input Clamp Voltage on G or S
V
I
Min, V
CC
12 mA, T
Min,
e
25 C
a
b
CC
b
b
1.5
1
e b
§
IN
A
http://www.national.com
2
e
e b
e
5V, T 25 C
A
Switching Characteristics V
5V, V
CC
a
b
§
CC
Symbol
Parameter
Conditions
Min
Typ
17
Max
25
Units
ns
e
(Note 1)
e
e
e
e
t
t
t
t
Propagation Delay Time, Low to
High Level, from Differential
Inputs A and B to Output
R
L
390X, C
50 pF,
50 pF,
50 pF
50 pF
(Note 3)
PLH(D)
PHL(D)
PLH(S)
PHL(S)
L
L
L
L
(Note 4)
19
25
ns
e
(Note 1)
Propagation Delay Time, High to
Low Level, from Differential
Inputs A and B to Output
R
L
390X, C
(Note 3)
(Note 4)
17
19
25
25
ns
ns
e
e
Propagation Delay Time, Low to
High Level, from Strobe Input G
or S to Output
R
L
R
L
390X, C
390X, C
(Note 3)
(Note 4)
10
13
15
20
ns
ns
Propagation Delay Time, High to
Low Level, from Strobe Input G
or S to Output
(Note 3)
(Note 4)
8
15
20
ns
ns
13
a
b
Note 1: Differential input is 100 mV to 100 mV pulse. Delays read from 0 mV on input to 1.5V on output.
Note 2: Only one output at a time should be shorted.
Note 3: DS55107/DS75107 only.
Note 4: DS75108 only.
DS75208
s
s
a
Electrical Characteristics 0 C
§
T
A
70 C
§
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
0.5V, V
e
b
I
High Level Input Current
into A1, B1, A2 or B2
V
V
Max, V
Max,
e b
3V to 3V
a
e
IH
CC
CC
30
75
mA
ID
IC
e
e b
e
Max,
I
Low Level Input Current
into A1, B1, A2 or B2
V
V
Max, V
b
CC
a
IL
CC
b
10
mA
e b
2V, V
3V to 3V
ID
IC
e
a
e
e
I
High Level Input Current
into G1 or G2
V
V
Max,
Max
V
2.4V
40
mA
IH
CC
IH(S)
e
b
CC
V
IH(S)
Max V
1
mA
a
a
CC
e
a
e
I
Low Level Input Current
into G1 or G2
V
V
Max, V
0.4V
Max,
b
IL
CC
CC
b
1.6
mA
e
IL(S)
e
e
e
e
I
High Level Input Current into S
V
V
Max,
Max
V
V
2.4V
80
mA
a
IH
CC
IH(S)
b
CC
Max V
2
mA
IH(S)
CC
e
e
e
I
Low Level Input Current into S
Low Level Output Voltage
V
V
Max, V
0.4V
Max,
a
b
IL
CC
CC
b
3.2
mA
V
IL(S)
e
e
b
e b
10 mV,
V
V
CC
Min, V
CC
Min,
a
OL
e
I
16 mA, V
ID
0.4
SINK
e b
V
IC
3V to 3V
e
a
e
Min,
I
High Level Output Current
High Logic Level Supply
V
V
Min, V
CC
b
OH
CC
OH
250
30
mA
mA
mA
V
e
Max V
CC
a
e
e
Max, V
b
CC
I
I
V
V
Max,
e
25 C
a
b
a
CCH
CCH
CC
18
e
Current from V
10 mV, T
A
a
§
CC
ID
e
e
b
High Logic Level Supply
V
V
Max, V
Max,
e
25 C
a
CC
CC
b
b
15
8.4
e
Current from V
10 mV, T
A
b
§
CC
ID
e
e
b
V
Input Clamp Voltage on G or S
V
I
Min, V
CC
Min,
e
25 C
a
I
CC
b
b
1.5
1
e b
12 mA, T
§
IN
A
3
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e
e b
e
5V, T 25 C
A
Switching Characteristics V
5V, V
CC
a
b
§
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
e
e
e
e
e
e
t
t
t
t
Propagation Delay Time, Low-to-
High Level, from Differential
Inputs A and B to Output
R
470X, C
470X, C
470X, C
470X, C
15 pF, (Note 1)
15 pF, (Note 1)
15 pF
PLH(D)
PHL(D)
PLH(S)
PHL(S)
L
L
L
L
L
L
L
L
35
ns
Propagation Delay Time, High-to-
Low Level, from Differential
Inputs A and B to Output
R
R
R
20
17
17
ns
ns
ns
Propagation Delay Time, Low-to-
High Level, from Strobe Input G
or S to Output
Propagation Delay Time, High-to-
Low Level, from Strobe Input G
or S to Output
15 pF
a
b
Note 1: Differential input is 10 mV to 30 mV pulse. Delays read from 0 mV on input to 1.5V on output.
Voltage Waveforms
TL/F/9446–12
Typical Applications
Basic Balanced-Line Transmission System
TL/F/9446–2
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4
Typical Applications (Continued)
Data-Bus or Party-Line System
TL/F/9446–3
APPLICATION
25 mV (or less). For normal line resistances, data may be
recovered from lines of several thousand feet in length.
The DS55107, DS75107 dual line circuits are designed spe-
cifically for use in high speed data transmission systems
that utilize balanced, terminated transmission lines such as
twisted-pair lines. The system operates in the balanced
mode, so that noise induced on one line is also induced on
the other. The noise appears common mode at the receiver
input terminals where it is rejected. The ground connection
between the line driver and receiver is not part of the signal
circuit so that system performance is not affected by circu-
lating ground currents.
Line termination resistors (R ) are required only at the ex-
T
treme ends of the line. For short lines, termination resistors
at the receiver only may prove adequate. The signal ampli-
tude will then be approximately:
j
c
V
DIFF
I
R
T
(2)
O(on)
The strobe feature of the receivers and the inhibit feature of
the drivers allow the DS55107, DS75107 dual line circuits to
be used in data-bus or party-line systems. In these applica-
tions, several drivers and receivers may share a common
transmission line. An enabled driver transmits data to all
enabled receivers on the line while other drivers and receiv-
ers are disabled. Data is thus time multiplexed on the trans-
mission line. The DS55107, DS75107 device specifications
allow widely varying thermal and electrical environments at
the various driver and receiver locations. The data-bus sys-
tem offers maximum performance at minimum cost.
The unique driver output circuit allows terminated transmis-
sion lines to be driven at normal line impedances. High
speed system operation is ensured since line reflections are
virtually eliminated when terminated lines are used. Cross-
talk is minimized by low signal amplitudes and low line im-
pedances.
a
The typical data delay in a system is approximately (30
1.3L) ns, where L is the distance in feet separating the driv-
er and receiver. This delay includes one gate delay in both
the driver and receiver.
The DS55107, DS75107 dual line circuits may also be used
in unbalanced or single line systems. Although these sys-
tems do not offer the same performance as balanced sys-
tems for long lines, they are adequate for very short lines
where environment noise is not severe.
Data is impressed on the balanced-line system by unbalanc-
ing the line voltages with the driver output current. The driv-
en line is selected by appropriate driver input logic levels.
The voltage difference is approximately:
The receiver threshold level is established by applying a DC
reference voltage to one receiver input terminal. The signal
from the transmission line is applied to the remaining input.
The reference voltage should be optimized so that signal
j
c
V
DIFF
(/2 I
O(on)
R
T
(1)
High series line resistance will cause degradation of the sig-
nal. The receivers, however, will detect signals as low as
5
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Typical Applications (Continued)
swing is symmetrical about it for maximum noise margin.
DS75108 Wired-OR Output Connections
b
The reference voltage should be in the range of 3.0V to
3.0V. It can be provided by a voltage supply or by a volt-
a
age divider from an available supply voltage.
Unbalanced or Single-Line Systems
TL/F/9446–4
TL/F/9446–6
Precautions in the Use of DS1603, DS3603, DS55107,
DS75107, DS75108 and DS75208 Dual Line Receivers
Circuit Differences Between ‘‘A’’ and Standard Devices
The difference between the ‘‘A’’ and standard devices is
shown in the following schematics of the input stage.
The following precaution should be observed when using or
testing DS55107, DS75107 line circuits.
When only one receiver in a package is being used, at least
one of the differential inputs of the unused receiver should
‘‘A’’ Devices
b
a
be terminated at some voltage between 3.0V and 3.0V,
preferably at ground. Failure to do so will cause improper
operation of the unit being used because of common bias
circuitry for the current sources of the two receivers.
The DS55107, DS75107 and DS75108 line receivers fea-
g
ture a common mode input voltage range of 3.0V. This
satisfies the requirements for all but the noisiest system ap-
plications. For these severe noise environments, the com-
mon mode range can be extended by the use of external
input attenuators. Common mode input voltages can in this
g
way be reduced to 3.0V at the receiver input terminals.
Differential data signals will be reduced proportionately. In-
put sensitivity, input impedance and delay times will be ad-
versely affected.
The DS75108 line receivers feature an open-collector-out-
put circuit that can be connected in the DOT-OR logic con-
figuration with other DS75108 outputs. This allows a level of
logic to be implemented without addtional logic delay.
TL/F/9446–7
Increasing Common Mode Input
Voltage Range of Receiver
Standard Devices
TL/F/9446–5
TL/F/9446–8
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6
Typical Applications (Continued)
The input protection diodes are useful in certain party-line
This would be a problem in specific systems which might
possibly have the transmission lines biased to some poten-
tial greater than 1.4V. Since this is not a widespread appli-
cation problem, both the ‘‘A’’ and standard devices will be
available. The ratings and characteristic specifications of
the ‘‘A’’ devices are the same as those of the standard
devices.
a
systems which may have multiple V power supplies and,
in which case, may be operated with some of the V sup-
a
plies turned off. In such a system, if a supply is turned off
and allowed to go to ground, the equivalent input circuit
connected to that supply would be as follows:
‘‘A’’ Devices
The DS55107A feature the ‘‘A’’ device input stage.
TL/F/9446–9
Standard Devices
TL/F/9446–10
Schematic Diagrams
DS55107/DS75107, DS75108, DS75208
TL/F/9446–11
Note 1: (/2 of the dual circuit is shown.
Note 2: *Indicates connections common to second half of dual circuit.
Note 3: Components shown with dash lines are applicable to the DS55107, DS75207 and DS75107 only.
7
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8
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number DS55107J, DS75107J or DS75208J
NS Package Number J14A
Molded Dual-In-Line Package (M)
Order Number DS75107M, DS75107AM or DS75108M
NS Package Number M14A
9
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Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number DS75107N, DS75107AN, DS75108N or DS75208N
NS Package Number N14A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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a
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a
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a
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