DS78C120J/883 [NSC]
Dual CMOS Compatible Differential Line Receiver; 双CMOS兼容差动线路接收器
| 型号： | DS78C120J/883 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual CMOS Compatible Differential Line Receiver |
| 文件： | 总9页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1999
DS78C120
Dual CMOS Compatible Differential Line Receiver
General Description
Features
n Full compatibility with EIA Standards RS232-C, RS422
and RS423, Federal Standards 1020, 1030 and
MIL-188-114
The DS78C120 is a high performance, dual differential,
CMOS compatible line receiver for both balanced and unbal-
anced digital data transmission. The inputs are compatible
with EIA, Federal and MIL standards.
±
n Input voltage range of 15V (differential or
common-mode)
Input specifications meet or exceed those of the popular
DS7820 line receiver.
n Separate strobe input for each receiver
n 1/2 VCC strobe threshold for CMOS compatibility
n 5k typical input impedance
n 50 mV input hysteresis
±
The line receiver will discriminate a 200 mV input signal
±
±
over a common-mode range of 10V and a 300 mV signal
±
over a range of 15V.
n 200 mV input threshold
n Operation voltage range 4.5V to 15V
n Separate fail-safe mode
Circuit features include hysteresis and response control for
applications where controlled rise and fall times and/or high
frequency noise rejection are desirable. Threshold offset
control is provided for fail-safe detection, should the input be
open or short. Each receiver includes a 180Ω terminating re-
sistor and the output gate contains a logic strobe for time dis-
crimination. The DS78C120 is specified over a −55˚C to
+125˚C temperature range.
=
Connection Diagram
Dual-In-Line Package
DS005801-1
Top View
For Complete Military Product Specifications,
refer to the appropriate SMD or MDS.
Order Number DS78C120J/883
See NS Package Number J16A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS005801
www.national.com
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
−65˚C to +150˚C
260˚C
Lead Temperature (Soldering, 4 seconds)
Operating Conditions
Supply Voltage
18V
25V
18V
Min
Max
Units
±
Input Voltage
Supply Voltage (VCC
Temperature (TA)
DS78C120
)
4.5
15
V
Strobe Voltage
Output Sink Current
Maximum Power Dissipation (Note 1) at 25˚C
Cavity Package
50 mA
−55
−15
+125
+15
˚C
V
Common-Mode Voltage (VCM
)
1433 mW
1362 mW
Note 1: Derate cavity package 9.6 mW/˚C; derate molded package
10.9 mW/˚C above 25˚C.
Molded Package
Electrical Characteristics (Notes 3, 4)
Symbol
Parameter
Differential Threshold
Voltage
Conditions
Min
Typ
0.06
Max Units
=
VTH
VTL
VTH
IOUT −200 µA,
−7V ≤ VCM ≤ 7V
0.2
0.3
V
V
V
V
V
VOUT ≥ V − 1.2V
CC
−15V ≤ VCM ≤ 15V
0.06
=
Differential Threshold
Voltage
IOUT 1.6 mA,VOUT ≤ 0.5V −7V ≤ VCM ≤ 7V
−0.08
−0.08
0.47
−0.2
−0.3
0.7
−15V ≤ VCM ≤ 15V
=
Differential Threshold
Voltage Fail-Safe
IOUT −200 µA,
−7V ≤ VCM ≤ 7V
VOUT ≥ VCC − 1.2V
=
=
VTL
RIN
RT
Offset 5V
IOUT 1.6 mA,VOUT ≤ 0.5V −7V ≤ VCM ≤ 7V
0.2
4
0.42
5
V
kΩ
Ω
Input Resistance
−15V ≤V ≤ 15V, 0V ≤ VCC ≤ 15V
CM
=
Line Termination
Resistance
TA 25˚C
100
180
300
=
RO
Offset Control Resistance
Data Input Current
(Unterminated)
TA 25˚C
56
2
kΩ
mA
mA
mA
V
=
IIND
0V ≤ VCC ≤ 15V
VCM 10V
3.1
−0.5
−3.1
0.4
=
VCM 0V
0
=
VCM −10V
−2
0.1
=
VTHB
Input Balance
(Note 6)
IOUT 200 µA, VOUT
≥
−7V ≤ VCM ≤ 7V
=
VCC − 1.2V, RS 500Ω
=
IOUT 1.6 mA,VOUT ≤ 0.5V −7V ≤ VCM ≤ 7V
−0.1
−0.4
V
=
RS 500Ω
=
=
=
VOH
VOL
ICC
Logical “1” Output Voltage
Logical “0” Output Voltage
Power Supply Current
I
I
−200 µA, VDIFF 1V
VCC − 1.2 VCC − 0.75
V
V
OUT
OUT
=
1.6 mA, VDIFF −1V
0.25
8
0.5
15
30
=
15V ≤ VCM ≤ −15V,
VCC 5.5V
mA
mA
=
=
VDIFF −0.5V
VCC 15V
15
(Both Receivers)
=
=
=
15V, VDIFF 3V
IIN(1)
IIN(0)
VIH
Logical “1” Strobe Input
Current
V
V
STROBE
STROBE
15
100
µA
µA
=
0V, VDIFF −3V
Logical “0” Strobe Input
Current
−0.5
−100
=
=
Logical “1” Strobe Input
Voltage
VOL ≤ 0.5V, IOUT 1.6 mA
VCC 5V
3.5
8.0
2.5
5.0
7.5
2.5
5.0
7.5
−20
V
V
=
VCC 10V
=
VCC 15V
12.5
V
=
VIL
Logical “0” Strobe Input
Voltage
VOH
V
− 1.2V,
VCC 5V
1.5
2.0
2.5
−40
V
CC
=
=
IOUT −200 µA
VCC 10V
V
=
VCC 15V
V
=
=
=
IOS
Output Short-Circuit
Current
V
0V, VCC 15V, VSTROBE 0V, (Note 5)
−5
mA
OUT
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they
are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
=
=
Note 3: Unless otherwise specified min/max limits apply across the −55˚C to +125˚C temperature range for the DS78C120. All typical values for T
25˚C, V
CC
A
=
5V and V
0V.
CM
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2
Electrical Characteristics (Notes 3, 4) (Continued)
Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 5: Only one output at a time should be shorted.
Note 6: Refer to EIA-RS422 for exact conditions.
Switching Characteristics
=
=
VCC 5V, TA 25˚C
Symbol
Parameter
Conditions
Min
Typ
60
Max
100
150
70
Units
ns
=
CL 50 pF
tpd0(D)
tpd1(D)
tpd0(S)
tpd1(S)
Differential Input to “0” Output
Differential Input to “1” Output
Strobe Input to “0” Output
Strobe Input to “1” Output
=
CL 50 pF
100
30
ns
=
CL 50 pF
ns
=
CL 50 pF
100
150
ns
AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal
DS005801-3
*Includes probe and test fixture capacitance
DS005801-4
=
t
t ≤ 10 ns
f
r
=
PRR 1 MHz
Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).
3
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Schematic Diagram (1⁄
2
Circuit Shown)
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4
Application Hints
Balanced Data Transmission
DS005801-5
Unbalanced Data Transmission
DS005801-6
Logic Level Translator
DS005801-8
DS005801-7
±
The DS78C120 may be used a level transistor to interface between 12V MOS, ECL, TTL and CMOS. To configure, bias either
1
input to voltage equal to
⁄ the voltage of the input signal, and the other input to the driving gate.
2
5
www.national.com
Application Hints (Continued)
LINE DRIVERS
Line drivers which will interface with the DS78C120 are
listed below.
Balanced Drivers
DS26LS31Quad RS-422 Line Driver
DS7830, DS8830Dual TTL
®
DS7831, DS8831Dual TRI-STATE TTL
DS7832, DS8832Dual TRI-STATE TTL
DS1691A, DS3691- Dual RS-422
DS1692, DS3692 Dual TRI-STATE
RS-422
DS3587, DS3487Quad TRI-STATE RS-422
Unbalanced Drivers
DS005801-9
FIGURE 1. Noise Pulse Width vs
Response Control Capacitor
DS1488Quad RS-232
DS14C88Quad RS-232
DS75150Dual RS-232
RESPONSE CONTROL AND HYSTERESIS
In unbalanced (RS-232/RS-423) applications it is recom-
mended that the rise time and fall time of the line driver be
controlled to reduce cross-talk. Elimination of switching
noise is accomplished in the DS78C120 by the 50 mV of
hysteresis incorporated in the output gate. This eliminates
the oscillations which may appear in a line receiver due to
the input signal slowly varying about the threshold level for
extended periods of time.
DS005801-10
High frequency noise which is superimposed on the input
signal which may exceed 50 mV can be reduced in ampli-
tude by filtering the device input. On the DS78C120, a high
impedance response control pin in the input amplifier is
available to filter the input signal without affecting the termi-
nation impedance of the transmission line. Noise pulse width
rejection vs the value of the response control capacitor is
shown in Figure 1 and Figure 2. This combination of filters
followed by hysteresis will optimize performance in a worse
case noise environment.
TRANSMISSION LINE TERMINATION
DS005801-11
On a transmission line which is electrically long, it is advis-
able to terminate the line in its characteristic impedance to
prevent signal reflection and its associated noise/cross-talk.
A 180Ω termination resistor is provided in the DS78C120 line
receiver. To use the termination resistor, connect pins 2 and
3 together and pins 13 and 14 together. The 180Ω resistor
provides a good compromise between line reflections, power
dissipation in the driver, and IR drop in the transmission line.
If power dissipation and IR drop are still a concern, a capaci-
tor may be connected in series with the resistor to minimize
power loss.
FIGURE 2.
FAIL-SAFE OPERATION
Communication systems require elements of a system to de-
tect the presence of signals in the transmission lines, and it
is desirable to have the system shut-down in a fail-safe
mode if the transmission line is open or shorted. To facilitate
the detection of input opens or shorts, the DS78C120 incor-
porates an input threshold voltage offset. This feature will
force the line receiver to a specific logic state if presence of
either fault is a condition.
The value of the capacitor is recommended to be the line
length (time) divided by 3 times the resistor value. Example:
if the transmission line is 1,000 feet long, (approximately
1000 ns) the capacitor value should be 1852 pF. For addi-
tional application details, refer to application notes AN-22
and AN-108.
±
Given that the receiver input threshold is 200 mV, an input
signal greater than 200 mV insures the receiver will be in a
specific logic state. When the offset control input (pins 1 and
±
=
15) is connected to VCC 5V, the input thresholds are offset
from 200 mV to 700 mV, referred to the non-inverting input,
or −200 mV to −700 mV, referred to the inverting input.
Therefore, if the input is open or shorted, the input will be
greater than the input threshold and the receiver will remain
in a specified logic state.
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6
For unbalanced operation, the receiver would be in an inde-
terminate logic state if the offset control input was open.
Connecting the offset to 5V offsets the receiver threshold
0.45V. The output is forced to a logic zero state if the input is
open or shorted.
Application Hints (Continued)
The input circuit of the receiver consists of a 5k resistor ter-
minated to ground through 120Ω on both inputs. This net-
work acts as an attenuator, and permits operation with
±
common-mode input voltages greater than 15V. The offset
For balanced operation with inputs shorted or open, receiver
C will be in an indeterminate logic state. Receivers A and B
will be in a logic zero state allowing the NOR gate to detect
the short or open condition. The strobe will disable receivers
A and B and may therefore be used to sample the fail-safe
detector. Another method of fail-safe detection consists of fil-
tering the output of the NOR gate D so it would not indicate
a fault condition when receiver inputs pass through the
threshold region, generating an output transient.
control input is actually another input to the attenuator, but its
resistor value is 56k. The offset control input is connected to
the inverting input side of the attenuator, and the input volt-
age to the amplifier is the sum of the inverting input plus 0.09
times the voltage on the offset control input. When the offset
control input is connected to 5V the input amplifier will see
VIN(INVERTING) + 0.45V or VIN(INVERTING) + 0.9V when the
control input is connected to 10V. The offset control input will
not significantly affect the differential performance of the re-
ceiver over its common-mode operating range, and will not
change the input impedance balance of the receiver.
In a communications system, only the control signals are re-
quired to detect input fault condition. Advantages of a bal-
anced data transmission system over an unbalanced trans-
mission system are:
It is recommended that the receiver be terminated (500Ω or
less) to insure it will detect an open circuit in the presence of
noise.
1. High noise immunity
2. High data ratio
The offset control can be used to insure fail-safe operation
for unbalanced interface (RS-423) or for balanced interface
(RS-422) operation.
3. Long line lengths
Unbalanced RS-423 and RS-232 Fail-Safe
DS005801-12
7
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Application Hints (Continued)
Balanced RS-422 Fail Safe
DS005801-13
DS005801-14
DS005801-15
DS005801-16
Truth Table
(For Balanced Fail-Safe)
Input
Strobe A-OUT B-OUT C-OUT D-OUT
0
1
X
0
1
X
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
X
0
0
0
0
0
1
0
0
0
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8
Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number DS78C120J/883
NS Package Number J16A
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