DS90C383B [NSC]
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz; + 3.3V可编程LVDS发射器24位平板显示器（ FPD ）链路65兆赫
| 型号： | DS90C383B |
| 厂家： | 
National Semiconductor |
| 描述： | +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz |
| 文件： | 总11页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2006
DS90C383B
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link-65 MHz
General Description
Features
n No special start-up sequence required between
clock/data and /PD pins. Input signal (clock and data)
can be applied either before or after the device is
powered.
The DS90C383B transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fifth LVDS link. Every
cycle of the transmit clock 28 bits of input data are sampled
and transmitted. At a transmit clock frequency of 65 MHz, 24
bits of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughput is 227 Mbytes/sec. The DS90C383B trans-
mitter can be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge or
Falling edge strobe transmitter will interoperate with a Falling
edge strobe Receiver (DS90CF386) without any translation
logic.
n Support Spread Spectrum Clocking up to 100kHz
frequency modulation & deviations of 2.5% center
spread or −5% down spread.
n "Input Clock Detection" feature will pull all LVDS pairs to
logic low when input clock is missing and when /PD pin
is logic high.
n 18 to 68 MHz shift clock support
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption 130 mW (typ) 65MHz
Grayscale
n 40% Less Power Dissipation than BiCMOS Alternatives
<
@
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
<
n Tx Power-down mode 60µW (typ)
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.8 Gbps throughput
n Up to 227 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead TSSOP package
n Improved replacement for:
SN75LVDS83, DS90C383A
Block Diagram
DS90C383B
20098401
Order Number DS90C383BMT
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS200984
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
7 kV
500V
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
Recommended Operating
Conditions
CMOS/TTL Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit
Duration
Min Nom
Max
Units
Supply Voltage
(VCC
Operating Free Air
3.0
3.3
3.6
V
Continuous
+150˚C
)
Junction Temperature
Storage Temperature
Lead Temperature
−65˚C to +150˚C
Temperature (TA) −10
Supply Noise
+25
+70
200
˚C
mVPP
(Soldering, 4 sec)
+260˚C
Voltage (VCC
)
@
Maximum Package Power Dissipation Capacity 25˚C
TxCLKIN frequency
18
68
MHz
MTD56 (TSSOP) Package:
DS90C383B
Package Derating:
DS90C383B
1.63 W
12.5 mW/˚C above +25˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions
CMOS/TTL DC SPECIFICATIONS
Min
Typ
Max
Units
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
−0.79
+1.8
0
−1.5
+10
V
V
V
= 0.4V, 2.5V or VCC
= GND
µA
µA
IN
IN
−10
250
LVDS DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
345
450
35
mV
mV
∆VOD
Change in VOD between
complimentary output states
Offset Voltage (Note 4)
VOS
1.13
1.25
1.38
35
V
∆VOS
Change in VOS between
complimentary output states
Output Short Circuit Current
Output TRI-STATE® Current
mV
IOS
IOZ
VOUT = 0V, RL = 100Ω
−3.5
1
−5
10
mA
µA
Power Down = 0V,
VOUT = 0V or V
CC
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
Worst Case
RL = 100Ω,
CL = 5 pF,
f = 25MHz
f = 40MHz
f = 65 MHz
31
37
48
45
50
60
mA
mA
mA
Worst Case Pattern
(Figures 1, 4 )" Typ "
values are given for V
CC = 3.6V and T
=
A
+25˚C, " Max " values
are given for V
=
CC
3.6V and T = −10˚C
A
www.national.com
2
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TRANSMITTER SUPPLY CURRENT
ICCTG
Transmitter Supply Current
16 Grayscale
RL = 100Ω,
CL = 5 pF,
f = 25MHz
f = 40MHz
f = 65 MHz
29
40
mA
16 Grayscale Pattern
(Figures 2, 4 )" Typ "
values are given for V
33
39
17
45
50
mA
mA
µA
CC = 3.6V and T
=
A
+25˚C, " Max " values
are given for V
=
CC
3.6V and T = −10˚C
A
ICCTZ
Transmitter Supply Current
Power Down
Power Down = Low
150
Driver Outputs in TRI-STATE under
Power Down Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25˚C unless specified otherwise.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V and ∆V ).
OD
OD
Note 4:
V
OS
previously referred as V
.
CM
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
TCIT
Parameter
Min
Typ
Max Units
TxCLK IN Transition Time (Figure 5 )
TxCLK IN Period (Figure 6 )
5
ns
ns
ns
ns
ns
us
TCIP
14.7
T
50
TCIH
TCIL
TxCLK IN High Time (Figure 6 )
TxCLK IN Low Time (Figure 6)
0.35T 0.5T 0.65T
0.35T 0.5T 0.65T
TXIT
TxIN, and Power Down pins Transition Time
Minimum pulse width for Power Down pin signal
1.5
1
6.0
TXPD
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 4 )
LVDS High-to-Low Transition Time (Figure 4 )
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note
5)
Min
Typ
Max
Units
ns
0.75
0.75
0
1.4
1.4
LHLT
ns
TPPos0
f = 65
MHz
−0.20
+0.20
ns
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
2.00
4.20
2.20
4.40
2.40
4.60
ns
ns
ns
ns
ns
ns
6.39
6.59
6.79
8.59
8.79
8.99
10.79
12.99
10.99
13.19
11.19
13.39
3
www.national.com
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note
5)
Min
Typ
Max
Units
TPPos0
f = 40
MHz
−0.25
0
+0.25
ns
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note
5)
3.32
6.89
3.57
7.14
10.71
14.29
17.86
21.43
0
3.82
7.39
ns
ns
ns
ns
ns
ns
ns
10.46
14.04
17.61
21.18
−0.45
10.96
14.54
18.11
21.68
+0.45
f =
25MHz
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TSTC
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxIN Setup to TxCLK IN (Figure 6 )
5.26
10.98
16.69
22.41
25.12
33.84
2.5
5.71
6.16
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.43
17.14
22.86
28.57
34.29
11.88
17.59
23.31
29.02
34.74
THTC
TxIN Hold to TxCLK IN (Figure 6 )
0.5
TCCD
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle
input clock is assumed, TA= −10˚C, and 65MHz for ” Min ”,
TA= 70˚C,and 25MHz for ” Max ”, VCC= 3.6V, R_FB = VCC
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle
input clock is assumed, TA= −10˚C, and 65MHz for ” Min ”,
TA= 70˚C, and 25MHz for ” Max ”, VCC= 3.6V, R_FB = GND
3.340
7.211
6.062
3.011
ns
SSCG
f =
100kHz
25MHz
f =
2.5%/−5%
100kHz
Spread Spectrum Clock support; Modulation frequency with a
linear profile(Note 6).
40MHz
f =
2.5%/−5%
100kHz
65MHz
2.5%/−5%
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 8 )
Transmitter Power Down Delay (Figure 10 )
10
ms
ns
100
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking
Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
www.national.com
4
AC Timing Diagrams
20098404
FIGURE 1. “Worst Case” Test Pattern
20098405
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
5
www.national.com
AC Timing Diagrams (Continued)
20098430
FIGURE 3. DS90C383B (Transmitter) LVDS Output Load
20098406
FIGURE 4. DS90C383B (Transmitter) LVDS Transition Times
20098408
FIGURE 5. DS90C383B (Transmitter) Input Clock Transition Time
20098410
FIGURE 6. DS90C383B (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
20098412
FIGURE 7. DS90C383B (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
www.national.com
6
AC Timing Diagrams (Continued)
20098414
FIGURE 8. DS90C383B (Transmitter) Phase Lock Loop Set Time
20098417
FIGURE 9. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs
20098418
FIGURE 10. Transmitter Power Down Delay
7
www.national.com
AC Timing Diagrams (Continued)
20098426
FIGURE 11. Transmitter LVDS Output Pulse Position Measurement
DS90C383B Pin Description—FPD Link Transmitter
Pin Name
I/O
No.
Description
TxIN
I
28
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
TxOUT+
O
O
I
4
4
1
1
1
1
1
TxOUT−
Negative LVDS differential data output.
FPSHIFT IN
R_FB
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
I
TxCLK OUT+
TxCLK OUT−
PWR DOWN
O
O
I
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down. See Applications Information section.
Power supply pins for TTL inputs.
VCC
I
I
I
I
I
I
3
5
1
2
1
3
GND
Ground pins for TTL inputs.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
www.national.com
8
data is stopped and reapplied, such as changing video mode
within Graphics Controller, it is not necessary to cycle the PD
signal. However, there are in certain cases where the PD
may need to be asserted during these mode changes. In
cases where the source (Graphics Source) may be supply-
ing an unstable clock or spurious noisy clock output to the
LVDS transmitter, the LVDS Transmitter may attempt to lock
onto this unstable clock signal but is unable to do so due the
instability or quality of the clock source. The PD signal in
these cases should then be asserted once a stable clock is
applied to the LVDS transmitter. Asserting the PWR DOWN
pin will effectively place the device in reset and disable the
PLL, enabling the LVDS Transmitter into a power saving
standby mode. However, it is still generally a good practice
to assert the PWR DOWN pin or reset the LVDS transmitter
whenever the clock/data is stopped and reapplied but it is
not mandatory for the DS90C383B.
Applications Information
The DS90C383B are backward compatible with the
DS90C383/DS90CF383, DS90C383A/DS90CF383A and
are a pin-for-pin replacement.
This device may also be used as a replacement for the
DS90CF583 (5V, 65MHz) and DS90CF581 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL VCC of the transmitter.
2. The DS90C383B transmitter input and control inputs
accept 3.3V LVTTL/LVCMOS levels. They are not 5V
tolerant.
3. To implement a falling edge device for the DS90C383B,
the R_FB pin (pin 17) may be tied to ground OR left
unconnected (an internal pull-down resistor biases this
pin low). Biasing this pin to Vcc implements a rising edge
device.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90C383B can support Spread Spectrum Clocking
signal type inputs. The DS90C383B outputs will accurately
track Spread Spectrum Clock/Data inputs with modulation
frequencies of up to 100kHz (max.)with either center spread
of 2.5% or down spread -5% deviations.
TRANSMITTER INPUT PINS
The TxIN and control input pins are compatible with LVC-
MOS and LVTTL levels. These pins are not 5V tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
POWER SOURCES SEQUENCE
The DS90C383B does not require any special requirement
for sequencing of the input clock/data and PD (PowerDown)
signal. The DS90C383B offers a more robust input sequenc-
ing feature where the input clock/data can be inserted after
the release of the PD signal. In the case where the clock/
In typical applications, it is recommended to have VCC, LVDS
VCC and PLL VCC from the same power source with three
separate de-coupling bypass capacitor groups. There is no
requirement on which VCC entering the device first.
9
www.national.com
Pin Diagram
DS90C383B
20098423
Typical Application
20098403
TABLE 1. Programmable Transmitter (DS90C383B)
Pin
Condition
R_FB = VCC
R_FB = GND or NC
Strobe Status
Rising edge strobe
Falling edge strobe
R_FB
R_FB
www.national.com
10
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90C383BMT
NS Package Number MTD56
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances
and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:
www.national.com/quality/green.
Lead free products are RoHS compliant.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
相关型号：
DS90C383MTD
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
NSC
DS90C383MTDX
IC QUAD LINE DRIVER, PDSO56, LOW PROFILE, PLASTIC, TSSOP-56, Line Driver or Receiver
NSC
DS90C383MTDX/NOPB
IC QUAD LINE DRIVER, PDSO56, LOW PROFILE, PLASTIC, TSSOP-56, Line Driver or Receiver
NSC
©2020 ICPDF网 联系我们和版权申明