DS90C401 [NSC]

Dual Low Voltage Differential Signaling (LVDS) Driver; 双通道低电压差分信号( LVDS )驱动器
DS90C401
型号: DS90C401
厂家: National Semiconductor    National Semiconductor
描述:

Dual Low Voltage Differential Signaling (LVDS) Driver
双通道低电压差分信号( LVDS )驱动器

驱动器
文件: 总11页 (文件大小:648K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
August 2005  
DS90C401  
Dual Low Voltage Differential Signaling (LVDS) Driver  
General Description  
Features  
n Ultra low power dissipation  
n Operates above 155.5 Mbps  
n Standard TIA/EIA-644  
The DS90C401 is a dual driver device optimized for high  
data rate and low power applications. This device along with  
the DS90C402 provides a pair chip solution for a dual high  
speed point-to-point interface. The DS90C401 is a current  
mode driver allowing power dissipation to remain low even at  
high frequency. In addition, the short circuit fault current is  
also minimized. The device is in a 8 lead small outline  
package. The differential driver outputs provides low EMI  
with its low output swings typically 340 mV.  
n 8 Lead SOIC Package saves space  
n Low Differential Output Swing typical 340 mV  
Connection Diagram  
10001301  
Order Number DS90C401M  
See NS Package Number M08A  
Functional Diagram  
10001302  
© 2005 National Semiconductor Corporation  
DS100013  
www.national.com  
Absolute Maximum Ratings (Note 1)  
Maximum Junction  
Temperature  
+150˚C  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
ESD Rating  
(HBM, 1.5 k, 100 pF)  
(EIAJ, 0 , 200 pF)  
3,500V  
250V  
Supply Voltage (VCC  
Input Voltage (DIN  
)
−0.3V to +6V  
−0.3V to (VCC + 0.3V)  
−0.3V to (VCC + 0.3V)  
)
Output Voltage (DOUT+, DOUT−  
)
Recommended Operating  
Conditions  
Short Circuit Duration  
(DOUT+, DOUT−  
)
Continuous  
Min  
Typ  
Max  
Units  
@
Maximum Package Power Dissipation +25˚C  
M Package  
Supply Voltage (VCC  
Operating Free Air  
Temperature (TA)  
)
+4.5  
+5.0  
+5.5  
V
1068 mW  
Derate M Package  
8.5 mW/˚C above +25˚C  
−65˚C to +150˚C  
−40  
+25  
+85  
˚C  
Storage Temperature Range  
Lead Temperature Range  
Soldering (4 sec.)  
+260˚C  
Electrical Characteristics  
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 3)  
Symbol  
VOD1  
Parameter  
Differential Output Voltage  
Change in Magnitude of VOD1 for  
Complementary Output States  
Offset Voltage  
Conditions  
Pin  
Min  
Typ  
340  
4
Max  
450  
35  
Units  
mV  
RL = 100(Figure 1)  
DOUT−  
,
250  
DOUT+  
VOD1  
|mV|  
VOS  
1.125  
1.25  
5
1.375  
25  
V
VOS  
Change in Magnitude of VOS for  
Complementary Output States  
Output Voltage High  
|mV|  
VOH  
VOL  
IOS  
VIH  
VIL  
II  
RL = 100Ω  
1.41  
1.07  
−3.5  
1.60  
V
V
Output Voltage Low  
0.90  
Output Short Circuit Current  
Input Voltage High  
VOUT = 0V (Note 8)  
−5.0  
VCC  
0.8  
mA  
V
DIN  
2.0  
GND  
−10  
Input Voltage Low  
V
Input Current  
VIN = VCC, GND, 2.5V or 0.4V  
ICL = −18 mA  
1
−0.8  
1.7  
3.5  
8
+10  
µA  
V
VCL  
ICC  
Input Clamp Voltage  
−1.5  
No Load Supply Current  
DIN = VCC or GND  
VCC  
3.0  
5.5  
mA  
mA  
mA  
DIN = 2.5V or 0.4V  
ICCL  
Loaded Supply Current  
RL = 100All Channels  
VIN = VCC or GND (all inputs)  
14.0  
Switching Characteristics  
VCC = +5.0V 10%, TA = −40˚C to +85˚C (Notes 3, 4, 5, 6, 9)  
Symbol  
tPHLD  
tPLHD  
tSKD  
Parameter  
Conditions  
Min  
Typ  
Max  
3.5  
3.5  
900  
1.0  
3.0  
2.0  
2.0  
Units  
ns  
Differential Propagation Delay High to Low  
Differential Propagation Delay Low to High  
RL = 100, CL = 5 pF  
(Figure 2 and Figure 3)  
0.5  
0.5  
0
2.0  
2.1  
80  
ns  
Differential Skew |tPHLD – tPLHD  
|
ps  
tSK1  
Channel-to-Channel Skew (Note 4)  
Chip to Chip Skew (Note 5)  
Rise Time  
0
0.3  
ns  
tSK2  
ns  
tTLH  
0.35  
0.35  
ns  
tTHL  
Fall Time  
ns  
www.national.com  
2
Parameter Measurement Information  
10001304  
FIGURE 1. Driver VOD and VOS Test Circuit  
10001305  
FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit  
10001306  
FIGURE 3. Driver Propagation Delay and Transition Time Waveforms  
Typical Application  
10001309  
FIGURE 4. Point-to-Point Application  
3
www.national.com  
current mode requires (as discussed above) that a resistive  
termination be employed to terminate the signal and to com-  
plete the loop as shown in Figure 4. AC or unterminated  
configurations are not allowed. The 3.4 mA loop current will  
develop a differential voltage of 340 mV across the 100Ω  
termination resistor which the receiver detects with a 240 mV  
minimum differential noise margin neglecting resistive line  
losses (driven signal minus receiver threshold (340 mV –  
100 mV = 240 mV)). The signal is centered around +1.2V  
(Driver Offset, VOS) with respect to ground as shown in  
Figure 5. Note that the steady-state voltage (VSS) peak-to-  
peak swing is twice the differential voltage (VOD) and is  
typically 680 mV.  
Applications Information  
LVDS drivers and receivers are intended to be primarily used  
in an uncomplicated point-to-point configuration as is shown  
in Figure 4. This configuration provides a clean signaling  
environment for the quick edge rates of the drivers. The  
receiver is connected to the driver through a balanced media  
which may be a standard twisted pair cable, a parallel pair  
cable, or simply PCB traces. Typically, the characteristic  
impedance of the media is in the range of 100. A termina-  
tion resistor of 100should be selected to match the media,  
and is located as close to the receiver input pins as possible.  
The termination resistor converts the current sourced by the  
driver into a voltage that is detected by the receiver. Other  
configurations are possible such as a multi-receiver configu-  
ration, but the effects of a mid-stream connector(s), cable  
stub(s), and other impedance discontinuities as well as  
ground shifting, noise margin limits, and total termination  
loading must be taken into account.  
The current mode driver provides substantial benefits over  
voltage mode drivers, such as an RS-422 driver. Its quies-  
cent current remains relatively flat versus switching fre-  
quency. Whereas the RS-422 voltage mode driver increases  
exponentially in most case between 20 MHz–50 MHz. This  
is due to the overlap current that flows between the rails of  
the device when the internal gates switch. Whereas the  
current mode driver switches a fixed current between its  
output without any substantial overlap current. This is similar  
to some ECL and PECL devices, but without the heavy static  
ICC requirements of the ECL/PECL designs. LVDS requires  
The DS90C401 differential line driver is a balanced current  
source design. A current mode driver, generally speaking  
has a high output impedance and supplies a constant cur-  
rent for a range of loads (a voltage mode driver on the other  
hand supplies a constant voltage for a range of loads).  
Current is switched through the load in one direction to  
produce a logic state and in the other direction to produce  
the other logic state. The typical output current is mere 3.4  
mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The  
>
80% less current than similar PECL devices. AC specifi-  
cations for the driver are a tenfold improvement over other  
existing RS-422 drivers.  
10001310  
FIGURE 5. Driver Output Levels  
www.national.com  
4
Note 3: All typicals are given for: V  
= +5.0V, T = +25˚C.  
A
CC  
Pin Descriptions  
Note 4: Channel-to-Channel Skew is defined as the difference between the  
propagation delay of the channel and the other channels in the same chip  
with an event on the inputs.  
TABLE 1. Device Pin Descriptions  
Note 5: Chip to Chip Skew is defined as the difference between the mini-  
mum and maximum specified differential propagation delays.  
Pin No.  
4, 8  
3, 7  
2, 6  
5
Name  
Description  
Note 6: Generator waveform for all tests unless otherwise specified: f = 1  
MHz, Z = 50, t 6 ns, and t 6 ns.  
DIN  
TTL/CMOS driver input pins  
O
r
f
DOUT+ Non-inverting driver output pin  
DOUT− Inverting driver output pin  
GND Ground pin  
Note 7: ESD Ratings:  
HBM (1.5 k, 100 pF) 3,500V  
EIAJ (0, 200 pF) 250V  
Note 8: Output short circuit current (I ) is specified as magnitude only,  
OS  
1
VCC  
Positive power supply pin,  
+5.0V 10%  
minus sign indicates direction only.  
Note 9: C includes probe and jig capacitance.  
L
Truth Table  
Ordering Information  
DIN  
L
DOUT+  
DOUT−  
Operating  
Temperature  
−40˚C to +85˚C  
Package Type/  
Number  
Order Number  
L
H
X
H
L
H
SOP/M08A  
DS90C401M  
>
DIN 0.8V and  
X
Note 1: “Absolute Maximum Ratings” are those values beyond which the  
safety of the device cannot be guaranteed. They are not meant to imply that  
the devices should be operated at these limits. The table of “Electrical  
Characteristics” specifies conditions of device operation.  
<
DIN 2.0V  
H = Logic high level  
L = Logic low level  
X = Indeterminant state  
Note 2: Current into device pins is defined as positive. Current out of device  
pins is defined as negative. All voltages are referenced to ground except:  
V
and V  
.
OD1  
OD1  
Typical Performance Characteristics  
Power Supply Current  
vs Power Supply Voltage  
Power Supply Current  
vs Temperature  
10001311  
10001312  
5
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Typical Performance Characteristics (Continued)  
Power Supply Current  
vs Power Supply Voltage  
Power Supply Current  
vs Temperature  
10001313  
10001314  
Output Short Circuit Current  
vs Power Supply Voltage  
Differential Output Voltage  
vs Power Supply Voltage  
10001317  
10001316  
www.national.com  
6
Typical Performance Characteristics (Continued)  
Differential Output Voltage  
vs Ambient Temperature  
Output Voltage High vs  
Power Supply Voltage  
10001318  
10001319  
Output Voltage High vs  
Ambient Temperature  
Output Voltage Low vs  
Power Supply Voltage  
10001320  
10001321  
7
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Typical Performance Characteristics (Continued)  
Output Voltage Low vs  
Ambient Temperature  
Offset Voltage vs  
Power Supply Voltage  
10001322  
10001323  
Offset Voltage vs  
Ambient Temperature  
Power Supply Current  
vs Frequency  
10001324  
10001325  
www.national.com  
8
Typical Performance Characteristics (Continued)  
Differential Output Voltage  
vs Load Resistor  
Differential Propagation Delay  
vs Power Supply Voltage  
10001327  
10001328  
Differential Propagation Delay  
vs Ambient Temperature  
Differential Skew vs  
Power Supply Voltage  
10001330  
10001329  
9
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Typical Performance Characteristics (Continued)  
Differential Skew vs  
Ambient Temperature  
Differential Transition Time  
vs Power Supply Voltage  
10001331  
10001332  
Differential Transition Time  
vs Ambient Temperature  
10001333  
www.national.com  
10  
Physical Dimensions inches (millimeters) unless otherwise noted  
8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC  
Order Number DS90C401M  
NS Package Number M08A  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves  
the right at any time without notice to change said circuitry and specifications.  
For the most current product information visit us at www.national.com.  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS  
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR  
CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body, or  
(b) support or sustain life, and whose failure to perform when  
properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to result  
in a significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be reasonably  
expected to cause the failure of the life support device or  
system, or to affect its safety or effectiveness.  
BANNED SUBSTANCE COMPLIANCE  
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no ‘‘Banned Substances’’ as defined in CSP-9-111S2.  
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