DS90CF384 [NSC]
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz; + 3.3V可编程LVDS发射器24位平板显示器（ FPD ）链路65兆赫， + 3.3V LVDS接收器24位平板显示器（ FPD ）链路65兆赫
| 型号： | DS90CF384 |
| 厂家： | 
National Semiconductor |
| 描述： | +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz |
| 文件： | 总20页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2000
DS90C383/DS90CF384
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link—65 MHz, +3.3V LVDS Receiver
24-Bit Flat Panel Display (FPD) Link—65 MHz
General Description
Features
n 20 to 65 MHz shift clock support
n Programmable transmitter (DS90C383) strobe select
(Rising or Falling edge strobe)
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams. A phase-locked transmit clock is transmit-
ted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CF384 receiver con-
verts the LVDS data streams back into 28 bits of LVCMOS/
LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits
of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughputs is 227 Mbytes/sec. The transmitter is of-
fered with programmable edge data strobes for convenient
interface with a variety of graphics controllers. The transmit-
ter can be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge trans-
n Single 3.3V supply
n Chipset (Tx + Rx) power consumption 250 mW (typ)
n Power-down mode ( 0.5 mW total)
<
<
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 227 Megabytes/sec bandwidth
n Up to 1.8 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package.
n Also available in a 64 ball, 0.8mm fine pitch ball grid
array (FBGA) package
mitter will inter-operate with
a Falling edge receiver
(DS90CF384) without any translation logic. Both devices are
also offered in a 64 ball, 0.8mm fine pitch ball grid array
(FBGA) package which provides a 44 % reduction in PCB
footprint compared to the TSSOP package.
n Falling edge data strobe Receiver
n Compatible with TIA/EIA-644 LVDS standard
>
n ESD rating 7 kV
n Operating Temperature: −40˚C to +85˚C
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagrams
Typical Application
DS012887-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS012887
www.national.com
Block Diagrams (Continued)
DS90C383
DS012887-1
Order Number DS90C383MTD or DS90C383SLC
See NS Package Number MTD56 or SLC64A
DS90CF384
DS012887-24
Order Number DS90CF384MTD or DS90CF384SLC
See NS Package Number MTD56 or SLC64A
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DS90CF384MTD
12.4 mW/˚C above +25˚C
Maximum Package Power Dissipation Capacity 25˚C
SLC64A Package:
DS90C383SLC
2.0 W
2.0 W
DS90CF384SLC
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
Package Derating:
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
DS90C383SLC
DS90CF384SLC
10.2 mW/˚C above +25˚C
10.2 mW/˚C above +25˚C
ESD Rating
LVDS Output Short Circuit
Duration
>
(HBM, 1.5 kΩ, 100 pF)
7 kV
Continuous
+150˚C
Junction Temperature
Storage Temperature
Recommended Operating
Conditions
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec for TSSOP)
+260˚C
Min Nom Max
Units
Solder Reflow Temperature
(20 sec for FBGA)
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
)
3.0
3.3
3.6
V
+220˚C
Maximum Package Power Dissipation Capacity 25˚C
MTD56 (TSSOP) Package:
DS90C383MTD
−40
0
+25
+85
2.4
˚C
V
Receiver Input Range
1.63 W
1.61 W
Supply Noise Voltage (VCC
)
100
mVPP
DS90CF384MTD
Package Derating:
DS90C383MTD
12.5 mW/˚C above +25˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions
LVCMOS/LVTTL DC SPECIFICATIONS
Min
Typ
Max
Units
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VCL
IIN
IOH = −0.4 mA
IOL = 2 mA
3.3
0.06
V
0.3
V
ICL = −18 mA
−0.79
−1.5
V
±
±
10
Input Current
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
5.1
µA
mA
IOS
Output Short Circuit Current
−60
−120
LVDS DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
250
345
450
35
mV
mV
∆VOD
Change in VOD between
complimentary output states
Offset Voltage (Note 4)
VOS
1.125
1.25
−3.5
1.375
35
V
∆VOS
Change in VOS between
complimentary output states
Output Short Circuit Current
Output TRI-STATE® Current
mV
IOS
IOZ
VOUT = 0V, RL = 100Ω
Power Down = 0V,
VOUT = 0V or VCC
VCM = +1.2V
−5
mA
µA
±
±
10
1
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
+100
mV
mV
µA
−100
±
±
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
10
10
µA
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current
RL = 100Ω,
CL = 5 pF,
f = 32.5 MHz
f = 37.5 MHz
31
32
45
50
mA
mA
Worst Case
Worst Case Pattern
3
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TRANSMITTER SUPPLY CURRENT
(Figures 1, 3 ), TA
−40˚C to +85˚C
=
f = 65 MHz
42
23
55
35
mA
mA
ICCTG Transmitter Supply Current
16 Grayscale
RL = 100Ω,
f = 32.5 MHz
CL = 5 pF,
16 Grayscale Pattern
f = 37.5 MHz
f = 65 MHz
28
31
40
45
mA
mA
(Figures 2, 3 ), TA
−40˚C to +85˚C
=
ICCTZ
Transmitter Supply Current
Power Down
Power Down = Low
Driver Outputs in TRI-STATE® under
10
55
µA
Power Down Mode
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current
Worst Case
C
= 8 pF,
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
49
53
78
65
70
mA
mA
mA
L
Worst Case Pattern
(Figures 1, 4 ), TA
−40˚C to +85˚C
=
105
ICCRG Receiver Supply Current,
16 Grayscale
C
= 8 pF,
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
28
30
43
45
47
60
mA
mA
mA
L
16 Grayscale Pattern
(Figures 2, 4 ), TA
−40˚C to +85˚C
=
ICCRZ Receiver Supply Current
Power Down
Power Down = Low
10
55
µA
Receiver Outputs Stay Low during
Power Down Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25C.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V and ∆V ).
OD
OD
Note 4:
V
previously referred as V
.
CM
OS
Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 3 )
LVDS High-to-Low Transition Time (Figure 3 )
TxCLK IN Transition Time (Figure 5 )
Min
Typ
0.75
0.75
Max Units
1.5
1.5
5
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TxOUT Channel-to-Channel Skew (Figure 6 )
Transmitter Output Pulse Position for Bit 0 (Figure 17 )
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 7)
250
0
f = 65 MHz
−0.4
1.8
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
2.2
4.4
6.6
8.8
11
4.0
6.2
8.4
10.6
12.8
15
13.2
T
TCIH
TxCLK IN High Time (Figure 7)
0.35T
0.35T
2.5
0.5T 0.65T
0.5T 0.65T
TCIL
TxCLK IN Low Time (Figure 7)
TSTC
TxIN Setup to TxCLK IN (Figure 7 )
f = 65 MHz
THTC
TxIN Hold to TxCLK IN (Figure 7 )
0
TCCD
TxCLK IN to TxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 9 )
3.0
3.7
5.5
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4
Transmitter Switching Characteristics (Continued)
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
TPLLS
TPDD
Parameter
Transmitter Phase Lock Loop Set (Figure 11 )
Transmitter Power Down Delay (Figure 15 )
Min
Typ
Max Units
10
ms
ns
100
Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CMOS/TTL High-to-Low Transition Time (Figure 4 )
Receiver Input Strobe Position for Bit 0 (Figure 18 )
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure 19 )
RxCLK OUT Period (Figure 8)
Min
Typ
2.2
Max Units
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
µs
CHLT
2.2
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
f = 65 MHz
0.7
2.9
1.1
1.4
3.3
3.6
5.1
5.5
5.8
7.3
7.7
8.0
9.5
9.9
10.2
12.4
14.6
11.7
13.9
400
15
12.1
14.3
f = 65 MHz
f = 65 MHz
RCOP
T
50
RCOH
RCOL
RxCLK OUT High Time (Figure 8 )
7.3
8.6
4.9
6.9
5.7
7.1
RxCLK OUT Low Time (Figure 8)
3.45
2.5
RSRC
RxOUT Setup to RxCLK OUT (Figure 8 )
RxOUT Hold to RxCLK OUT (Figure 8 )
RxCLK IN to RxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 10 )
Receiver Phase Lock Loop Set (Figure 12 )
Receiver Power Down Delay (Figure 16 )
RHRC
2.5
RCCD
5.0
9.0
10
1
RPLLS
RPDD
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
AC Timing Diagrams
DS012887-3
FIGURE 1. “Worst Case” Test Pattern
5
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AC Timing Diagrams (Continued)
DS012887-4
FIGURE 2. “16 Grayscale” Test Pattern (Notes 6, 7, 8, 9)
Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 8: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 9: Recommended pin to signal mapping. Customer may choose to define differently.
DS012887-5
FIGURE 3. DS90C383 (Transmitter) LVDS Output Load and Transition Times
DS012887-6
FIGURE 4. DS90CF384 (Receiver) CMOS/TTL Output Load and Transition Times
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6
AC Timing Diagrams (Continued)
DS012887-7
FIGURE 5. DS90C383 (Transmitter) Input Clock Transition Time
DS012887-8
Measurements at V = 0V
diff
TCCS measured between earliest and latest LVDS edges.
TxCLK Differential Low V High Edge
FIGURE 6. DS90C383 (Transmitter) Channel-to-Channel Skew
DS012887-9
FIGURE 7. DS90C383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
DS012887-10
FIGURE 8. DS90CF384 (Receiver) Setup/Hold and High/Low Times
7
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AC Timing Diagrams (Continued)
DS012887-11
FIGURE 9. DS90C383 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
DS012887-12
FIGURE 10. DS90CF384 (Receiver) Clock In to Clock Out Delay
DS012887-13
FIGURE 11. DS90C383 (Transmitter) Phase Lock Loop Set Time
DS012887-14
FIGURE 12. DS90CF384 (Receiver) Phase Lock Loop Set Time
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8
AC Timing Diagrams (Continued)
DS012887-15
FIGURE 13. Seven Bits of LVDS in Once Clock Cycle
DS012887-16
FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
DS012887-17
FIGURE 15. Transmitter Power Down Delay
9
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AC Timing Diagrams (Continued)
DS012887-18
FIGURE 16. Receiver Power Down Delay
DS012887-26
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
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10
AC Timing Diagrams (Continued)
DS012887-25
FIGURE 18. Receiver LVDS Input Strobe Position
11
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AC Timing Diagrams (Continued)
DS012887-21
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHZ
Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 19. Receiver LVDS Input Skew Margin
Applications Information
The DS90C383 and DS90CF384 are backward compatible
with the existing 5V FPD Link transmitter/receiver pair
(DS90CR583, DS90CR584, DS90CF583 and DS90CF584).
To upgrade from a 5V to a 3.3V system the following must be
addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL VCC of both the transmitter
and receiver devices. This change may enable the re-
moval of a 5V supply from the system, and power may
be supplied from an existing 3V power source.
2. The DS90C383 (transmitter) incorporates a rise/fall
strobe select pin. This select function is on pin 17,
formerly a VCC connection on the 5V products. When the
rise/fall strobe select pin is connected to VCC, the part is
configured with a rising edge strobe. In a system cur-
rently using
a 5V rising edge strobe transmitter
(DS90CR583), no layout changes are required to ac-
commodate the new rise/fall select pin on the 3.3V
transmitter. The VCC signal may remain at pin 17, and
the device will be configured with a rising edge strobe.
When converting from a 5V falling edge transmitter
(DS90CF583) to the 3V transmitter a minimal board
layout change is necessary. The 3.3V transmitter will
not be configured with a falling edge strobe if VCC re-
mains connected to the select pin. To guarantee the
3.3V transmitter functions with a falling edge strobe pin
17 should be connected to ground OR left unconnected.
When not connected (left open) and internal pull-down
resistor ties pin 17 to ground, thus configuring the trans-
mitter with a falling edge strobe.
3. The DS90C383 transmitter input and control inputs ac-
cept 3.3V TTL/CMOS levels. They are not 5V tolerant.
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12
DS90C383 TSSOP Package Pin Description — FPD Link Transmitter
Pin Name
TxIN
I/O No.
Description
I
28
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+
O
O
I
4
4
1
1
1
1
1
Positive LVDS differentiaI data output.
TxOUT−
Negative LVDS differential data output.
FPSHIFT IN
R_FB
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Programmable strobe select.
I
RTxCLK OUT+
TxCLK OUT−
PWR DOWN
O
O
I
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
VCC
I
I
I
I
I
I
3
4
1
2
1
3
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
DS90C383SLC SLC64A (FBGA) Package Pin Summary — FPD Link
Transmitter
Pin Name
TxIN
I/O
I
No.
28
4
Description
TTL level input.
TxOUT+
O
O
I
Positive LVDS differential data output.
Negative LVDS differential data output.
TxOUT−
4
TxCLKIN
1
TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
TxCLK OUT+
TxCLK OUT−
PWR DWN
O
O
I
1
1
Negative LVDS differential clock output.
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
R_FB
I
I
I
I
I
I
I
1
3
5
1
2
2
4
6
Programmable strobe select. HIGH = rising edge, LOW = falling edge.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
NC
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Pins not connected.
DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link
Transmitter
By Pin
Pin Name
TxIN27
By Pin Type
Pin Name
GND
Pin
A1
A2
A3
A4
A5
A6
Type
Pin
D3
E4
E8
G1
G6
B3
Type
G
I
TxOUT0-
O
O
P
P
O
GND
G
TxOUT0+
LVDS VCC
LVDS VCC
TxCLKOUT-
GND
G
GND
G
GND
G
LVDS GND
G
13
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DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link
Transmitter (Continued)
By Pin
TxCLKOUT+
TxOUT3+
TxIN1
By Pin Type
LVDS GND
LVDS GND
LVDS GND
PLL GND
PLL GND
PWR DWN
R_FB
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D4
D5
D6
D7
D8
E1
E2
E3
E4
E5
E6
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
O
O
I
B4
B7
D5
C6
D6
D7
G5
C8
B2
B1
D2
C1
D1
F1
E2
E3
G2
H1
G3
H3
F4
G4
H4
H5
E5
F5
H6
H7
H8
G7
F7
G8
E7
F8
D8
A1
A6
A7
A2
A3
C4
D4
B5
C5
B6
A8
A4
A5
G
G
G
G
G
I
TxIN0
I
LVDS GND
LVDS GND
TxOUT2-
TxOUT3-
LVDS GND
NC
G
G
O
O
G
I
TxCLKIN
TxIN0
I
I
TxIN1
I
TxIN3
I
TxIN2
I
NC
TxIN3
I
NC
TxIN4
I
TxOUT1-
TxOUT2+
PLL GND
PLL VCC
TxCLKIN
TxIN4
O
O
G
P
I
TxIN5
I
TxIN6
I
TxIN7
I
TxIN8
I
TxIN9
I
I
TxIN10
I
TxIN2
I
TxIN11
I
GND
G
O
G
G
I
TxIN12
I
TxOUT1+
LVDS GND
PLL GND
PWD DWN
TxIN26
VCC
TxIN13
I
TxIN14
I
TxIN15
I
TxIN16
I
I
TxIN17
I
P
I
TxIN18
I
TxIN6
TxIN19
I
TxIN7
I
TxIN20
I
GND
G
I
TxIN21
I
TxIN16
VCC
TxIN22
I
P
I
TxIN23
I
TxIN24
GND
TxIN24
I
G
I
TxIN25
I
TxIN5
TxIN26
I
NC
TxIN27
I
NC
TxCLKOUT-
TxCLKOUT+
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
TxOUT2-
TxOUT2+
TxOUT3-
TxOUT3+
LVDS VCC
LVDS VCC
O
O
O
O
O
O
O
O
O
O
P
P
TxIN12
TxIN17
NC
I
I
TxIN22
TxIN25
GND
I
I
G
I
TxIN8
TxIN10
TxIN13
R_FB
I
I
I
GND
G
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14
DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link
Transmitter (Continued)
By Pin
TxIN21
TxIN23
TxIN9
By Pin Type
PLL VCC
VCC
VCC
VCC
NC
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
I
I
C7
E1
E6
H2
B8
C2
C3
F2
F3
F6
P
P
P
P
I
VCC
P
I
TxIN11
TxIN14
TxIN15
TxIN18
TxIN19
TxIN20
I
NC
I
NC
I
NC
I
NC
I
NC
G : Ground
I : Input
O : Output
P : Power
NC : No Connect
DS90CF384 MTD56 TSSOP Package Pin Description — FPD Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
4
4
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
28
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
O
I
I
GND
I
Ground pins for TTL outputs.
PLL VCC
I
Power supply for PLL.
PLL GND
LVDS VCC
LVDS GND
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
DS90CF384 64 ball FBGA Package Pin Description — FPD Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
4
4
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
28
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
2
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
O
I
I
GND
I
Ground pins for TTL outputs.
PLL VCC
I
Power supply for PLL.
PLL GND
LVDS VCC
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
15
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DS90CF384 64 ball FBGA Package Pin Description — FPD Link Receiver
(Continued)
Pin Name
LVDS GND
NC
I/O No.
Description
I
4
6
Ground pins for LVDS inputs.
Pins not connected.
DS90CF384 64 ball, FBGA Package Pin Definition — FPD Link Receiver
By Pin
Pin Name
RxOUT17
VCC
By Pin Type
Pin Name
GND
Pin
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D4
D5
D6
D7
D8
E1
E2
E3
E4
E5
E6
E7
E8
F1
Type
O
Pin
A4
B1
B6
D8
E3
E5
G3
G7
H5
F6
G8
E6
H6
H7
H2
H3
F4
G4
G5
F5
G6
H8
E7
E8
C8
D7
B8
C6
B7
A8
A7
A6
C5
D5
B4
A5
D4
C4
A3
B3
A1
Type
G
G
G
G
G
G
G
G
G
G
G
I
P
GND
RxOUT15
GND
O
GND
G
GND
RxOUT12
RxOUT8
RxOUT7
RxOUT6
GND
O
GND
O
LVDS GND
LVDS GND
LVDS GND
LVDS GND
PLL GND
PLL GND
PWR DWN
RxCLKIN-
RxCLKIN+
RxIN0-
O
O
G
NC
RxOUT16
RxOUT11
VCC
O
O
P
I
GND
G
O
O
O
I
RxOUT5
RxOUT3
RxOUT21
NC
I
RxIN0+
I
RxIN1-
I
RxIN1+
I
RxOUT18
RxOUT14
RxOUT9
RxOUT4
NC
O
O
O
O
RxIN2-
I
RxIN2+
I
RxIN3-
I
RxIN3+
I
RxCLKOUT
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT10
RxOUT11
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT16
RxOUT17
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
RxOUT1
VCC
O
P
O
O
O
O
P
O
G
O
O
G
P
G
I
RxOUT20
RxOUT19
RxOUT13
RxOUT10
VCC
RxOUT2
GND
RxOUT22
RxOUT24
GND
LVDS VCC
LVDS GND
PWR DWN
RxCLKOUT
RxOUT0
RxOUT23
O
O
O
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16
DS90CF384 64 ball, FBGA Package Pin Definition — FPD Link Receiver
(Continued)
By Pin
RxOUT26
NC
By Pin Type
RxOUT18
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT23
RxOUT24
RxOUT25
RxOUT26
RxOUT27
LVDS VCC
LVDS VCC
PLL VCC
VCC
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
O
C3
D3
D2
C1
E1
F1
E2
G1
F2
H1
E4
H4
F7
A2
B5
D1
D6
B2
C2
C7
F3
F8
G2
O
O
O
O
O
O
O
O
O
O
P
P
P
P
P
P
P
RxIN1-
I
I
RxIN2+
PLL GND
PLL VCC
NC
G
P
RxOUT25
NC
O
LVDS GND
RxIN1+
G
I
RxIN2-
I
RxIN3-
I
LVDS GND
PLL GND
RxOUT27
RxIN0-
G
G
O
I
VCC
VCC
VCC
RxIN0+
I
NC
LVDS VCC
LVDS GND
RxCLKIN-
RxCLKIN+
RxIN3+
P
G
I
NC
NC
NC
I
NC
I
NC
G : Ground
I : Input
O : Output
P : Power
NC : Not Connect
17
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Pin Diagrams for TSSOP Packages
DS90C383MTD
DS90CF384MTD
DS012887-22
DS012887-23
TABLE 1. Programmable Transmitter
Condition Strobe Status
R_FB = VCC
R_FB = GND
Pin
R_FB
R_FB
Rising edge strobe
Falling edge strobe
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18
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Dimensions show in millimeters
Order Number DS90C383MTD, DS90CF384MTD
NS Package Number MTD56
19
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
64 ball, 0.8mm fine pitch ball grid array (FBGA) Package
Dimensions show in millimeters only
Order Number DS90CF384SLC or DS90C383SLC
NS Package Number SLC64A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
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English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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