DS90LV028 [NSC]
3V LVDS Dual CMOS Differential Line Receiver; 3V LVDS双CMOS差动线路接收器
| 型号： | DS90LV028 |
| 厂家： | 
National Semiconductor |
| 描述： | 3V LVDS Dual CMOS Differential Line Receiver |
| 文件： | 总10页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1998
DS90LV028A
3V LVDS Dual CMOS Differential Line Receiver
General Description
Features
>
n
400 Mbps (200 MHz) switching rates
The DS90LV028A is a dual CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion, low noise and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
n 50 ps differential skew (typical)
n 0.1 ns channel-to-channel skew (typical)
n 2.5 ns maximum propagation delay
n 3.3V power supply design
The DS90LV028A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS out-
put levels. The receiver also supports open, shorted and ter-
minated (100Ω) input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV028A has a
flow-through design for easy PCB layout.
n Flow-through pinout
n Power down high impedance on LVDS inputs
n Low Power design (18mW 3.3V static)
n Interoperable with existing 5V LVDS networks
n Accepts small swing (350 mV typical) differential signal
levels
n Supports open, short and terminated input fail-safe
n Conforms to ANSI/TIA/EIA-644 Standard
n Industrial temperature operating range
(−40˚C to +85˚C)
@
The DS90LV028A and companion LVDS line driver provide a
new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.
n Available in SOIC package
Connection Diagram
Functional Diagram
Dual-in-Line
DS100077-1
Order Number DS90LV028ATM
See NS Package Number M08A
DS100077-2
Truth Table
INPUTS
[RIN+] − [RIN−]
VID ≥ 0.1V
OUTPUT
ROUT
H
L
VID ≤ −0.1V
Full Fail-safe
OPEN/SHORT
or Terminated
H
© 1998 National Semiconductor Corporation
DS100077
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Maximum Junction Temperature
ESD Rating (Note 4)
+150˚C
(HBM 1.5 kΩ, 100 pF)
(EIAJ 0Ω, 200 pF)
≥ 7 kV
≥ 500 V
Supply Voltage (VCC
Input Voltage (RIN+, RIN−)
Output Voltage (ROUT
)
−0.3V to +4V
−0.3V to +3.9V
Recommended Operating
Conditions
)
−0.3V to VCC + 0.3V
Maximum Package Power Dissipation +25˚C
M Package
Min
+3.0
GND
Typ
Max
+3.6
3.0
Units
1025 mW
Supply Voltage (VCC
)
+3.3
V
V
Derate M Package
8.2 mW/˚C above +25˚C
−65˚C to +150˚C
Receiver Input Voltage
Operating Free Air
Temperature (TA)
Storage Temperature Range
Lead Temperature Range Soldering
(4 sec.)
−40
25
+85
˚C
+260˚C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)
Symbol
VTH
Parameter
Conditions
Pin
Min
Typ
Max
Units
mV
mV
µA
µA
µA
V
Differential Input High Threshold VCM = +1.2V, 0V, 3V (Note 12)
Differential Input Low Threshold
RIN+,
+100
VTL
RIN−
−100
−10
−10
-20
±
±
IIN
Input Current
VIN = +2.8V
VIN = 0V
VCC = 3.6V or 0V
1
1
+10
+10
+20
VIN = +3.6V
VCC = 0V
VOH
Output High Voltage
IOH = −0.4 mA, VID = +200 mV
IOH = −0.4 mA, Inputs terminated
IOH = −0.4 mA, Inputs shorted
IOL = 2 mA, VID = −200 mV
VOUT = 0V (Note 5)
ROUT
2.7
3.1
3.1
2.7
V
2.7
3.1
V
VOL
IOS
VCL
ICC
Output Low Voltage
0.3
0.5
V
Output Short Circuit Current
Input Clamp Voltage
−15
−50
−0.8
5.4
−100
mA
V
ICL = −18 mA
−1.5
No Load Supply Current
Inputs Open
VCC
9
mA
Switching Characteristics
±
VCC = +3.3V 10%, TA = −40˚C to +85˚C (Notes 6, 7)
Symbol
Parameter
Conditions
CL = 15 pF
VID = 200 mV
(Figure 1 and Figure 2)
Min
1.0
1.0
0
Typ
1.6
1.7
50
Max
2.5
Units
ns
tPHLD
tPLHD
tSKD1
tSKD2
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Pulse Skew |tPHLD − tPLHD| (Note 8)
2.5
ns
400
ps
Differential Channel-to-Channel Skew-same device
(Note 9)
0
0.1
0.5
ns
tSKD3
tSKD4
tTLH
Differential Part to Part Skew (Note 10)
Differential Part to Part Skew (Note 11)
Rise Time
0
0
1.0
1.5
ns
ns
325
225
250
800
800
ps
tTHL
Fall Time
ps
fMAX
Maximum Operating Frequency (Note 13)
200
MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise speci-
fied (such as V ).
ID
Note 3: All typicals are given for: V
= +3.3V and T = +25˚C.
A
CC
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 7 kV
EIAJ (0Ω, 200 pF) ≥ 500V
Note 5: Output short circuit current (I ) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not ex-
OS
ceed maximum junction temperature specification.
Note 6:
C includes probe and jig capacitance.
L
Note 7: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z = 50Ω, t and t (0% to 100%) ≤ 3 ns for R
.
IN
O
r
f
Note 8:
t
SKD1
is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
www.national.com
2
Switching Characteristics (Continued)
Note 9:
integrated circuit.
Note 10: , part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V
t
is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the
SKD2
t
S
K
D
3
C
C
and within 5˚C of each other within the operating temperature range.
Note 11: , part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recom-
t
SKD4
mended operating temperature and voltage ranges, and across process distribution. t
is defined as |Max − Min| differential propagation delay.
SKD4
Note 12:
V
is always higher than R + and R − voltage. R + and R − are allowed to have voltage range −0.05V to +3.05V. V is not allowed to be greater
CC IN IN IN IN ID
than 100 mV when V
= 0V or 3V.
CM
=
<
t
f
Note 13:
f
generator input conditions: t
1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle,
(min 2.7V), load 15 pF (stray plus probes).
OH
MAX
r
=
V
(max 0.4V), V
OL
Parameter Measurement Information
DS100077-3
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
DS100077-4
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
Typical Application
Balanced System
DS100077-5
FIGURE 3. Point-to-Point Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN1035, AN977, AN971, AN916, AN805, AN903.
100Ω should be selected to match the media, and is located
as close to the receiver input pins as possible. The termina-
tion resistor converts the driver output (current mode) into a
voltage that is detected by the receiver. Other configurations
are possible such as a multi-receiver configuration, but the
effects of a mid-stream connector(s), cable stub(s), and
other impedance discontinuities as well as ground shifting,
noise margin limits, and total termination loading must be
taken into account.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 3. This configuration provides a clean signaling en-
vironment for the fast edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically the characteristic impedance of
the media is in the range of 100Ω. A termination resistor of
The DS90LV028A differential line receiver is capable of de-
±
tecting signals as low as 100 mV, over a 1V common-mode
range centered around +1.2V. This is related to the driver off-
3
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should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
Applications Information (Continued)
set voltage which is typically +1.2V. The driven signal is cen-
±
tered around this voltage and may shift 1V around this cen-
Termination:
±
ter point. The 1V shifting may be the result of a ground
Use a termination resistor which best matches the differen-
tial impedance or your transmission line. The resistor should
be between 90Ω and 130Ω. Remember that the current
mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor termi-
nation. Typically, connecting a single resistor across the pair
at the receiver end will suffice.
potential difference between the driver’s ground reference
and the receiver’s ground reference, the common-mode ef-
fects of coupled noise, or a combination of the two. The AC
parameters of both receiver input pins are optimized for a
recommended operating input voltage range of 0V to +2.4V
(measured from each pin to ground). The device will operate
for receiver input voltages up to VCC, but exceeding VCC will
turn on the ESD protection circuitry which will clamp the bus
voltages.
Surface mount 1% - 2% resistors are the best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
Power Decoupling Recommendations:
<
the termination resistor and the receiver should be 10mm
(12mm MAX).
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.001µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
Fail-Safe Feature:
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
PC Board considerations:
Use at least 4 PCB board layers (top to bottom): LVDS sig-
nals, ground, power, TTL signals.
1. Open Input Pins. The DS90LV028A is a dual receiver
device, and if an application requires only 1 receiver, the
unused channel inputs should be left OPEN. Do not tie
unused receiver inputs to ground or any other voltages.
The input is biased by internal high value pull up and pull
down resistors to set the output to a HIGH state. This in-
ternal circuitry will guarantee a HIGH, stable output state
for open inputs.
Isolate TTL signals from LVDS signals, otherwise the TTL
signals may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
Differential Traces:
2. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a power-off condition,
the receiver output will again be in a HIGH state, even
with the end of cable 100Ω termination resistor across
the input pins. The unplugged cable can become a float-
ing antenna which can pick up noise. If the cable picks
up more than 10mV of differential noise, the receiver
may see the noise as a valid signal and switch. To insure
that any noise is seen as common-mode and not differ-
ential, a balanced interconnect should be used. Twisted
pair cable will offer better balance than flat ribbon cable.
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
<
(stubs should be 10mm long). This will help eliminate re-
flections and ensure noise is coupled as common-mode. In
fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is re-
jected by the receiver.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ-
ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to
2.4V). It is only supported with inputs shorted and no ex-
ternal common-mode voltage applied.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field can-
cellation benefits of differential signals and EMI will result!
(Note that the velocity of propagation, v = c/E where c (the
r
speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Care-
fully review dimensions to match differential impedance and
provide isolation for the differential lines. Minimize the num-
ber of vias and other discontinuities on the line.
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
of higher noise levels. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2V (less than 1.75V)
to be compatible with the internal circuitry.
Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
Probing LVDS Transmission Lines:
>
Always use high impedance ( 100kΩ), low capacitance
<
(
2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments:
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4
Applications Information (Continued)
Pin Descriptions
When choosing cable and connectors for LVDS it is impor-
tant to remember:
Pin No.
1, 4
2, 3
6, 7
8
Name
RIN
RIN
Description
-
Inverting receiver input pin
Non-inverting receiver input pin
Use controlled impedance media. The cables and connec-
tors you use should have a matched differential impedance
of about 100Ω. They should not introduce major impedance
discontinuities.
+
ROUT Receiver output pin
VCC Power supply pin, +3.3V 0.3V
GND Ground pin
±
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax) for noise re-
duction and signal quality. Balanced cables tend to generate
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation a common-mode (not differen-
tial mode) noise which is rejected by the receiver.
5
Ordering Information
Operating
Temperature
−40˚C to +85˚C
Package Type/
Order Number
Number
<
For cable distances
0.5M, most cables can be made to
work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (cat-
egory 3) twisted pair cable works well, is readily available
and relatively inexpensive.
SOP/M08A
DS90LV028ATM
Typical Performance Curves
Output High Voltage vs
Power Supply Voltage
Output Low Voltage vs
Power Supply Voltage
DS100077-7
DS100077-8
Output Short Circuit Current vs
Power Supply Voltage
Differential Transition Voltage vs
Power Supply Voltage
DS100077-10
DS100077-9
5
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Typical Performance Curves (Continued)
Power Supply Current
vs Frequency
Power Supply Current vs
Ambient Temperature
DS100077-12
DS100077-11
Differential Propagation Delay vs
Power Supply Voltage
Differential Propagation Delay vs
Ambient Temperature
DS100077-13
DS100077-14
Differential Skew vs
Power Supply Voltage
Differential Skew vs
Ambient Temperature
DS100077-15
DS100077-16
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6
Typical Performance Curves (Continued)
Differential Propagation Delay vs
Differential Input Voltage
Differential Propagation Delay vs
Common-Mode Voltage
DS100077-17
DS100077-18
Transition Time vs
Transition Time vs
Power Supply Voltage
Ambient Temperature
DS100077-19
DS100077-20
Differential Propagation Delay
vs Load
Transition Time
vs Load
DS100077-22
DS100077-21
7
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Typical Performance Curves (Continued)
Differential Propagation Delay
vs Load
Transition Time
vs Load
DS100077-24
DS100077-23
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8
9
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC
Order Number DS90LV028ATM
NS Package Number M08A
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