DS92LV1021MDC [NSC]
IC LINE DRIVER, UUC, DIE, Line Driver or Receiver;
| 型号： | DS92LV1021MDC |
| 厂家： | 
National Semiconductor |
| 描述： | IC LINE DRIVER, UUC, DIE, Line Driver or Receiver 驱动 接口集成电路 驱动器 |
| 文件： | 总18页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1999
DS92LV1021 and DS92LV1210
16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
due to charged cable conditions. The DS92LV1021 output
General Description
®
pins may be TRI-STATE
to achieve a high impedance
The DS92LV1021 transforms a 10-bit wide parallel CMOS/
TTL data bus into a single high speed Bus LVDS serial data
stream with embedded clock. The DS92LV1210 receives the
Bus LVDS serial data stream and transforms it back into a
10-bit wide parallel data bus and separates clock. The
DS92LV1021 may transmit data over heavily loaded back-
planes or 10 meters of cable. The reduced cable, PCB trace
count and connector size saves cost and makes PCB design
layout easier. Clock-to-data and data-to-data skew are elimi-
nated since one output will transmit both clock and all data
bits serially. The powerdown pin is used to save power, by
reducing supply current when either device is not in use. The
Serializer has a synchronization mode that should be acti-
vated upon power-up of the device. The Deserializer will es-
tablish lock to this signal within 1024 cycles, and will flag
Lock status. The embedded clock guarantees a transition on
the bus every 12-bit cycle; eliminating transmission errors
state. The PLL can lock to frequencies between 16 MHz and
40 MHz.
Features
n Guaranteed transition every data transfer cycle
n Single differential pair eliminates multi-channel skew
n Flow-through pinout for easy PCB layout
n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
n Synchronization mode and LOCK indicator
n Programmable edge trigger on clock
n High impedance on receiver inputs when power is off
n Bus LVDS serial output rated for 27Ω load
n Small 28-lead SSOP package-MSA
Block Diagrams
DS100110-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100110
www.national.com
Block Diagrams (Continued)
Application
DS100110-2
tion is that one or both of the Serializer SYNC inputs are as-
serted for at least 1024 cycles of TCLK to initiate transmis-
sion of SYNC patterns. The Serializer will continue to send
SYNC patterns after the minimum of 1024 if either of the
SYNC inputs remain high.
Functional Description
The DS92LV1021 and DS92LV1210 is a 10-bit Serializer /
Deserializer chipset designed to transmit data over a heavily
loaded differential backplanes at clock speeds from 16 to
40MHz. It may also be used to drive data over Unshielded
Twisted Pair (UTP) cable.
When the Deserializer detects edge transitions at the Bus
LVDS input it will attempt to lock to the embedded clock in-
formation. When the Deserializer locks to the Bus LVDS
clock, the LOCK output will go low. When LOCK is low the
Deserializer outputs represent incoming Bus LVDS data.
The chipset has three active states of operation: Initializa-
tion, Data Transfer, and Resynchronization; and two passive
states: Powerdown and TRI-STATE®.
The following sections describe each operation and passive
state.
Data Transfer
After initialization, the Serializer inputs DIN0–DIN9 may be
used to input data to the Serializer. Data is clocked into the
Serializer by the TCLK input. The edge of TCLK used to
strobe in data is selectable via the TCLK_R/F pin. TCLK_R/F
high selects the rising edge for clocking data and low selects
the falling edge. If either of the SYNC inputs is high for
5*TCLK cycles the data at DIN 0-DIN9 is ignored regardless
of the clock edge.
Initialization
Before data can be transferred both devices must be initial-
ized. Initialization refers to synchronization of the Serializer
and the Deserializer PLL’s to local clocks that may be the
same or separate. Afterward, synchronization of Deserializer
to Serializer occurs as the second step of initialization.
Step 1: When VCC is applied to both Serializer and/or Dese-
rializer, the respective outputs are held in TRI-STATE® and
internal circuitry is disabled by on-chip power-on circuitry.
When VCC reaches VCC OK (2.5V) the PLL in each device
begins locking to a local clock. For the Serializer, the local
clock is the transmit clock, TCLK, provided by the source
ASIC or other device. For the Deserializer, the local clock is
provided by an on-board oscillator or other source and ap-
plied to the REFCLK pin. After VCC OK is reached the de-
vice’s PLL will lock.
A start bit and a stop bit, appended internally, frame the data
bits in the register. The start bit is always high and the stop
bit is always low. The start and stop bits function as the em-
bedded clock bits in the serial stream.
Serialized data and clock bits (10+2 bits) are transmitted
from the serial data output (DO) at 12 times the TCLK fre-
quency. For example, if TCLK is 40 MHz, the serial rate is 40
x 12 = 480 Mega bits per second. Since only 10 bits are from
input data, the serial “payload” rate is 10 times the TCLK fre-
quency. For instance, if TCLK = 40 MHz, the payload data
rate is 40 x 10 = 400 Mbps. TCLK is provided by the data
source and must be in the range 16 MHz to 40 MHz nominal.
The Serializer outputs are held in TRI-STATE while the PLL
locks to the TCLK. The Serializer is now ready to send data
or SYNC patterns depending on the levels of the SYNC1 and
SYNC2 inputs. The SYNC pattern is composed of six ones
and six zeros switching at the input clock rate.
±
The outputs (DO ) can drive a heavily loaded backplane or
a point-to-point connection. The outputs transmit data when
the enable pin (DEN) is high, PWRDN = high and SYNC1
and SYNC2 are low. The DEN pin may be used to TRI-
STATE the outputs when driven low.
The Deserializer LOCK output will remain high while its PLL
is locking to the local clock- the REFCLK input and then to
SYNC patterns on the input.
Step 2: The Deserializer PLL must synchronize to the Serial-
izer to complete the initialization. The transmission of SYNC
patterns to the Deserializer enables the Deserializer to lock
to the Serializer signal.
The LOCK pin on the Deserializer is driven low when it is
synchronized with the Serializer. The Deserializer locks to
the embedded clock and uses it to recover the serialized
data. ROUT data is valid when LOCK is low. Otherwise
ROUT0–ROUT9 is invalid.
Control of the sync pins is left to the user. A feedback loop
between the LOCK pin is one recommendation. Another op-
www.national.com
2
there is no data to be transferred. Powerdown is entered
when PWRDN and REN are driven low on the Deserializer,
and when the PWRDN is driven low on the Serializer. In
Powerdown, the PLL is stopped and the outputs go into TRI-
STATE, disabling load current and also reducing supply cur-
rent to the milliamp range. To exit Powerdown, PWRDN is
driven high.
Data Transfer (Continued)
RCLK pin is the reference to data on the ROUT0-ROUT9
pins. The polarity of the RCLK edge is controlled by the
RCLK_R/F input.
ROUT(0-9), LOCK and RCLK outputs will drive a minimum
of three CMOS input gates (15 pF load) with 40 MHz clock.
Both the Serializer and Deserializer must reinitialize and re-
synchronize before data can be transferred. Initialization of
the Serializer takes 1024 TCLK cycles. The Deserializer will
initialize and assert LOCK high until it is locked to the Bus
LVDS clock.
Resynchronization
The Deserializer LOCK pin driven low indicates that the De-
serializer PLL is locked to the embedded clock edge. If the
Deserializer loses lock, the LOCK output will go high and the
outputs (including RCLK) will be TRI-STATE.
TRI-STATE
The LOCK pin must be monitored by the system to detect a
loss of synchronization and the system must arrange to
pulse the Serializer SYNC1 or SYNC2 pin to resynchronize.
There are multiple approaches possible. One recommenda-
tion is to provide a feedback loop using the LOCK pin itself to
control the sync request of the Serializer (SYNC1 or
SYNC2). Otherwise, LOCK pin needs to be monitored and
when it is a high, the system needs to ensure that one or
both of the Serializer SYNC inputs area asserted for at least
1024 cycles of TCLK. A minimum of 1024 sync patterns are
needed to resynchronize. Dual SYNC pins are provided for
multiple control in a multi-drop application.
For the Serializer, TRI-STATE is entered when the DEN pin
is driven low. This will TRI-STATE both driver output pins
(DO+ and DO−). When DEN is driven high the serializer will
return to the previous state as long as all other control pins
remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
For the Deserializer, TRI-STATE is entered when the REN
pin is driven low. This will TRI-STATE the receiver output
pins (ROUT0–ROUT9), LOCK and RCLK.
Powerdown
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer may use to reduce power when
Order Numbers
NSID
Function
Serializer
Package
MSA28
MSA28
DS92LV1021TMSA
DS92LV1210TMSA
Deserializer
3
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Derating:
10.2 mW/˚C above
+25˚C
28L SSOP
>
ESD Rating (HBM)
5kV
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
Recommended Operating
Conditions
Bus LVDS Receiver Input
Voltage
−0.3V to +3.9V
−0.3V to +3.9V
Min
Nom Max Units
Bus LVDS Driver Output
Voltage
Supply Voltage (VCC
)
3.0
3.3
3.6
+85
2.4
V
˚C
V
Operating Free Air
Temperature (TA)
Bus LVDS Output Short
Circuit Duration
−40
0
+25
Continuous
+150˚C
Junction Temperature
Storage Temperature
Lead Temperature
Receiver Input Range
−65˚C to +150˚C
Supply Noise Voltage
100 mVP-P
(VCC
)
(Soldering, 4 seconds)
+260˚C
Maximum Package Power Dissipation Capacity
@
25˚C Package:
28L SSOP
1.27 W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions
Min
Typ
Max
Units
SERIALIZER CMOS/TTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN)
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
−1.5
+10
V
±
VIN = 0V or 3.6V
−10
2
µA
DESERIALIZER CMOS/TTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins
ROUT, RCLK, LOCK = outputs)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
2.0
VCC
0.8
V
V
GND
VCL
IIN
ICL = −18 mA
−0.62
−1.5
+10
VCC
0.6
V
±
Input Current
VIN = 0V or 3.6V
IOH = −9 mA
−10
2.1
1
µA
V
VOH
VOL
IOS
IOZ
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE Output Current
2.93
0.33
−38
IOL = 9 mA
GND
−15
−10
V
VOUT = 0V
−85
+10
mA
µA
±
PWRDN or REN = 0.8V, VOUT = 0V or VCC
0.4
SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−)
VOD
Output Differential Voltage
(DO+)–(DO−)
RL = 27Ω
200
270
mV
∆VOD
Output Differential Voltage
Unbalance
35
mV
VOS
∆VOS
IOS
Offset Voltage
0.78
1.1
1.3
35
V
Offset Voltage Unbalance
Output Short Circuit Current
TRI-STATE Output Current
Power-Off Output Current
mV
mA
µA
µA
D0 = 0V, DIN = High,PWRDN and DEN = 2.4V
PWRDN or DEN = 0.8V, DO = 0V or VCC
VCC = 0V, DO = 0V or VCC
−10
−15
+10
+20
±
±
IOZ
−10
−20
1
1
IOX
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
VTH
Differential Threshold High
Voltage
VCM = +1.1V
+19
−7
+100
mV
mV
VTL
Differential Threshold Low
Voltage
−100
www.national.com
4
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
±
±
IIN
Input Current
VIN = +2.4V, VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V or 0V
−10
−15
1
1
+10
+15
µA
µA
SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCD
Serializer Supply Current
Worst Case
RL = 27Ω
f = 40 MHz
f = 16 MHz
32
25
55
45
mA
mA
Figure 1
ICCXD
Serializer Supply Current
Powerdown
PWRDN = 0.8V
4
10
mA
DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCR
Deserializer Supply Current
Worst Case
CL = 15 pF
f = 40 MHz
f = 16 MHz
44
31
75
55
mA
mA
Figure 2
ICCXR
Deserializer Supply Current
Powerdown
PWRDN = 0.8V, REN = 0.8V
1.5
5.0
mA
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Conditions
Min
25
Typ
T
Max
62.5
0.6T
0.6T
6
Units
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
ns
ns
ns
ns
ps
tTCIH
tTCIL
tCLKT
tJIT
0.4T
0.4T
0.5T
0.5T
3
150
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
RL = 27Ω
Figure 3
Min
Typ
Max
Units
tLLHT
Bus LVDS Low-to-High
Transition Time
0.2
1
1
ns
CL=10pF to GND
tLHLT
Bus LVDS High-to-Low
Transition Time
0.25
ns
tDIS
tDIH
tHZD
DIN (0-9) Setup to TCLK
Figure 6
RL = 27Ω,
CL=10pF to GND
1.0
6.5
0
ns
ns
DIN (0-9) Hold from TCLK
4.5
±
DO HIGH to
Figure 7 (Note 4)
RL = 27Ω,
CL=10pF to GND
3.5
2.9
2.5
2.7
10
10
10
10
ns
ns
ns
ns
TRI-STATE Delay
±
tLZD
tZHD
tZLD
DO LOW to TRI-STATE
Delay
±
DO TRI-STATE to HIGH
Delay
±
DO TRI-STATE to LOW
Delay
tSPW
tPLD
tSD
SYNC Pulse Width
Serializer PLL Lock Time
Serializer Delay
Bus LVDS Bit Width
Figure 8
RL = 27Ω
1024*tTCP
2048*tTCP
tTCP
1029*tTCP
2049*tTCP
tTCP+ 5
ns
ns
ns
Figure 9 RL = 27Ω
tTCP + 2.5
tCLK / 12
tBIT
RL = 27Ω,
CL=10pF to GND
ns
5
www.national.com
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRFCP
Parameter
REFCLK Period
Conditions
Min
Typ
T
Max
Units
ns
25
62.5
tRFDC
REFCLK Duty Cycle
50
%
tRFCP / tTCP
Ratio of REFCLK to TCLK
Periods
0.83
1
3
1.03
6
tRFTT
REFCLK Transition Time
ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
tRCP
Receiver out Clock
Period
Figure 9
tRCP = tTCP
RCLK
25
62.5
ns
ns
tCLH
tCHL
CMOS/TTL Low-to-High
Transition Time
CL = 15 pF
Figure 4
Rout(0-9),
2
5
5
CMOS/TTL High-to-Low
Transition Time
LOCK, RCLK
2
ns
ns
ns
tDD
Deserializer Delay
Figure 10
Figure 11
1.75*tRCP
0.4*tRCP
1.75*tRCP+3
0.5*tRCP
1.75*tRCP+7
tROS
ROUT (0-9) Setup Data to
RCLK
RCLK
tROH
ROUT (0-9) Hold Data to
RCLK
−0.4*tRCP
40
−0.5*tRCP
ns
tRDC
tHZR
tLZR
RCLK Duty Cycle
50
60
%
ns
ns
ns
ns
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Figure 12
Rout(0-9),
LOCK
4+0.5*tRCP
4.2+0.5*tRCP
6+0.5*tRCP
6.5+0.5*tRCP
10+tRCP
10+tRCP
12+tRCP
12+tRCP
tZHR
tZLR
tDSR1
Deserializer PLL Lock Time
from PWRDWN (with
SYNCPAT)
(Note 5)
Figure 13
Figure 14
16MHz
40MHz
7
15
µs
µs
4.8
25.6
tDSR2
Deserializer PLL Lock time
from SYNCPAT
16MHz
40MHz
LOCK
7
10
7
µs
µs
4.5
tZHLK
tRNM
TRI-STATE to HIGH Delay
(power-up)
1.5
12
ns
Deserializer Noise Margin
Figure 15
(Note 6)
16 MHz
40 MHz
400
100
1100
400
ps
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V
CC
= 3.3V and T = +25˚C.
A
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD, VTH
and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions
of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time required
for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before initiating ei-
ther condition. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from not re-
ceiving data to receiving synchronization patterns (SYNCPATs).
Note 6: tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur.
www.national.com
6
AC Timing Diagrams and Test Circuits
DS100110-3
FIGURE 1. “Worst Case” Serializer ICC Test Pattern
DS100110-4
FIGURE 2. “Worst Case” Deserializer ICC Test Pattern
DS100110-5
FIGURE 3. Serializer Bus LVDS Output Load and Transition Times
DS100110-6
FIGURE 4. Deserializer CMOS/TTL Output Load and Transition Times
DS100110-7
FIGURE 5. Serializer Input Clock Transition Time
7
www.national.com
AC Timing Diagrams and Test Circuits (Continued)
DS100110-8
Timing shown for TCLK_R/F = LOW
FIGURE 6. Serializer Setup/Hold Times
DS100110-9
FIGURE 7. Serializer TRI-STATE Test Circuit and Timing
DS100110-10
FIGURE 8. Serializer PLL Lock Time, SYNC Timing and PWRDN TRI-STATE Delays
www.national.com
8
AC Timing Diagrams and Test Circuits (Continued)
DS100110-11
FIGURE 9. Serializer Delay
DS100110-12
FIGURE 10. Deserializer Delay
DS100110-13
Timing shown for RCLK_R/F = LOW
Duty Cycle (t ) =
RDC
FIGURE 11. Deserializer Setup and Hold Times
9
www.national.com
AC Timing Diagrams and Test Circuits (Continued)
DS100110-14
FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing
DS100110-15
FIGURE 13. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
www.national.com
10
AC Timing Diagrams and Test Circuits (Continued)
DS100110-22
FIGURE 14. Deserializer PLL Lock Time from SyncPAT
DS100110-21
SW - Setup and Hold Time (Internal data sampling window)
t
t
- Serializer Output Bit Position Jitter
JIT
= Receiver Sampling Margin Time
RSM
FIGURE 15. Receiver Bus LVDS Input Skew Margin
DS100110-16
+
−
=
V
OD
(DO )–(DO ).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
11
www.national.com
While the Deserializer LOCK output is low, data at the Dese-
rializer outputs (ROUT0-9) is valid except for the specific
case of loss of lock during transmission.
Application Information
Using the DS92LV1021 and DS92LV1210
The Serializer and Deserializer chipset is an easy to use
transmitter and receiver pair that sends 10 bits of parallel
TTL data over a serial Bus LVDS link up to 400 Mbps. Seri-
alization of the input data is accomplished using an onboard
PLL at the Serializer which embeds two clock bits with the
data. The Deserializer uses
a separate reference clock
(REFCLK) and an onboard PLL to extract the clock informa-
tion from the incoming data stream and deserialize the data.
The Deserializer monitors the incoming clock information to
determine lock status and will indicate loss of lock by raising
the LOCK output.
Power Considerations
All CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the Bus LVDS outputs minimize the
slope of the speed vs. ICC curve of CMOS designs.
Powering Up the Serializer
The DS92LV1021 must be powered up using a specific se-
quence to properly start the PLL up. Not following the se-
quence can cause the Bus LVDS outputs to be stuck in a
certain output state. This may occur if the TCLK input is
driven before power is applied to the Serializer. It is impor-
tant to note that this is not a latch up condition: no excessive
current is drawn by the Serializer in this state and the power
does not need to be cycled to recover from this state. Cycling
the PWRDWN pin from high to low and back to high will reset
the PLL and return the Serializer to normal operation.
To avoid this condition, the Serializer should be powered up
(ALL VCC pins) simultaneously with the PWRDWN pin held
low for 1µs. Once the VCC pins have stabilized the TCLK in-
put can be driven and the Serializer will be ready for data
transmission.
Powering Up the Deserializer
The DS92LV1210 can be powered up at any time following
the proper sequence. The REFCLK input can be running be-
fore the Deserializer is powered up and it must be running in
order for the Deserializer to lock to incoming data. The Dese-
™
rializer outputs will remain in TRI-STATE until the Deserial-
izer detects data transmission at its inputs and locks to the
incoming stream. The recommended power up sequence for
the deserializer is to power up all VCC pins simultaneously
with the PWRDWN pin held low for 1µs. Once the VCC pins
have stabilized the Deserializer is ready for locking. Another
option to ensure proper power up is to cycle the PWRDWN
pin from high to low and back to high after power up.
Transmitting Data
Once the Serializer and Deserializer are powered up and
running they must be phase locked to each other in order to
transmit data. Phase locking is accomplished by the Serial-
izer sending SYNC patterns to the Deserializer. SYNC pat-
terns are sent by the Serializer whenever SYNC1 or SYNC2
inputs are held high. The LOCK output of the Deserializer is
high whenever the Deserializer is not locked. Connecting the
LOCK output of the Deserializer to one of the SYNC inputs of
the Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
www.national.com
12
alizer to the slot connector appears as a stub to the Serial-
izer driving the backplane traces. Longer stubs lower the
impedance of the bus increasing the load on the Serializer
and lowers threshold margin at the Deserializers. Deserial-
izer devices should be placed no more than 1 inch from the
slot connector.
Application Information (Continued)
Noise Margin
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reli-
ably receive data. Various environmental and systematic fac-
tors include:
Transmission Media
Serializer: TCLK jitter, VCC noise (noise bandwidth and
out-of-band noise)
The Serializer and Deserializer are designed for data trans-
mission over a multi-drop bus. Multi-drop buses use a single
Serializer and multiple Deserializer devices. Since the Seri-
alizer can be driving from any point on the bus, the bus must
be terminated at both ends. For example, a 100 Ohm differ-
ential bus must be terminated at each end with 100 Ohms
lowering the DC impedance that the Serializer must drive to
50 Ohms. This load is further lowered by the addition of mul-
tiple Deserializers. Adding up to 20 Deserializers to the bus
(depending upon spacing) will lower the total load to about
27 Ohms (54 Ohm bus). The Serializer is designed for DC
loads between 27 and 100 Ohms.
Media: ISI, VCM noise
Deserializer: VCC noise
Recovering from LOCK Loss
In the case where the Serializer loses lock during data trans-
mission up to 5 cycles of data that was previously received
can be invalid. This is due to the delay in the lock detection
circuit. The lock detect circuit requires that invalid clock infor-
mation be received 4 times in a row to indicate loss of lock.
Since clock information has been lost it is possible that data
was also lost during these cycles. When the Deserializer
LOCK pin goes low, data from at least the previous 5 cycles
should be resent upon regaining lock.
The Serializer and Deserializer can also be used in
point-to-point configuration of a backplane, PCB trace or
through a twisted pair cable. In point-to-point configurations
the transmission media need only be terminated at the re-
ceiver end. In the point-to-point configuration the potential of
offsetting the ground levels of the Serializer vs. the Deserial-
izer must be considered. Bus LVDS provides a plus / minus
one volt common mode range at the receiver inputs.
Lock can be regained at the Deserializer by causing the Se-
rializer to resend SYNC patterns as described above.
PCB Considerations
The Bus LVDS devices Serializer and Deserializer should be
placed as close to the edge connector as possible. In mul-
tiple Deserializer applications, the distance from the Deseri-
13
www.national.com
Pin Diagrams
DS92LV1021TMSA - Serializer
DS100110-18
DS92LV1210TMSA - Deserializer
DS100110-19
www.national.com
14
Serializer Pin Description
Pin Name
I/O
No.
Description
DIN
I
3–12
Data Input. TTL levels inputs. Data on these pins are loaded into
a 10-bit input register.
TCLK_R/F
I
13
Transmit Clock Rising/Falling strobe select. TTL level input.
Selects TCLK active edge for strobing of DIN data. High selects
rising edge. Low selects falling edge.
DO+
DO−
DEN
O
O
I
22
21
19
+ Serial Data Output. Non-inverting Bus LVDS differential output.
− Serial Data Output. Inverting Bus LVDS differential output.
Serial Data Output Enable. TTL level input. A low, puts the Bus
LVDS outputs in TRI-STATE.
PWRDN
I
24
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
TCLK
SYNC
I
I
14
Transmit Clock. TTL level input. Input for 16 MHz–40 MHz
(nominal) system clock.
1, 2
Assertion of SYNC (high) for at least 1024 synchronization
symbols to be transmitted on the Bus LVDS serial output.
Synchronization symbols continue to be sent if SYNC continues
asserted. TTL level input. The two SYNC pins are ORed.
DVCC
DGND
AVCC
AGND
I
I
I
I
27, 28
15, 16
Digital Circuit power supply.
Digital Circuit ground.
17, 26
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
18, 25, 20, 23
15
www.national.com
Deserializer Pin Description
Pin Name
I/O
No.
Description
±
ROUT
O
15–19,
24–28
Data Output. 9 mA CMOS level outputs.
RCLK_R/F
I
2
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High
selects rising edge. Low selects falling edge.
RI+
I
I
I
5
6
7
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
RI−
PWRDN
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
LOCK
O
10
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wire OR connection.
RCLK
REN
O
I
9
8
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,
LOCK and RCLK when driven low.
DVCC
DGND
AVCC
I
I
I
I
I
21, 23
14, 20, 22
4, 11
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
AGND
REFCLK
1, 12, 13
3
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
www.national.com
16
Truth Table
DIN (0–9)
TCLK_R/F
TCLK
SYNC1/SYNC2 DEN PWRDN
DO+
Z
DO−
Z
X
X
X
X
X
1
X
X
X
X
0
1
1
1
0
1
1
1
1
X
Z
Z
z
X
SYSTEM CLK
1
SYNC PTRN SYNC PTRN*
L
DATA
DATA
0
0
DATA (0–9)
DATA (0–9)
DATA (0–9)*
DATA (0–9)*
K
0
RI
X
RI−
X
RCLK_R/F
REFCLK
X
REN PWRDN
RCLK
Z
LOCK
ROUT (0–9)
X
X
X
1
X
0**
1
0
1
1
1
1
Z
Z
Z
Z
X
X
X
Z
†
SYNC PTRN SYNC PTRN*
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
CLK
L
K
1
SYNC PTRN
DATA
DATA (0–9)
DATA (0–9)
DATA (0–9)*
DATA (0–9)*
1
0
0
1
0
DATA
z
Pulse 5-bits
* Inverted
†
Must be 1 before SYNC PTRN starts
** Device must be locked first
17
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS92LV1021TMSA or DS92LV1210TMSA
NS Package Number MSA28
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
DS92LV1021TMSA
DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery
TI
©2020 ICPDF网 联系我们和版权申明