HPC46083 [NSC]
High-Performance microControllers; 高性能微控制器
| 型号： | HPC46083 |
| 厂家： | 
National Semiconductor |
| 描述： | High-Performance microControllers |
| 文件： | 总36页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
April 1994
HPC16083/HPC26083/HPC36083/HPC46083/
HPC16003/HPC26003/HPC36003/HPC46003
High-Performance microControllers
General Description
Features
Y
The HPC16083 and HPC16003 are members of the HPCTM
family of High Performance microControllers. Each member
of the family has the same core CPU with a unique memory
and I/O configuration to suit specific applications. The
HPC16083 has 8k bytes of on-chip ROM. The HPC16003
has no on-chip ROM and is intended for use with external
direct memory. Each part is fabricated in National’s ad-
vanced microCMOS technology. This process combined
with an advanced architecture provides fast, flexible I/O
control, efficient data manipulation, and high speed compu-
tation.
HPC familyÐcore features:
Ð 16-bit architecture, both byte and word
Ð 16-bit data bus, ALU, and registers
Ð 64k bytes of external direct memory addressing
Ð FASTÐ200 ns for fastest instruction when using
20.0 MHz clock, 134 ns at 30 MHz
Ð High code efficiencyÐmost instructions are single
byte
Ð 16 x 16 multiply and 32 x 16 divide
Ð Eight vectored interrupt sources
Ð Four 16-bit timer/counters with 4 synchronous out-
puts and WATCHDOG logic
The HPC devices are complete microcomputers on a single
chip. All system timing, internal logic, ROM, RAM, and I/O
are provided on the chip to produce a cost effective solution
for high performance applications. On-chip functions such
as UART, up to eight 16-bit timers with 4 input capture regis-
ters, vectored interrupts, WATCHDOGTM logic and MICRO-
WIRE/PLUSTM provide a high level of system integration.
The ability to address up to 64k bytes of external memory
enables the HPC to be used in powerful applications typical-
ly performed by microprocessors and expensive peripheral
chips. The term ‘‘HPC16083’’ is used throughout this data-
sheet to refer to the HPC16083 and HPC16003 devices un-
less otherwise specified.
Ð MICROWIRE/PLUS serial I/O interface
Ð CMOSÐvery low power with two power save modes:
IDLE and HALT
Y
Y
UARTÐfull duplex, programmable baud rate
Four additional 16-bit timer/counters with pulse width
modulated outputs
Y
Y
Y
Y
Y
Four input capture registers
52 general purpose I/O lines (memory mapped)
8k bytes of ROM, 256 bytes of RAM on chip
ROMless version available (HPC16003)
a
b
40 C to
Commercial (0 C to
a
70 C), industrial
(
85 C), automotive ( 40 C to 105 C) and military
§
§
§
b
a
55 C to 125 C) temperature ranges
§
§
§
The microCMOS process results in very low current drain
and enables the user to select the optimum speed/power
product for his system. The IDLE and HALT modes provide
further current savings. The HPC is available in 68-pin
PLCC, LDCC, PGA and 80-Pin PQFP packages.
b
a
(
§
§
For applications requiring more RAM and ROM see
HPC16064 data sheet.
Block Diagram (HPC16083 with 8k ROM shown)
TL/DD/8801–1
Series 32000É, TapePakÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
MOLETM, HPCTM, COPSTM, MICROWIRE/PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation.
UNIXÉ is a registered trademarks of AT&T Bell Laboratories.
VAXTM is a trademark of Digital Equipment Corporation.
IBMÉ and PC/ATÉ are registered trademarks of International Business Machines Corporation.
SUNÉ is a registered trademark of Sun Microsystems.
SunOSTM is a trademark of Sun Microsystems.
C
1995 National Semiconductor Corporation
TL/DD/8801
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
0.5V to 7.0V
V
with Respect to GND
CC
a
b
0.5)V to (GND 0.5)V
All Other Pins
(V
CC
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
Total Allowable Source or Sink Current
Storage Temperature Range
100 mA
b
a
65 C to 150 C
§
§
Lead Temperature (Soldering, 10 sec)
300 C
§
e
HPC46083/HPC46003, 40 C to 85 C for HPC36083/HPC36003, 40 C to 105 C for
e
A
a
0 C to 70 C for
g
5.0V 10% unless otherwise specified, T
DC Electrical Characteristics V
§
§
§
CC
b
a
b
a
§
HPC26083/HPC26003, 55 C to 125 C for HPC16083/HPC16003
§
§
b
a
§
§
Symbol
Parameter
Test Conditions
Min
Max
65
Units
mA
mA
mA
mA
mA
mA
mA
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
I
I
I
Supply Current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
5.5V, f
5.5V, f
5.5V, f
5.5V, f
5.5V, f
5.5V, f
5.5V, f
2.5V, f
30 MHz (Note 1)
20 MHz (Note 1)
CC
CC
CC
in
in
in
in
in
in
in
in
1
2
3
47
2.0 MHz (Note 1)
30 MHz (Note 1)
20 MHz, (Note 1)
2.0 MHz, (Note 1)
0 kHz, (Note 1)
0 kHz, (Note 1)
10
IDLE Mode Current
HALT Mode Current
5.0
3.0
1
200
50
mA
INPUT VOLTAGE LEVELS FOR SCHMITT TRIGGERED INPUTS RESET, NMI AND WO; AND ALSO CKI
V
IH
Logic High
Logic Low
0.9 V
V
V
1
CC
V
IL
0.1 V
0.2 V
1
CC
INPUT VOLTAGE LEVELS FOR ALL OTHER INPUTS
V
IH
Logic High
0.7 V
V
V
2
CC
V
IL
Logic Low
2
CC
e
e
e
e
g
I
I
Input Leakage Current
V
V
0 and V
0
V
CC
2
mA
LI1
LI2
IN
IN
Input Leakage Current
RDY/HLD, EXUI
b
b
50
3
mA
IN
I
Input Leakage Current
B12
LI3
e
RESET
0, V
IN
V
CC
0.5
7
mA
C
C
Input Capacitance
I/O Capacitance
(Note 2)
(Note 2)
10
20
pF
pF
I
IO
OUTPUT VOLTAGE LEVELS
V
e b
b
OH
Logic High (CMOS)
Logic Low (CMOS)
Port A/B Drive, CK2
I
I
I
I
I
I
I
I
I
10 mA (Note 2)
V
CC
0.1
V
V
V
V
V
V
V
V
V
1
2
3
OH
OH
OH
OL
OH
OL
OH
OL
OH
V
V
V
V
V
V
V
V
e
OL
10 mA (Note 2)
0.1
0.4
0.4
0.4
1
e b
OH
OL
7 mA
2.4
2.4
2.4
2.4
(A –A , B , B , B , B
0 15 10 11 12 15
)
e
3 mA
2
e b
OH
OL
Other Port Pin Drive, WO (open
drain), (B –B , B , B , P –P )
1.6 mA (except WO)
0
9
13 14
0
3
e
0.5 mA
3
e b
OH4
OL
ST1 and ST2 Drive
6 mA
e
1.6 mA
4
e b
OH5
Port A/B Drive (A –A ,
0
1 mA
15
, B , B , B ) when used
as External Address/Data Bus
B
10 11 12 15
e
V
I
3 mA
0.4
V
OL5
OL
V
I
RAM Keep-Alive Voltage
(Note 3)
2.5
V
V
RAM
CC
e
e
g
TRI-STATE Leakage Current
É
V
IN
0 and V
V
CC
5
mA
OZ
IN
e
e
e
e
is measured with NMI V
Note 1: I
, I
CC CC CC
, I
measured with no external drive (I
OH
and V , with rise and fall times less than 10 ns.
and I
0, I and I
IH
0). I
CC
is measured with RESET
V , I
SS CC
3
,
CC
OL
IL
1
CKI driven to V
2
IH1
3
1
IL1
Note 2: This is guaranteed by design and not tested.
Note 3: Test duration is 100 ms.
2
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 thru Figure 5) V
e
HPC46083/HPC46003, 40 C to 85 C for HPC36083/HPC36003, 40 C to 105 C for HPC26083/HPC26003, 55 C to
e a
0 C to 70 C for
g
5.0V 10% unless otherwise specified, T
§
§
CC
A
b
125 C for HPC16083/HPC16003
a
b
a
b
§
§
§
§
§
a
§
Symbol and Formula
Parameter
Min
Max
Units
Note
f
t
t
t
t
t
t
CKI Operating Frequency
CKI Clock Period
2
20
MHz
ns
C
e
1/f
50
500
C1
C
CKI High Time
22.5
22.5
100
100
ns
CKIH
CKI Low Time
ns
CKIL
e
2/f
e
CPU Timing Cycle
ns
C
C
t
C
CPU Wait State Period
Delay of CK2 Rising Edge after
CKI Falling Edge
ns
WAIT
DC1C2R
DC1C2F
0
0
55
55
ns
ns
(Note 2)
(Note 2)
t
Delay of CK2 Falling Edge after
CKI Falling Edge
e
f
f
f /8
C
External UART Clock Input Frequency
External MICROWIRE/PLUS
Clock Input Frequency
2.5**
MHz
MHz
U
MW
1.25
e
f
t
f /22
C
External Timer Input Frequency
Pulse Width for Timer Inputs
0.91
MHz
ns
XIN
e
t
C
100
XIN
t
t
t
MICROWIRE Setup TimeÐMaster
ÐSlave
100
20
ns
ns
ns
UWS
UWH
UWV
MICROWIRE Hold TimeÐMaster
ÐSlave
20
50
MICROWIRE Output Valid TimeÐMaster
ÐSlave
50
150
e
e
a
10
t
t
t
t
t
t
*/4 t
40
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
115
110
ns
ns
ns
ns
ns
ns
SALE
C
a
t
C
HWP
e
e
a
100
t
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
200
160
116
(Note 3)
HAE
HAD
C
a
*/4 t
85
66
C
e
a
C
(/2 t
(Note 5)
(Note 5)
BF
BE
e
a
66
(/2 t
116
10
10
100
0
C
t
t
t
t
t
t
t
t
t
t
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UAS
UAH
RPW
OE
URD Falling Edge to Output Data Valid
Rising Edge of URD to Output Data Invalid
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
60
35
70
5
(Note 6)
OD
DRDY
WDW
UDS
UDH
A
40
10
20
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
WRRDY Delay from Rising Edge of UWR
70
**This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
3
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 thru Figure 5) V
e
HPC46083/HPC46003, 40 C to 85 C for HPC36083/HPC36003, 40 C to 105 C for HPC26083/HPC26003, 55 C to
e a
0 C to 70 C for
g
5.0V 10% unless otherwise specified, T
§
§
CC
A
b
125 C for HPC16083/HPC16003 (Continued)
a
b
a
b
§
§
§
§
§
a
§
Symbol and Formula
Parameter
Min
Max
Units
Note
t
t
t
t
Delay from CKI Rising
DC1ALER
DC1ALEF
DC2ALER
DC2ALEF
0
35
ns
(Notes 1, 2)
Edge to ALE Rising Edge
Delay from CKI Rising
0
35
45
45
ns
ns
(Notes 1, 2)
(Note 2)
Edge to ALE Falling Edge
a
a
20
20
Delay from CK2 Rising
e
e
(/4 t
(/4 t
C
Edge to ALE Rising Edge
Delay from CK2 Rising
C
ns
ns
ns
(Note 2)
Edge to ALE Rising Edge
e
e
b
9
t
t
(/2 t
ALE Pulse Width
41
18
LL
C
b
(/4 t
7
Setup of Address Valid
before ALE Falling Edge
ST
C
e
b
t
(/4 t
5
Hold of Address Valid
after ALE Falling Edge
VP
C
20
20
ns
ns
ns
e
e
b
5
t
t
(/4 t
ALE Falling Edge to RD Falling Edge
ARR
C
a
b
WS 55
t
C
Data Input Valid after
Address Output Valid
ACC
145
95
(Note 6)
e
a
C
b
WS 65
t
(/2 t
Data Input Valid after
RD Falling Edge
RD
ns
ns
ns
ns
ns
ns
ns
e
e
a
b
b
WS 10
t
t
(/2 t
RD Pulse Width
140
0
RW
C
*/4 t
15
Hold of Data Input Valid
after RD Rising Edge
DR
C
60
e
b
15
t
t
t
Bus Enable after RD Rising Edge
85
RDA
C
e
b
5
(/2 t
ALE Falling Edge to
WR Falling Edge
ARW
C
45
e
a
b
WS 15
t
t
*/4 t
WR Pulse Width
160
145
WW
C
e
a
C
b
WS 5
(/2 t
Data Output Valid before
WR Rising Edge
V
e
b
5
t
t
t
(/4 t
Hold of Data Valid after
WR Rising Edge
HW
C
20
ns
e
a
C
b
WS 50
(/4 t
Falling Edge of ALE
DAR
RWP
75
ns
ns
to Falling Edge of RDY
e
t
RDY Pulse Width
100
C
e
Note: C
40 pF.
L
Note 1: These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t and T ) on CKI input less than 2.5 ns.
CKIR
CKIL
Note 2: Do not design with these parameters unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3: t
HAE
edge occurs later, t
is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed. If HLD falling
a
a
a
100) may occur depending on the following CPU instruction cycles, its wait state and ready input.
C
as long as (3t
4WS
72 t
HAE
C
e
Note 4: WS (t ) x (number of preprogrammed wait states). Minimum and maximum values are calculated at maximum operating frequency, t
WAIT
one wait programmed.
20 MHz, with
C
Note 5: Due to emulation restrictionsÐactual limits will be better.
Note 6: This is guaranteed by design and not tested.
4
30 MHz
AC Electrical Characteristics (Continued)
CC
e
HPC46083/HPC46003, 40 C to 85 C for HPC36083/HPC36003, 40 C to 105 C for HPC26083/HPC26003, 55 C to
e a
0 C to 70 C for
g
5.0V 10% unless otherwise specified, T
(See Notes 1 and 4 and Figure 1 thru Figure 5) V
§
§
A
b
125 C for HPC16083/HPC16003
a
b
a
b
§
§
§
§
§
a
§
Symbol and Formula
Parameter
Min
Max
Units
Note
f
t
t
t
t
t
t
CKI Operating Frequency
CKI Clock Period
2
33
30
MHz
ns
C
e
1/f
500
C1
C
CKI High Time
15
ns
CKIH
CKIL
CKI Low Time
16.6
66
ns
e
2/f
e
CPU Timing Cycle
ns
C
C
t
C
CPU Wait Sate Period
Delay of CK2 Rising Edge after
CKI Falling Edge
66
ns
WAIT
DC1C2R
DC1C2F
0
0
55
55
ns
ns
(Note 2)
(Note 2)
t
Delay of CK2 Falling Edge after
CKI Falling Edge
e
f
f
f /8
C
External UART Clock Input Frequency
External MICROWIRE/PLUS
Clock Input Frequency
3.75**
MHz
MHz
U
MW
1.875
e
f
t
f /22
C
External Timer Input Frequency
Pulse Width for Timer Inputs
1.364
MHz
ns
XIN
e
t
C
66
XIN
t
t
t
MICROWIRE Setup TimeÐMaster
ÐSlave
100
20
UWS
UWH
UWV
ns
ns
ns
MICROWIRE Hold TimeÐMaster
ÐSlave
20
50
MICROWIRE Output Valid TimeÐMaster
ÐSlave
50
150
e
e
a
10
t
t
t
t
t
t
*/4 t
40
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
90
76
ns
ns
ns
ns
ns
ns
SALE
C
a
t
C
HWP
e
e
a
85
t
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
151
135
99
(Note 3)
HAE
HAD
C
a
*/4 t
85
C
e
a
66
a
66
(/2 t
(Note 5)
(Note 5)
BF
BE
C
e
(/2 t
99
10
10
100
0
C
t
t
t
t
t
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
ns
ns
ns
ns
UAS
UAH
RPW
OE
URD Falling Edge to Output Data Valid
60
35
70
Rising Edge of URD to
Output Data Invalid
OD
5
ns
(Note 6)
t
t
t
t
t
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
ns
ns
ns
ns
ns
DRDY
WDW
UDS
UDH
A
40
10
15
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
WRRDY Delay from Rising Edge of UWR
70
**This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
5
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 thru Figure 5) V
e
HPC46083/HPC46003, 40 C to 85 C for HPC36083/HPC36003, 40 C to 105 C for HPC26083/HPC26003, 55 C to
e a
0 C to 70 C for
g
5.0V 10% unless otherwise specified, T
§
§
CC
A
b
125 C for HPC16083/HPC16003 (Continued)
a
b
a
b
§
§
§
§
§
a
§
Symbol and Formula
Parameter
Min
0
Max
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(Notes 1, 2)
(Notes 1, 2)
(Note 2)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay from CKI Rising Edge to ALE Rising Edge
Delay from CKI Rising Edge to ALE Falling Edge
Delay from CK2 Rising Edge to ALE Rising Edge
Delay from CK2 Falling Edge to ALE Falling Edge
ALE Pulse Width
DC1ALER
DC1ALEF
DC2ALER
DC2ALEF
0
35
e
e
a
a
(/4 t
20
20
37
C
(/4 t
37
(Note 2)
C
e
e
e
b
(/2 t
9
7
5
24
9
LL
ST
VP
C
b
b
(/4 t
(/4 t
Setup of Address Valid before ALE Falling Edge
Hold of Address Valid after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
Data Input Valid after Address Output Valid
Data Input Valid after RD Falling Edge
RD Pulse Width
C
C
11
12
e
e
b
C
(/4 t
5
ARR
ACC
a
b
WS 32
t
C
100
60
(Note 6)
e
a
C
b
WS 39
(/2 t
RD
RW
DR
e
e
a
b
b
WS 14
(/2 t
85
0
C
*/4 t
15
Hold of Data Input Valid after RD Rising Edge
Bus Enable after RD Rising Edge
35
C
e
b
15
t
C
51
28
101
94
7
RDA
e
b
5
(/2 t
ALE Falling Edge to WR Falling Edge
WR Pulse Width
ARW
C
e
a
b
WS 15
*/4 t
WW
C
e
a
(/2 t
C
b
WS 5
Data Output Valid before WR Rising Edge
Hold of Data Valid after WR Rising Edge
V
e
b
10
(/4 t
HW
C
e
a
C
b
WS 50
t
t
(/4 t
Falling Edge of ALE to Falling Edge of RDY
RDY Pulse Width
33
ns
ns
DAR
e
t
C
66
RWP
e
Note: C
40 pF.
Note 1: These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO wih rise and fall
times (t and t ) on CKI input less than 2.5 ns.
L
CKIR
CKIL
Note 2: Do not design with these parameters unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3: t
HAE
edge occurs later, t
is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed. If HLD falling
a
a
a
100) may occur depending on the following CPU instruction cycles, its wait states and ready input.
C
as long as (3t
4WS
72 t
HAE
C
c
e
30 MHz,
Note 4: WS t
WAIT
with one wait state programmed.
(number of pre-programmed wait states). Minimum and maximum values are calculated from maximum operating frequency, t
C
Note 5: Due to emulation restrictionsÐactual limits will be better.
Note 6: This is guaranteed by design and not tested.
CKI Input Signal Characteristics
Rise/Fall Time
Duty Cycle
TL/DD/8801–36
TL/DD/8801–35
FIGURE 1. CKI Input Signal
TL/DD/8801–38
FIGURE 2. Input and Output for AC Tests
Note: AC testing inputs are driven at V for a logic ‘‘1’’ and V for a logic ‘‘0’’. Output timing measurements are made at 2.0V for a logic ‘‘1’’ and 0.8V for a logic
IH IL
‘‘0’’.
6
Timing Waveforms
TL/DD/8801–33
FIGURE 3. CKI, CK2, ALE Timing Diagram
TL/DD/8801–3
FIGURE 4. Write Cycle
TL/DD/8801–4
FIGURE 5. Read Cycle
TL/DD/8801–5
FIGURE 6. Ready Mode Timing
7
Timing Waveforms (Continued)
TL/DD/8801–6
FIGURE 7. Hold Mode Timing
TL/DD/8801–37
FIGURE 8. MICROWIRE Setup/Hold Timing
TL/DD/8801–9
FIGURE 9. UPI Read Timing
TL/DD/8801–10
FIGURE 10. UPI Write Timing
8
The following is the Military 883 Electrical Specification for HPC16083 and HPC16003. For latest information on RETS 16083X
contact NSC local sales office.
e
g
5V 10% (Unless Otherwise Specified) (Note 1)
DC Electrical Specifications Test Conditions V
CC
SBGRP 1 SBGRP 2 SBGRP 3
b
55 C
a
a
25 C
125 C
§
§
§
Min Max Min Max Min Max
Symbol
Parameter
Conditions
Units Notes
V
IH1
V
IH2
V
IH3
Logical ‘‘1’’ Input
Voltage
RESET, NMI, CKI and WO
–B , B
13 15
0.9 0.9 0.9
V
V
B
(V
)
)
(V
)
)
(V
)
)
10
All Inputs except Port A
CC
0.7
CC
0.7
CC
0.7
(V
CC
(V
CC
(V
CC
e
e
Port A, V
Port A, V
5.5V
4.5V
4.65
3.95
4.65
3.95
4.65
3.95
V
V
(Note 2)
(Note 2)
CC
CC
V
IL1
V
IL2
V
IL3
Logical ‘‘0’’ Input
Voltage
RESET, NMI, CKI and WO
0.1
0.1
0.1
V
V
(V
CC
0.2
)
)
(V
CC
0.2
)
)
(V
CC
0.2
)
)
All Inputs except Port A
(V
CC
0.7
(V
CC
0.7
(V
CC
0.7
e
e
Port A, V
Port A, V
5.5V
4.5V
V
V
(Note 3)
(Note 3)
CC
CC
0.5
0.5
0.5
e b
7 mA (A –A ,
0 15
–B , B , CK2)
12 15
V
V
Logical ‘‘1’’ Output
Voltage
I
B
I
OH2
OH
2.4
2.4
2.4
V
10
e b
P –P ), WO (Open Drain)
1.6 mA (B –B , B –B ,
13 14
OH3
OH3
0
9
2.4
2.4
2.4
2.4
2.4
2.4
V
V
0
3
e b
e b
V
V
I
I
6 mA (ST1, ST2)
1 mA (A –A , B –B , B
OH4
OH5
OH
OH
)
0
15 10 12 15
When Used as an External
Address/Data Bus
2.4
2.4
2.4
V
e
e
V
V
Logical ‘‘0’’ Output
Voltage
I
I
3 mA (CK2, A –A , B -B , B
0
)
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
V
V
OL2
OL3
OL
15 10 12 15
0.5 mA (B –B , B -B , P –P
13 14 3
OL
0
9
0
WO (Open Drain)
e
e
V
V
I
I
1.6 mA (ST1, ST2)
3 mA (A –A , B –B , B
OL4
OL5
OL
OL
)
0
15 10 12 15
When Used as an External
Address/Data Bus
0.4
0.4
0.4
V
s
Port B), V
s
V
I
I
TRI-STATE Leakage
V
SS
V
IN
(WO, Port A,
CC
5.5V
OZ
g
g
b
g
g
b
g
g
b
5
2
3
5
2
3
5
2
3
mA
e
CC
s
s
V
(I –I , D –D , CKI,
e
5.5V
Input Leakage
Current
V
V
, V
LI1
SS
IN
CC CC
mA (Note 7)
1
6
0
7
RESET, EXM, EI)
e
I
I
Input Pullup Current
V
0 (I , I , RDY/HLD,
0
LI2
LI3
IN
EXUI), V
7
b
b
b
50
50
50
mA (Note 7)
e
5.5V
CC
e
Port B Pulldown
12
during Reset
V
V
V
CC
5.5V
, Port B ,
12
IN
1
7
1
7
1
7
mA
V
e
CC
VRAM RAM Keep Alive
Voltage
Test Duration is 10 ms
2.5
2.5
2.5
e
e
e
V
0 mA, V
I
Supply Current
Dynamic
F
20 MHz, RESET
e
,
CC1
IN
SS
CC
55
55
55
mA
e
5.5V
I
0 mA, I
OL
OH
e
I
I
Idle Mode Current
Halt Mode Current
F
20 MHz, External Clock
3.5
2
3.5
2
3.5
2
mA
mA
CC2
CC
IN
e
NMI
V
CC
1.0 MHz,
I/O Pin to Ground
e
CI/O
Input/Output
Capacitance
f
test
20
pF (Note 4)
SBGRP4
e
Input Pin to Ground
CI
Input Capacitance
f
1.0 MHz,
test
10
pF (Note 4)
Note 1: Electrical end point testing (when required) for Groups C & D shall consist only of subgroups 1, 2, 9 and 10.
Note 2: Port A V test limit includes 700 mV offset caused by output loads being on during Data Drive Time.
IH
Note 3: Port A V test limit includes 400 mV offset caused by output loads being on during Data Drive Time.
IL
Note 4: Verified at initial qual only.
Note 7: Future revisions of this device will not have pullups on pins I , I which will be tested to I conditions.
LI1
0
7
9
e
AC Electrical Specifications Test Conditions V
4.5V and 5.5V (Unless Otherwise Specified) (Note 1)
SBGRP 9 SBGRP 10 SBGRP 11
CC
a
a
b
55 C
25 C
§
125 C
§
§
Symbol
Parameter
Conditions
Units Notes
Min Max Min Max
Min
Max
e
e
e
e
f
t
t
t
t
CKI Freq.
Operating Frequency
Clock Period
2
20
2
20
2
20
MHz (Note 5)
C
1/FC
2/FC
50
50
50
ns
ns
ns
(Note 5)
(Note 5)
(Note 6)
CI
C
Timing Cycle
100
41
100
41
100
41
b
b
(/2 t
9
7
ALE Pulse Width
LL
C
e
(/4 t
Address Valid to
ALE Falling Edge
ST
C
18
18
18
ns
ns
(Note 6)
(Note 5)
e
e
e
t
t
WS
Wait State Period
100
100
100
WAIT
C
FMW
0.0625 f
External MICROWIRE/PLUS
CLK Input Frequency
C
1.25
1.25
1.25
MHz (Note 6)
MHz (Note 5)
e
f
U
0.125 f
External UART
C
2.5
55
2.5
55
2.5
55
Clock Input Frequency
t
t
CK2 Delay From CK1
ns
ns
(Note 6)
(Note 6)
DCIC2
e
b
5
(/4 t
ALE Falling Edge
to RD Falling Edge
ARR
C
20
140
0
20
140
0
20
140
0
e
t
t
(/2
RD Pulse Width
RW
ns
ns
ns
ns
ns
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
a
b
WS 10
C
e
b
15
t
3.4 t
Data Hold after
DR
C
60
85
60
85
60
85
Rising Edge of RD
e
t
t
(/2
RD Falling Edge to
Data in Valid
RD
a
b
WS 65
C
e
b
15
t
t
t
t
C
RD Rising Edge to
Address Valid
RDA
85
20
85
20
85
20
e
b
(/4 t
C
5
Address Hold from
ALE Falling Edge
VP
e
b
(/2 t
5
ALE Trailing Edge
to WR Falling Edge
ARW
C
45
160
20
45
160
20
45
160
20
ns
ns
ns
(Note 6)
(Note 6)
(Note 6)
e
a b
WS 15 WR Pulse Width
t
t
*/4 t
WW
C
e
b
5
(/4 t
Data Hold after
HW
C
Trailing Edge of WR
e
a
C
b
WS 5
t
t
(/2 t
Data Valid before
Rising Edge of WR
V
145
145
145
ns
ns
(Note 6)
(Note 6)
e
a
(/4 t
C
b
WS 50 Falling Edge of ALE
DAR
75
75
75
to Falling Edge of RDY
10
e
AC Electrical Specifications Test Conditions V
4.5V and 5.5V (Unless Otherwise Specified) (Note 1)
CC
(Continued)
SBGRP 9
a
SBGRP 10
a
SBGRP 11
b
55 C
25 C
§
125 C
§
§
Symbol
Parameter
Conditions
Units Notes
Min
Max
Min
Max
Min
Max
e
e
t
t
t
RDY Pulse Width
100
115
110
100
115
110
100
115
110
ns
ns
ns
ns
(Note 6)
(Note 6)
(Note 6)
(Note 6)
RWP
C
a
*/4 t
40 Falling Edge of HLD to
to Rising Edge of ALE
SALE
C
e
e
a
10
t
t
t
C
HLD Pulse Width
HWP
a
*/4 t
85
Rising Edge on HLD to
Rising Edge on HLDA
HAD
C
160
200
116
160
200
116
160
200
116
e
a
100
t
t
t
t
t
t
Falling Edge on HLD to
Falling Edge on HLDA
HAE
C
ns
ns
ns
ns
(Note 6)
(Note 6)
(Note 6)
(Note 6)
e
a
C
(/2 t
66
66
BUS Float before
BF
BE
Falling Edge on HLDA
e
a
(/2 t
BUS Enable from
C
116
10
116
10
116
10
Rising Edge of HLDA
Address Setup Time to
Falling Edge of URD
UAS
UAH
Address Hold Time from
Rising Edge of URD
10
10
10
ns
ns
ns
(Note 6)
(Note 6)
(Note 6)
t
t
URD Pulse Width
100
100
100
RPW
URD Falling Edge to
Data Out Valid
OE
60
70
60
70
60
70
t
RDY Delay from
RDRDY
ns
ns
ns
(Note 6)
(Note 6)
(Note 6)
Rising Edge of URD
t
t
UWR Pulse Width
40
10
40
10
40
10
WDW
Data Invalid before
UDS
Trailing Edge of UWR
t
Data In Hold after
UDH
A
15
15
15
ns
ns
(Note 6)
(Note 6)
Rising Edge of UWR
t
WRRDY Delay from
Rising Edge of UWR
70
70
70
Note 1: Electrical end point testing (when required) for groups C & D shall consist only of subgroups 1, 2, 9 and 10.
Note 5: Tested in functional patterns. Not directly measured.
e
Note 6: C
70 pF. Input and output levels are per DC characteristics.
L
Pin Descriptions
The HPC16083 is available in 68-pin PLCC, LDCC, PGA,
and 80-pin PQFP packages.
B0: TDX
B1:
UART Data Output
B2: CKX
B3: T2IO
B4: T3IO
B5: SO
B6: SK
B7: HLDA
B8: TS0
B9: TS1
B10: UA0
UART Clock (Input or Output)
Timer2 I/O Pin
I/O PORTS
Port A is a 16-bit bidirectional I/O port with a data direction
register to enable each separate pin to be individually de-
fined as an input or output. When accessing external memo-
ry, port A is used as the multiplexed address/data bus.
Timer3 I/O Pin
MICROWIRE/PLUS Output
MICROWIRE/PLUS Clock (Input or Output)
Hold Acknowledge Output
Port B is a 16-bit port with 12 bits of bidirectional I/O similar
in structure to Port A. Pins B10, B11, B12 and B15 are gen-
eral purpose outputs only in this mode. Port B may also be
configured via a 16-bit function register BFUN to individually
allow each pin to have an alternate function.
Timer Synchronous Output
Timer Synchronous Output
Address 0 Input for UPI Mode
B11: WRRDY Write Ready Output for UPI Mode
B12:
B13: TS2
Timer Synchronous Output
11
Pin Descriptions (Continued)
RDY/HLD has two uses, selected by a software bit. It’s ei-
ther a READY input to extend the bus cycle for
slower memories, or a HOLD request input to put
the bus in a high impedance state for DMA pur-
poses.
B14:
TS3
Timer Synchronous Output
B15:
RDRDY
Read Ready Output for UPI Mode
When accessing external memory, four bits of port B
are used as follows:
B10:
B11:
B12:
ALE
WR
Address Latch Enable Output
Write Output
NC
EXM
EI
(no connection) do not connect anything to this
pin.
HBE
High Byte Enable Output/Input
(sampled at reset)
External memory enable (active high) disables
internal ROM and maps it to external memory.
B15:
RD
Read Output
External
interrupt
with
vector
address
Port I is an 8-bit input port that can be read as general
purpose inputs and is also used for the following functions:
FFF1:FFF0. (Rising/falling edge or high/low lev-
el sensitive). Alternately can be configured as
4th input capture.
I0:
EXUI
External interrupt which is internally OR’ed with
the UART interrupt with vector address
FFF3:FFF2 (Active Low).
I1:
I2:
I3:
I4:
I5:
I6:
I7:
NMI
INT2
INT3
INT4
SI
Nonmaskable Interrupt Input
Maskable Interrupt/Input Capture/URD
Maskable Interrupt/Input Capture/UWR
Maskable Interrupt/Input Capture
MICROWIRE/PLUS Data Input
UART Data Input
Connection Diagrams
RDX
Plastic and Ceramic Leaded Chip Carriers
Port D is an 8-bit input port that can be used as general
purpose digital inputs.
Port P is a 4-bit output port that can be used as general
purpose data, or selected to be controlled by timers 4
through 7 in order to generate frequency, duty cycle and
pulse width modulated outputs.
POWER SUPPLY PINS
V
CC1
V
CC2
and
Positive Power Supply
GND
DGND
Ground for On-Chip Logic
Ground for Output Buffers
Note: There are two electrically connected V
DGND are electrically isolated. Both V
must be used.
pins on the chip, GND and
pins and both ground pins
CC
CC
CLOCK PINS
CKI
The Chip System Clock Input
The Chip System Clock Output (inversion of CKI)
CKO
Pins CKI and CKO are usually connected across an external
crystal.
TL/DD/8801–11
Top View
CK2
Clock Output (CKI divided by 2)
See NS Package Number EL68A or V68A
See Part Selection for Ordering Information
OTHER PINS
WO
This is an active low open drain output that sig-
nals an illegal situation has been detected by the
Watch Dog logic.
ST1
Bus Cycle Status Output: indicates first opcode
fetch.
ST2
Bus Cycle Status Output: indicates machine
states (skip, interrupt and first instruction cycle).
RESET
is an active low input that forces the chip to re-
start and sets the ports in a TRI-STATE mode.
12
Connection Diagrams (Continued)
Plastic Quad Flatpack
TL/DD/8801–34
Top View
See NS Package Number VJE80A
See Part Selection for Ordering Information
Pin Grid Array Pinout
TL/DD/8801–12
Top View
(looking down on component side of PC Board)
See NS Package Number U68A
See Part Selection for Ordering Information
13
Ports A & B
The highly flexible A and B ports are similarly structured.
The Port A (see Figure 11), consists of a data register and a
direction register. Port B (see Figures 12, 13, 14) has an
alternate function register in addition to the data and direc-
tion registers. All the control registers are read/write regis-
ters.
A write operation to a port pin configured as an input causes
the value to be written into the data register, a read opera-
tion returns the value of the pin. Writing to port pins config-
ured as outputs causes the pins to have the same value,
reading the pins returns the value of the data register.
Primary and secondary functions are multiplexed onto Port
B through the alternate function register (BFUN). The sec-
ondary functions are enabled by setting the corresponding
bits in the BFUN register.
The associated direction registers allow the port pins to be
individually programmed as inputs or outputs. Port pins se-
lected as inputs, are placed in a TRI-STATE mode by reset-
ting corresponding bits in the direction register.
TL/DD/8801–13
FIGURE 11. Port A: I/O Structure
TL/DD/8801–14
FIGURE 12. Structure of Port B Pins B0, B1, B2, B5, B6 and B7 (Typical Pins)
14
Ports A & B (Continued)
TL/DD/8801–15
FIGURE 13. Structure of Port B Pins B3, B4, B8, B9, B13 and B14 (Timer Synchronous Pins)
TL/DD/8801–16
FIGURE 14. Structure of Port B Pins B10, B11, B12 and B15 (Pins with Bus Control Roles)
15
ROM) on-chip. It can address internal memory only, consist-
ing of 8k bytes of ROM (E000 to FFFF) and 256 bytes of on-
chip RAM and registers (0000 to 01FF). The ‘‘illegal address
detection’’ feature of the WATCHDOG is enabled in the Sin-
gle-Chip Normal mode and a WATCHDOG Output (WO) will
occur if an attempt is made to access addresses that are
outside of the on-chip ROM and RAM range of the device.
Ports A and B are used for I/O functions and not for ad-
dressing external memory. The EXM pin and the EA bit of
the PSW register must both be logic ‘‘0’’ to enter the Single-
Chip Normal mode.
Operating Modes
To offer the user a variety of I/O and expanded memory
options, the HPC16083 has four operating modes. The
ROMless HPC16003 has one mode of operation. The vari-
ous modes of operation are determined by the state of both
the EXM pin and the EA bit in the PSW register. The state of
the EXM pin determines whether on-chip ROM will be ac-
cessed or external memory will be accessed within the ad-
dress range of the on-chip ROM. The on-chip ROM range of
the HPC16083 is E000 to FFFF (8k bytes). The HPC16003
has no on-chip ROM and is intended for use with external
memory for program storage. A logic ‘‘0’’ state on the EXM
pin will cause the HPC device to address on-chip ROM
when the Program Counter (PC) contains addresses within
the on-chip ROM address range. A logic ‘‘1’’ state on the
EXM pin will cause the HPC device to address memory that
is external to the HPC when the PC contains on-chip ROM
addresses. The EXM pin should always be pulled high (logic
‘‘1’’) on the HPC16003 because no on-chip ROM is avail-
able. The function of the EA bit is to determine the legal
addressing range of the HPC device. A logic ‘‘0’’ state in the
EA bit of the PSW register does two thingsÐaddresses are
limited to the on-chip ROM range and on-chip RAM and
Register range, and the ‘‘illegal address detection’’ feature
of the WATCHDOG logic is engaged. A logic ‘‘1’’ in the EA
bit enables accesses to be made anywhere within the 64k
byte address range and the ‘‘illegal address detection’’ fea-
ture of the WATCHDOG logic is disabled. The EA bit should
be set to ‘‘1’’ by software when using the HPC16003 to
disable the ‘‘illegal address detection’’ feature of WATCH-
DOG.
EXPANDED NORMAL MODE
The Expanded Normal mode of operation enables the
HPC16083 to address external memory in addition to the
on-chip ROM and RAM (see Table I). WATCHDOG illegal
address detection is disabled and memory accesses may
be made anywhere in the 64k byte address range without
triggering an illegal address condition. The Expanded Nor-
mal mode is entered with the EXM pin pulled low (logic ‘‘0’’)
and setting the EA bit in the PSW register to ‘‘1’’.
SINGLE-CHIP ROMLESS MODE
In this mode, the on-chip mask programmed ROM of the
HPC16083 is not used. The address space corresponding
to the on-chip ROM is mapped into external memory so 8k
bytes of external memory may be used with the HPC16083
(see Table I). The WATCHDOG circuitry detects illegal ad-
dresses (addresses not within the on-chip ROM and RAM
range). The Single-Chip ROMless mode is entered when the
EXM pin is pulled high (logic ‘‘1’’) and the EA bit is logic ‘‘0’’.
EXPANDED ROMLESS MODE
All HPC devices can be used with external memory. Exter-
nal memory may be any combination of RAM and ROM.
Both 8-bit and 16-bit external data bus modes are available.
Upon entering an operating mode in which external memory
is used, port A becomes the Address/Data bus. Four pins of
port B become the control lines ALE, RD, WR and HBE. The
High Byte Enable pin (HBE) is used in 16-bit mode to select
high order memory bytes. The RD and WR signals are only
generated if the selected address is off-chip. The 8-bit mode
is selected by pulling HBE high at reset. If HBE is left float-
ing or connected to a memory device chip select at reset,
the 16-bit mode is entered. The following sections describe
the operating modes of the HPC16083 and HPC16003.
This mode of operation is similar to Single-Chip ROMless
mode in that no on-chip ROM is used, however, a full 64k
bytes of external memory may be used. The ‘‘illegal address
detection’’ feature of WATCHDOG is disabled. The EXM pin
must be pulled high (logic ‘‘1’’) and the EA bit in the PSW
register set to ‘‘1’’ to enter this mode.
TABLE I. HPC16083 Operating Modes
Operating
Mode
EXM EA
Bit
Memory
Configuration
Pin
Single-Chip Normal
Expanded Normal
0
0
E000:FFFF on-chip
0
1
E000:FFFF on-chip
0200:DFFF off-chip
Note: The HPC devices use 16-bit words for stack memory. Therefore,
when using the 8-bit mode, User’s Stack must be in internal RAM.
Single-Chip ROMless
Expanded ROMless
1
1
0
1
E000:FFFF off-chip
0200:FFFF off-chip
HPC16083 Operating Modes
SINGLE CHIP NORMAL MODE
Note: In all operating modes, the on-chip RAM and Registers (0000:01FF)
may be accessed.
In this mode, the HPC16083 functions as a self-contained
microcomputer (see Figure 15) with all memory (RAM and
16
HPC16003 Operating Modes
EXPANDED ROMLESS MODE (HPC16003)
Because the HPC16003 has no on-chip ROM, it has only
one mode of operation, the Expanded ROMless Mode. The
EXM pin must be pulled high (logic ‘‘1’’) on power up, the
EA bit in the PSW register should be set to a ‘‘1’’. The
HPC16003 is a ROMless device and is intended for use with
external memory. The external memory may be any combi-
nation of ROM and RAM. Up to 64k bytes of external mem-
ory may be accessed. It is necessary to vector on reset to
an address between F000 and FFFF, therefore the user
should have external memory at these addresses. The EA
bit in the PSW register must immediately be set to ‘‘1’’ at the
beginning of the user’s program to disable illegal address
detection in the WATCHDOG logic.
TL/DD/8801–17
TABLE II. HPC16003 Operating Modes
FIGURE 15. Single-Chip Mode
Operating
Mode
EXM EA
Memory
Pin
Bit
Configuration
Expanded ROMless
1
1
0200:FFFF off-chip
Note: The on-chip RAM and Registers (0000:01FF) of the HPC16003 may
be accessed at all times.
TL/DD/8801–18
FIGURE 16. 8-Bit External Memory
17
HPC16003 Operating Modes (Continued)
TL/DD/8801–19
FIGURE 17. 16-Bit External Memory
IDLE MODE
Wait States
The internal ROM can be accessed at the maximum operat-
The HPC16083 is placed in the IDLE mode through the
PSW. In this mode, all processor activity, except the on-
board oscillator and Timer T0, is stopped. As with the HALT
mode, the processor is returned to full operation by the
RESET or NMI inputs, but without waiting for oscillator stabi-
lization. A timer T0 overflow will also cause the HPC16083
to resume normal operation.
ing frequency with one wait state. With 0 wait states, internal
ROM accesses are limited to )/3 f max.
C
The HPC16083 provides four software selectable Wait
States that allow access to slower memories. The Wait
States are selected by the state of two bits in the PSW
register. Additionally, the RDY input may be used to extend
the instruction cycle, allowing the user to interface with slow
memories and peripherals.
HPC16083 Interrupts
Complex interrupt handling is easily accomplished by the
HPC16083’s vectored interrupt scheme. There are eight
possible interrupt sources as shown in Table III.
Power Save Modes
Two power saving modes are available on the HPC16083:
HALT and IDLE. In the HALT mode, all processor activities
are stopped. In the IDLE mode, the on-board oscillator and
timer T0 are active but all other processor activities are
stopped. In either mode, all on-board RAM, registers and
I/O are unaffected.
TABLE III. Interrupts
Vector
Interrupt
Source
Arbitration
Ranking
Address
FFFF:FFFE
RESET
0
1
FFFD:FFFC Nonmaskable external on
rising edge of I1 pin
HALT MODE
The HPC16083 is placed in the HALT mode under software
control by setting bits in the PSW. All processor activities,
including the clock and timers, are stopped. In the HALT
mode, power requirements for the HPC16083 are minimal
FFFB:FFFA
FFF9:FFF8
FFF7:FFF6
FFF5:FFF4
FFF3:FFF2
External interrupt on I2 pin
External interrupt on I3 pin
External interrupt on I4 pin
Overflow on internal timers
2
3
4
5
and the applied voltage (V ) may be decreased without
CC
altering the state of the machine. There are two ways of
exiting the HALT mode: via the RESET or the NMI. The
RESET input reinitializes the processor. Use of the NMI in-
put will generate a vectored interrupt and resume operation
from that point with no initialization. The HALT mode can be
enabled or disabled by means of a control register HALT
enable. To prevent accidental use of the HALT mode the
HALT enable register can be modified only once.
Internal on the UART
transmit/receive complete
or external on EXUI
6
7
FFF1:FFF0
External interrupt on EI pin
18
interrupts may be disabled. IRPD is a Read/Write register.
The bits corresponding to the maskable, external interrupts
are normally cleared by the HPC16083 after servicing the
interrupts.
Interrupt Arbitration
The HPC16083 contains arbitration logic to determine which
interrupt will be serviced first if two or more interrupts occur
simultaneously. The arbitration ranking is given in Table III.
The interrupt on RESET has the highest rank and is serv-
iced first.
For the interrupts from the on-board peripherals, the user
has the responsibility of resetting the interrupt pending flags
through software.
The NMI bit is read only and I2, I3, and I4 are designed as to
only allow a zero to be written to the pending bit (writing a
one has no affect). A LOAD IMMEDIATE instruction is to be
the only instruction used to clear a bit or bits in the IRPD
register. This allows a mask to be used, thus ensuring that
the other pending bits are not affected.
Interrupt Processing
Interrupts are serviced after the current instruction is com-
pleted except for the RESET, which is serviced immediately.
RESET and EXUI are level-LOW-sensitive interrupts and EI
is programmable for edge-(RISING or FALLING) or level-
(HIGH or LOW) sensitivity. All other interrupts are edge-sen-
sitive. NMI is positive-edge sensitive. The external interrupts
on I2, I3 and I4 can be software selected to be rising or
falling edge. External interrupt (EXUI) is shared with the
UART interrupt. This interrupt is level-low sensitive. To se-
lect this interrupt disable the ERI and ETI UART interrupt
bits in the ENUI register. To select the UART interrupt leave
this pin floating or tie it high.
INTERRUPT CONDITION REGISTER (IRCD)
Three bits of the register select the input polarity of the
external interrupt on I2, I3, and I4.
Servicing the Interrupts
The Interrupt, once acknowledged, pushes the program
counter (PC) onto the stack thus incrementing the stack
pointer (SP) twice. The Global Interrupt Enable bit (GIE) is
copied into the CGIE bit of the PSW register; it is then reset,
thus disabling further interrupts. The program counter is
loaded with the contents of the memory at the vector ad-
dress and the processor resumes operation at this point. At
the end of the interrupt service routine, the user does a
RETI instruction to pop the stack and re-enable interrupts if
the CGIE bit is set, or RET to just pop the stack if the CGIE
bit is clear, and then returns to the main program. The GIE
bit can be set in the interrupt service routine to nest inter-
rupts if desired. Figure 18 shows the Interrupt Enable Logic.
Interrupt Control Registers
The HPC16083 allows the various interrupt sources and
conditions to be programmed. This is done through the vari-
ous control registers. A brief description of the different con-
trol registers is given below.
INTERRUPT ENABLE REGISTER (ENIR)
RESET and the External Interrupt on I1 are non-maskable
interrupts. The other interrupts can be individually enabled
or disabled. Additionally, a Global Interrupt Enable Bit in the
ENIR Register allows the Maskable interrupts to be collec-
tively enabled or disabled. Thus, in order for a particular
interrupt to request service both the individual enable bit
and the Global Interrupt bit (GIE) have to be set.
RESET
The RESET input initializes the processor and sets ports A
and B in the TRI-STATE condition and port P in the LOW
state. RESET is an active-low Schmitt trigger input. The
processor vectors to FFFF:FFFE and resumes operation at
the address contained at that memory location (which must
correspond to an on board location). The Reset vector ad-
dress must be between E000 and FFFF when using the
HPC16003.
INTERRUPT PENDING REGISTER (IRPD)
The IRPD register contains a bit allocated for each interrupt
vector. The occurrence of specified interrupt trigger condi-
tions causes the appropriate bit to be set. There is no indi-
cation of the order in which the interrupts have been re-
ceived. The bits are set independently of the fact that the
19
20
Timer Overview
The HPC16083 contains a powerful set of flexible timers
enabling the HPC16083 to perform extensive timer func-
tions; not usually associated with microcontrollers.
software control. Once enabled, the timers count down, and
upon underflow, the contents of its associated register are
automatically loaded into the timer.
The HPC16083 contains nine 16-bit timers. Timer T0 is a
free-running timer, counting up at a fixed CKI/16 (Clock In-
put/16) rate. It is used for WATCHDOG logic, high speed
event capture, and to exit from the IDLE mode. Conse-
quently, it cannot be stopped or written to under software
control. Timer T0 permits precise measurements by means
of the capture registers I2CR, I3CR, and I4CR. A control bit
in the register TMMODE configures timer T1 and its associ-
ated register R1 as capture registers I3CR and I2CR. The
capture registers I2CR, I3CR, and I4CR respectively, record
the value of timer T0 when specific events occur on the
interrupt pins I2, I3, and I4. The control register IRCD pro-
grams the capture registers to trigger on either a rising edge
or a falling edge of its respective input. The specified edge
can also be programmed to generate an interrupt (see Fig-
ure 19).
The HPC16083 provides an additional 16-bit free running
timer, T8, with associated input capture register EICR (Ex-
ternal Interrupt Capture Register) and Configuration Regis-
ter, EICON. EICON is used to select the mode and edge of
the EI pin. EICR is a 16-bit capture register which records
the value of T8 (which is identical to T0) when a specific
event occurs on the EI pin.
TL/DD/8801–21
FIGURE 19. Timers T0, T1 and T8
with Four Input Capture Registers
The timers T2 and T3 have selectable clock rates. The
clock input to these two timers may be selected from the
following two sources: an external pin, or derived internally
by dividing the clock input. Timer T2 has additional capabili-
ty of being clocked by the timer T3 underflow. This allows
the user to cascade timers T3 and T2 into a 32-bit timer/
counter. The control register DIVBY programs the clock in-
put to timers T2 and T3 (see Figure 20).
SYNCHRONOUS OUTPUTS
The flexible timer structure of the HPC16083 simplifies
pulse generation and measurement. There are four syn-
chronous timer outputs (TS0 through TS3) that work in con-
junction with the timer T2. The synchronous timer outputs
can be used either as regular outputs or individually pro-
grammed to toggle on timer T2 underflows (see Figure 20).
The timers T1 through T7 in conjunction with their registers
form Timer-Register pairs. The registers hold the pulse du-
ration values. All the Timer-Register pairs can be read from
or written to. Each timer can be started or stopped under
Timer/register pairs 4–7 form four identical units which can
generate synchronous outputs on port P (see Figure 21).
TL/DD/8801–22
FIGURE 20. Timers T2–T3 Block
21
Timer Overview (Continued)
TL/DD/8801–25
FIGURE 23. Synchronous Pulse Generation
TL/DD/8801–23
WATCHDOG register not be written to before Timer T0
overflows twice, or more often than once every 4096
counts, an infinite loop condition is assumed to have oc-
curred. An illegal condition also occurs when the processor
generates an illegal address when in the Single-Chip
modes.* Any illegal condition forces the WATCHDOG Out-
put (WO) pin low. The WO pin is an open drain output and
can be connected to the RESET or NMI inputs or to the
users external logic.
FIGURE 21. Timers T4–T7 Block
Maximum output frequency for any timer output can be ob-
tained by setting timer/register pair to zero. This then will
produce an output frequency equal to (/2 the frequency of
the source used for clocking the timer.
Timer Registers
There are four control registers that program the timers. The
divide by (DIVBY) register programs the clock input to tim-
ers T2 and T3. The timer mode register (TMMODE) contains
control bits to start and stop timers T1 through T3. It also
contains bits to latch, acknowledge and enable interrupts
from timers T0 through T3. The control register PWMODE
similarly programs the pulse width timers T4 through T7 by
allowing them to be started, stopped, and to latch and en-
able interrupts on underflows. The PORTP register contains
bits to preset the outputs and enable the synchronous timer
output functions.
*Note: See Operating Modes for details.
MICROWIRE/PLUS
MICROWIRE/PLUS is used for synchronous serial data
communications (see Figure 24). MICROWIRE/PLUS has
an 8-bit parallel-loaded, serial shift register using SI as the
input and SO as the output. SK is the clock for the serial
shift register (SIO). The SK clock signal can be provided by
an internal or external source. The internal clock rate is pro-
grammable by the DIVBY register. A DONE flag indicates
when the data shift is completed.
Timer Applications
The use of Pulse Width Timers for the generation of various
waveforms is easily accomplished by the HPC16083.
Frequencies can be generated by using the timer/register
pairs. A square wave is generated when the register value is
a constant. The duty cycle can be controlled simply by
changing the register value.
TL/DD/8801–24
FIGURE 22. Square Wave Frequency Generation
Synchronous outputs based on Timer T2 can be generated
on the 4 outputs TS0–TS3. Each output can be individually
programmed to toggle on T2 underflow. Register R2 con-
tains the time delay between events. Figure 23 is an exam-
ple of synchronous pulse train generation.
WATCHDOG Logic
TL/DD/8801–26
The WATCHDOG Logic monitors the operations taking
place and signals upon the occurrence of any illegal activity.
The illegal conditions that trigger the WATCHDOG logic are
potentially infinite loops and illegal addresses. Should the
FIGURE 24. MICROWIRE/PLUS
The MICROWIRE/PLUS capability enables it to interface
with any of National Semiconductor’s MICROWIRE periph-
erals (i.e., A/D converters, display drivers, EEPROMs).
22
tem could be used to interface to an instrument cluster and
various parts of the automobile. The diagram shows two
HPC16083 microcontrollers interconnected to other MI-
MICROWIRE/PLUS Operation
The HPC16083 can enter the MICROWIRE/PLUS mode as
the master or a slave. A control bit in the IRCD register
determines whether the HPC16083 is the master or slave.
The shift clock is generated when the HPC16083 is config-
ured as a master. An externally generated shift clock on the
SK pin is used when the HPC16083 is configured as a slave.
When the HPC16083 is a master, the DIVBY register pro-
grams the frequency of the SK clock. The DIVBY register
allows the SK clock frequency to be programmed in 15 se-
lectable steps from 64 Hz to 1 MHz with CKI at 16.0 MHz.
Ý
CROWIRE peripherals. HPC16083 1 is set up as the mas-
ter and initiates all data transfers. HPC16083 2 is set up
Ý
as a slave answering to the master.
The master microcontroller interfaces the operator with the
system and could also manage the instrument cluster in an
automotive application. Information is visually presented to
the operator by means of a LCD display controlled by the
COP472 display driver. The data to be displayed is sent
serially to the COP472 over the MICROWIRE/PLUS link.
Data such as accumulated mileage could be stored and re-
trieved from the EEPROM COP494. The slave HPC16083
could be used as a fuel injection processor and generate
timing signals required to operate the fuel valves. The mas-
ter processor could be used to periodically send updated
values to the slave via the MICROWIRE/PLUS link. To
speed up the response, chip select logic is implemented by
connecting an output from the master to the external inter-
rupt input on the slave.
The contents of the SIO register may be accessed through
any of the memory access instructions. Data waiting to be
transmitted in the SIO register is clocked out on the falling
edge of the SK clock. Serial data on the SI pin is clocked in
on the rising edge of the SK clock.
MICROWIRE/PLUS Application
Figure 25 illustrates a MICROWIRE/PLUS arrangement for
an automotive application. The microcontroller-based sys-
TL/DD/8801–27
FIGURE 25. MICROWIRE/PLUS Application
23
HPC16083 UART
The HPC16083 contains a software programmable UART.
The UART (see Figure 26) consists of a transmit shift regis-
ter, a receiver shift register and five addressable registers,
as follows: a transmit buffer register (TBUF), a receiver buff-
er register (RBUF), a UART control and status register
(ENU), a UART receive control and status register (ENUR)
and a UART interrupt and clock source register (ENUI). The
ENU register contains flags for transmit and receive func-
tions; this register also determines the length of the data
frame (8 or 9 bits) and the value of the ninth bit in transmis-
sion. The ENUR register flags framing and data overrun er-
rors while the UART is receiving. Other functions of the
ENUR register include saving the ninth bit received in the
data frame and enabling or disabling the UART’s Wake-up
Mode of operation. The determination of an internal or ex-
ternal clock source is done by the ENUI register, as well as
selecting the number of stop bits and enabling or disabling
transmit and receive interrupts.
The baud rate clock for the Receiver and Transmitter can
be selected for either an internal or external source using
two bits in the ENUI register. The internal baud rate is pro-
grammed by the DIVBY register. The baud rate may be se-
lected from a range of 8 Hz to 128 kHz in binary steps or T3
underflow. By selecting a 9.83 MHz crystal, all standard
baud rates from 75 baud to 38.4 kBaud can be generated.
The external baud clock source comes from the CKX pin.
The Transmitter and Receiver can be run at different rates
by selecting one to operate from the internal clock and the
other from an external source.
The HPC16083 UART supports two data formats. The first
format for data transmission consists of one start bit, eight
data bits and one or two stop bits. The second data format
for transmission consists of one start bit, nine data bits, and
one or two stop bits. Receiving formats differ from transmis-
sion only in that the Receiver always requires only one stop
bit in a data frame.
UART Wake-up Mode
The HPC16083 UART features a Wake-up Mode of opera-
tion. This mode of operation enables the HPC16083 to be
networked with other processors. Typically in such environ-
ments, the messages consist of addresses and actual data.
Addresses are specified by having the ninth bit in the data
frame set to 1. Data in the message is specified by having
the ninth bit in the data frame reset to 0.
The UART monitors the communication stream looking for
addresses. When the data word with the ninth bit set is
received, the UART signals the HPC16083 with an interrupt.
The processor then examines the content of the receiver
buffer to decide whether it has been addressed and whether
to accept subsequent data.
TL/DD/8801–28
FIGURE 26. UART Block Diagram
24
The host uses DMA to interface with the HPC16083. The
host initiates a data transfer by activating the HLD input of
the HPC16083. In response, the HPC16083 places its sys-
tem bus in a TRI-STATE Mode, freeing it for use by the host.
The host waits for the acknowledge signal (HLDA) from the
HPC16083 indicating that the sytem bus is free. On receiv-
ing the acknowledge, the host can rapidly transfer data into,
or out of, the shared memory by using a conventional DMA
controller. Upon completion of the message transfer, the
host removes the HOLD request and the HPC16083 re-
sumes normal operations.
Universal Peripheral Interface
The Universal Peripheral Interface (UPI) allows the
HPC16083 to be used as an intelligent peripheral to another
processor. The UPI could thus be used to tightly link two
HPC16083’s and set up systems with very high data ex-
change rates. Another area of application could be where a
HPC16083 is programmed as an intelligent peripheral to a
host system such as the Series 32000 microprocessor.
É
Figure 27 illustrates how a HPC16083 could be used an an
intelligent peripherial for a Series 32000-based application.
The interface consists of a Data Bus (port A), a Read Strobe
(URD), a Write Strobe (UWR), a Read Ready Line (RDRDY),
a Write Ready Line (WRRDY) and one Address Input (UA0).
The data bus can be either eight or sixteen bits wide.
Figure 28 illustrates an application of the shared memory
interface between the HPC16083 and a Series 32000 sys-
tem. To insure proper operation, the interface logic shown is
recommended as the means for enabling and disabling the
user’s bus.
The URD and UWR inputs may be used to interrupt the
HPC16083. The RDRDY and WRRDY outputs may be used
to interrupt the host processor.
Memory
The UPI contains an Input Buffer (IBUF), an Output Buffer
(OBUF) and a Control Register (UPIC). In the UPI mode,
port A on the HPC16083 is the data bus. UPI can only be
used if the HPC16083 is in the Single-Chip mode.
The HPC16083 has been designed to offer flexibility in
memory usage. A total address space of 64 kbytes can be
addressed with 8 kbytes of ROM and 256 bytes of RAM
available on the chip itself. The ROM may contain program
instructions, constants or data. The ROM and RAM share
the same address space allowing instructions to be execut-
ed out of RAM.
Shared Memory Support
Shared memory access provides a rapid technique to ex-
change data. It is effective when data is moved from a pe-
ripheral to memory or when data is moved between blocks
of memory. A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block. The HPC16083
supports shared memory access with two pins. The pins are
the RDY/HLD input pin and the HLDA output pin. The user
can software select either the Hold or Ready function by the
state of a control bit. The HLDA output is multiplexed onto
port B.
Program memory addressing is accomplished by the 16-bit
program counter on a byte basis. Memory can be addressed
directly by instructions or indirectly through the B, X and SP
registers. Memory can be addressed as words or bytes.
Words are always addressed on even-byte boundaries. The
HPC16083 uses memory-mapped organization to support
registers, I/O and on-chip peripheral functions.
The HPC16083 memory address space extends to 64
kbytes and registers and I/O are mapped as shown in Table
IV.
TL/DD/8801–29
FIGURE 27. HPC16083 as a Peripheral: (UPI Interface to Series 32000 Application)
25
Shared Memory Support (Continued)
TL/DD/8801–30
FIGURE 28. Shared Memory Application: HPC16083 Interface to Series 32000 System
TABLE IV. HPC16083 Memory Map
FFFF:FFF0 Interrupt Vectors
FFEF:FFD0 JSRP Vectors
FFCF:FFCE
0128
0126
0124
0122
ENUR Register
TBUF Register
RBUF Register
ENUI Register
ENU Register
UART
:
:
E001:E000
On-Chip ROM
USER MEMORY
0120
DFFF:DFFE
0104
Port D Input Register
:
:
0201:0200
External Expansion
Memory
00F5:00F4
00F3:00F2
00F1:00F0
BFUN Register
DIR B Register
DIR A Register / IBUF
PORTS A & B
CONTROL
01FF:01FE
:
01C1:01C0
:
On-Chip RAM
USER RAM
00E6
UPIC Register
UPI CONTROL
PORTS A & B
00E3:00E2
00E1:00E0
Port B
Port A / OBUF
0195:0194
WATCHDOG Address WATCHDOG Logic
0192
0191:0190
018F:018E DIVBY Register
018D:018C T3 Timer
018B:018A R3 Register
0189:0188
0187:0186
0185:0184
0183:0182
0181:0180
T0CON Register
TMMODE Register
00DE:00DF (reserved)
00DD:00DC HALT Enable Register
PORT CONTROL
& INTERRUPT
CONTROL
00D8
00D6
00D4
00D2
00D0
Port I Input Register
SIO Register
IRCD Register
IRPD Register
ENIR Register
Timer Block T0:T3
REGISTERS
T2 Timer
R2 Register
I2CR Register/ R1
I3CR Register/ T1
I4CR Register
00CF:00CE
00CD:00CC
00CB:00CA
00C9:00C8
00C7:00C6
00C5:00C4
00C3:00C2
00C0
X Register
B Register
K Register
A Register
PC Register
SP Register
(reserved)
PSW Register
015E:015F
015C
0153:0152
0151:0150
014F:014E
EICR
EICON
Port P Register
PWMODE Register
R7 Register
HPC CORE
REGISTERS
014D:014C T7 Timer
014B:014A R6 Register
00BF:00BE
: :
0001:0000
Timer Block T4:T7
On-Chip
RAM
USER RAM
0149:0148
0147:0146
0145:0144
0143:0142
0141:0140
T6 Timer
R5 Register
T5 Timer
R4 Register
T4 Timer
26
Design Considerations
Designs using the HPC family of 16-bit high speed CMOS
microcontrollers need to follow some general guidelines on
usage and board layout.
A recommended crystal oscillator circuit to be used with the
HPC is shown below. See table for recommended compo-
nent values. The recommended values given in the table
below have yielded consistent results and are made to
match a crystal with a 18 pF load capacitance, with some
small allowance for layout capacitance.
Floating inputs are a frequently overlooked problem. CMOS
inputs have extremely high impedance and, if left open, can
float to any voltage. You should thus tie unused inputs to
V
or ground, either through a resistor or directly. Unlike
A recommended layout for the oscillator network should be
as close to the processor as physically possible, entirely
CC
the inputs, unused outputs should be left floating to allow
the output to switch without drawing any DC current.
within 1 distance. This is to reduce lead inductance from
×
long PC traces, as well as interference from other compo-
nents, and reduce trace capacitance. The layout contains a
large ground plane either on the top or bottom surface of
the board to provide signal shielding, and a convenient loca-
tion to ground both the HPC, and the case of the crystal.
To reduce voltage transients, keep the supply line’s parasit-
ic inductances as low as possible by reducing trace lengths,
using wide traces, ground planes, and by decoupling the
supply with bypass capacitors. In order to prevent additional
voltage spiking, this local bypass capacitor must exhibit low
inductive reactance. You should therefore use high frequen-
cy ceramic capacitors and place them very near the IC to
minimize wiring inductance.
It is very critical to have an extremely clean power supply for
and
the HPC crystal oscillator. Ideally one would like a V
CC
ground plane that provide low inductance power lines to the
chip. The power planes in the PC board should be decou-
pled with three decoupling capacitors as close to the chip
as possible. A 1.0 mF, a 0.1 mF, and a 0.001 mF dipped mica
or ceramic cap mounted as close to the HPC as is physically
possible on the board, using the shortest leads, or surface
mount components. This should provide a stable power
supply, and noiseless ground plane which will vastly im-
prove the performance of the crystal oscillator network.
Keep V bus routing short. When using double sided or
CC
multilayer circuit boards, use ground plane techniques.
#
Keep ground lines short, and on PC boards make them
#
as wide as possible, even if trace width varies. Use sepa-
rate ground traces to supply high current devices such as
relay and transmission line drivers.
In systems mixing linear and logic functions and where
#
supply noise is critical to the analog components’ per-
formance, provide separate supply buses or even sepa-
rate supplies.
HPC Oscillator Table
XTAL
If you use local regulators, bypass their inputs with a tan-
#
Frequency
(MHz)
R (X)
1
talum capacitor of at least 1 mF and bypass their outputs
with a 10 mF to 50 mF tantalum or aluminum electrolytic
capacitor.
s
2
1500
1200
910
750
600
470
390
300
220
180
150
120
100
75
If the system uses a centralized regulated power supply,
use a 10 mF to 20 mF tantalum electrolytic capacitor or a
50 mF to 100 mF aluminum electrolytic capacitor to de-
#
4
6
couple the V
bus connected to the circuit board.
CC
8
Provide localized decoupling. For random logic, a rule of
thumb dictates approximately 10 nF (spaced within
12 cm) per every two to five packages, and 100 nF for
every 10 packages. You can group these capacitances,
but it’s more effective to distribute them among the ICs. If
the design has a fair amount of synchronous logic with
outputs that tend to switch simultaneously, additional de-
coupling might be advisable. Octal flip flop and buffers in
bus-oriented circuits might also require more decoupling.
Note that wire-wrapped circuits can require more decou-
pling than ground plane or multilayer PC boards.
#
10
12
14
16
18
20
22
24
26
28
30
62
e
e
e
R
3.3 MX
27 pF
F
1
2
C
C
33 pF
XTAL Specifications: The crystal used was an M-TRON Industries MP-1 Se-
ries XTAL. ‘‘AT’’ cut parallel resonant
e
C
L
18 pF
Series Resistance is:
@
TL/DD/8801–40
25X 25 MHz
@
40X 10 MHz
FIGURE 29. Recommended Crystal Circuit
@
600X 2 MHz
27
Indirect
HPC16083 CPU
The HPC16083 CPU has a 16-bit ALU and six 16-bit regis-
ters
The instruction contains an 8-bit address field. The contents
of the WORD addressed points to the memory for the oper-
and.
Arithmetic Logic Unit (ALU)
Indexed
The ALU is 16 bits wide and can do 16-bit add, subtract and
shift or logic AND, OR and exclusive OR in one timing cycle.
The ALU can also output the carry bit to a 1-bit C register.
The instruction contains an 8-bit address field and an 8- or
16-bit displacement field. The contents of the WORD ad-
dressed is added to the displacement to get the address of
the operand.
Accumulator (A) Register
The 16-bit A register is the source and destination register
for most I/O, arithmetic, logic and data memory access op-
erations.
Immediate
The instruction contains an 8-bit or 16-bit immediate field
that is used as the operand.
Address (B and X) Registers
Register Indirect (Auto Increment and Decrement)
The 16-bit B and X registers can be used for indirect ad-
dressing. They can automatically count up or down to se-
quence through data memory.
The operand is the memory addressed by the X register.
This mode automatically increments or decrements the X
register (by 1 for bytes and by 2 for words).
Register Indirect (Auto Increment and Decrement) with
Conditional Skip
Boundary (K) Register
The 16-bit K register is used to set limits in repetitive loops
of code as register B sequences through data memory.
The operand is the memory addressed by the B register.
This mode automatically increments or decrements the B
register (by 1 for bytes and by 2 for words). The B register is
then compared with the K register. A skip condition is gener-
ated if B goes past K.
Stack Pointer (SP) Register
The 16-bit SP register is the pointer that addresses the
stack. The SP register is incremented by two for each push
or call and decremented by two for each pop or return. The
stack can be placed anywhere in user memory and be as
deep as the available memory permits.
ADDRESSING MODESÐDIRECT MEMORY AS
DESTINATION
Direct Memory to Direct Memory
Program (PC) Register
The instruction contains two 8- or 16-bit address fields. One
field directly points to the source operand and the other field
directly points to the destination operand.
The 16-bit PC register addresses program memory.
Addressing Modes
ADDRESSING MODESÐACCUMULATOR AS
DESTINATION
Immediate to Direct Memory
The instruction contains an 8- or 16-bit address field and an
8- or 16-bit immediate field. The immediate field is the oper-
and and the direct field is the destination.
Register Indirect
This is the ‘‘normal’’ mode of addressing for the HPC16083
(instructions are single-byte). The operand is the memory
addressed by the B register (or X register for some instruc-
tions).
Double Register Indirect Using the B and X Registers
Used only with Reset, Set and IF bit instructions; a specific
bit within the 64 kbyte address range is addressed using the
B and X registers. The address of a byte of memory is
formed by adding the contents of the B register to the most
significant 13 bits of the X register. The specific bit to be
modified or tested within the byte of memory is selected
using the least significant 3 bits of register X.
Direct
The instruction contains an 8-bit or 16-bit address field that
directly points to the memory for the operand.
HPC Instruction Set Description
Mnemonic
Description
Action
ARITHMETIC INSTRUCTIONS
a
ADD
ADC
Add
Add with carry
Add short imm8
Decimal add with carry
Subtract with carry
Decimal subtract w/carry
Multiply (unsigned)
Divide (unsigned)
MA MemI
MA
xMA
x
x
a
a
C
MA
carryxC
carryxC
carryxC
carryxC
a
ADDS
DADC
SUBC
DSUBC
MULT
DIV
MA iMmemm8IxMA
a
a
a
MA MemI
x
CxMA
MA MemI CxMA (Decimal)
b
MA
C
ccaarrrryyxC
C
b
a
MemxI
x
MA (Decimal)x
MA*/MemIxMMAA,&reXm, .0xXK, ,00xKC, 0
xC
K, carry
DIVD
Divide Double Word (unsigned)
(X & MA)/MemIxMA, remxX, 0x
Compare MA & MemI, Do next if equal
x
C
IFEQ
IFGT
If equal
If greater than
l
Compare MA & MemI, Do next if MA MemI
AND
OR
XOR
Logical and
Logical or
Logical exclusive-or
MA and MemIxMA
MA
MA xoor rMMeemmI IxMA
x
MEMORY MODIFY INSTRUCTIONS
a
b
INC
DECSZ
Increment
Decrement, skip if 0
Mem
Mem
1
1
x
xMMeemm, Skip next if Mem
e
0
28
HPC Instruction Set Description (Continued)
Mnemonic
Description
Action
BIT INSTRUCTIONS
SBIT
RBIT
IFBIT
Set bit
Reset bit
If bit
0
1xMMeemm..bbiitt
x
If Mem.bit is true, do next instr.
MEMORY TRANSFER INSTRUCTIONS
LD
Load
MemI
Mxem(XM)em
xMA
x
g
A, X 1 (or 2)
Load, incr/decr X
Store to Memory
Exchange
x
X
ST
X
AÝ
Exchange, incr/decr X
Push Memory to Stack
Pop Stack to Memory
AÝMem
1 (or 2)
x
x
X
g
a
PUSH
POP
W
A xWM(SemP)(,XS),PX
SP
b
SP
2
x
Mem(B)x
SP, W(SP2)x
W
g
A, B 1 (or 2)
LDS
XS
Load A, incr/decr B,
Skip on condition
x
B,
MeSmki(pBn)Ýext if B greater/less than K
A,B 1 (or 2)
x
B,
g
Exchange, incr/decr B,
Skip on condition
Skip next if B greater/less than K
REGISTER LOAD IMMEDIATE INSTRUCTIONS
LD B
LD K
LD X
LD BK
Load B immediate
Load K immediate
Load X immediate
Load B and K immediate
immxB
x
immxK
immxBX,imm
x
K
ACCUMULATOR AND C INSTRUCTIONS
CLR A
INC A
DEC A
COMP A
SWAP A
RRC A
RLC A
SHR A
SHL A
SC
Clear A
0
x
A
a
Increment A
Decrement A
Complement A
Swap nibbles of A
Rotate A right thru C
Rotate A left thru C
Shift A right
Shift A left
A
A
x
1xA
b
1
A
x
x x xA7:4x
A15:12w
CwA15 w . . . wA0wC
1’s complemAe1n1t:8owf A AÝA3:0
CxA15
x
. . .x A0x C
0 wA15 w...... wAA00wC
0
CxA15
RC
Reset C
0
1xC
C
Set C
e
e
IFC
IF C
Do next if C
Do next if C
1
0
IFNC
IF not C
TRANSFER OF CONTROL INSTRUCTIONS
a
xPC
[
W(table
]
Ý
JSRP
Jump subroutine from table
PC
x
SP ,SP
2
x
SP
)
a
is 1025 to 1023)
a
a
b
b
[
a
]
SP ,SP
Ý
Ý
JSR
Jump subroutine relative
PC
(
x
2
x
SP,PC
x
x
PC
PC
b
Ý
a
[
]
JSRL
JP
Jump subroutine long
Jump relative short
Jump relative
PC
PC
PC
PC
PC
x
SP ,SP
2
x
SP,PC
a
a
a
a
a
Ý
Ý
Ý
Ý
x
x
x
PC( is 32 to 31)
a
Ý
JMP
JMPL
JID
PC( is 257 to 255)
PC
Jump relative long
a
a
Jump indirect at PC
A
A
1
x
PC
a
then Mem(PC) PC
JIDW
NOP
RET
RETSK
RETI
x
PC
a
b
b
No Operation
PC
SP
1
x
x
PC
[
[
[
]
]
]
SP 2xSP, SP
Return
x
x
x
PC
PC, & skip
PC, interrupt re-enabled
2xSSPP,, SSPP
Return then skip next
Return from interrupt
b
SP
2
Note: W is 16-bit word of memory
MA is Accumulator A or direct memory (8 or 16-bit)
Mem is 8-bit byte or 16-bit word of memory
MemI is 8- or 16-bit memory or 8 or 16-bit immediate data
imm is 8-bit or 16-bit immediate data
imm8 is 8-bit immediate data only
29
Memory Usage
Number Of Bytes For Each Instruction (number in parenthesis is 16-Bit field)
Using Accumulator A
To Direct Memory
Direct Immed.
Reg Indir.
Direct
Indir.
Index
Immed.
(B)
(X)
*
**
*
**
LD
X
1
1
1
1
1
1
2(4)
2(4)
2(4)
3
3
3
4(5)
4(5)
4(5)
2(3)
Ð
3(5)
Ð
5(6)
Ð
3(4)
Ð
5(6)
Ð
ST
Ð
Ð
Ð
Ð
Ð
ADC
1
Ð
1
2
Ð
2
3(4)
Ð
3
Ð
3
4(5)
Ð
4(5)
2
4(5)
Ð
5(6)
Ð
4(5)
Ð
5(6)
Ð
ADDS
SBC
3(4)
3(4)
3(4)
3(4)
3(4)
3(4)
3(4)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
2(3)
2(3)
2(3)
Ð
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
DADC
DSBC
ADD
1
2
3
1
2
3
1
2
3
MULT
DIV
1
2
3
1
2
3
DIVD
1
2
3
IFEQ
IFGT
AND
OR
1
1
1
1
1
2
2
2
2
2
3(4)
3(4)
3(4)
3(4)
3(4)
3
3
3
3
3
4(5)
4(5)
4(5)
4(5)
4(5)
2(3)
2(3)
2(3)
2(3)
2(3)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
4(5)
4(5)
4(5)
4(5)
4(5)
5(6)
5(6)
5(6)
5(6)
5(6)
XOR
*8-bit direct address
**16-bit direct address
Instructions that modify memory directly
Immediate Load Instructions
Immed.
(B)
(X)
Direct
Indir
Index
B&X
SBIT
RBIT
IFBIT
1
1
1
2
2
2
3(4)
3(4)
3(4)
3
3
3
4(5)
4(5)
4(5)
1
1
1
LD B,*
LD X,*
LD K,*
2(3)
2(3)
2(3)
DECSZ
INC
3
3
2
2
2(4)
2(4)
3
3
4(5)
4(5)
LD BK,*,*
3(5)
Register Indirect Instructions with
Auto Increment and Decrement
Instructions Using A and C
Transfer of Control Instructions
Register B With Skip
CLR
INC
A
A
A
A
A
A
A
A
A
1
1
1
1
1
1
1
1
1
1
1
1
1
JSRP
JSR
1
2
3
1
2
3
1
1
1
1
1
1
a
b
)
(B
)
(B
DEC
COMP
SWAP
RRC
RLC
SHR
SHL
SC
JSRL
JP
LDS A,*
XS A,*
1
1
1
1
JMP
JMPL
JID
Register X
JIDW
NOP
RET
RETSK
RETI
a
b
(X
)
(X
)
LD A,*
X A,*
1
1
1
1
RC
IFC
IFNC
Stack Reference Instructions
Direct
PUSH
POP
2
2
30
Code Efficiency
One of the most important criteria of a single chip microcon-
troller is code efficiency. The more efficient the code, the
more features that can be put on a chip. The memory size
on a chip is fixed so if code is not efficient, features may
have to be sacrificed or the programmer may have to buy a
larger, more expensive version of the chip.
BIT MANIPULATION INSTRUCTIONS
Any bit of memory, I/O or registers can be set, reset or
tested by the single byte bit instructions. The bits can be
addressed directly or indirectly. Since all registers and I/O
are mapped into the memory, it is very easy to manipulate
specific bits to do efficient control.
The HPC16083 has been designed to be extremely code-
efficient. The HPC16083 looks very good in all the standard
coding benchmarks; however, it is not realistic to rely only
on benchmarks. Many large jobs have been programmed
onto the HPC16083, and the code savings over other popu-
lar microcontrollers has been considerable.
DECIMAL ADD AND SUBTRACT
This instruction is needed to interface with the decimal user
world.
It can handle both 16-bit words and 8-bit bytes.
The 16-bit capability saves code since many variables can
be stored as one piece of data and the programmer does
not have to break his data into two bytes. Many applications
store most data in 4-digit variables. The HPC16083 supplies
8-bit byte capability for 2-digit variables and literal variables.
Reasons for this saving of code include the following:
SINGLE BYTE INSTRUCTIONS
The majority of instructions on the HPC16083 are single-
byte. There are two especially code-saving instructions:
MULTIPLY AND DIVIDE INSTRUCTIONS
JP is a 1-byte jump. True, it can only jump within a range of
plus or minus 32, but many loops and decisions are often
within a small range of program memory. Most other micros
need 2-byte instructions for any short jumps.
The HPC16083 has 16-bit multiply, 16-bit by 16-bit divide,
and 32-bit by 16-bit divide instructions. This saves both
code and time. Multiply and divide can use immediate data
or data from memory. The ability to multiply and divide by
immediate data saves code since this function is often
needed for scaling, base conversion, computing indexes of
arrays, etc.
JSRP is a 1-byte call subroutine. The user makes a table of
the 16 most frequently called subroutines and these calls
will only take one byte. Most other micros require two and
even three bytes to call a subroutine. The user does not
have to decide which subroutine addresses to put into the
table; the assembler can give this information.
Development Support
HPC MICROCONTROLLER DEVELOPMENT SYSTEM
EFFICIENT SUBROUTINE CALLS
The 2-byte JSR instructions can call any subroutine within
plus or minus 1k of program memory.
National Semiconductor’s HPC microcontroller develop-
ment is supported through a combination of third party hard-
ware and software, coupled with NSC in-house developed
software consisting of compilers, assemblers, linkers, cross
converters and debuggers. The code modules can then be
transferred to many EPROM programming systems.
MULTIFUNCTION INSTRUCTIONS FOR DATA MOVE-
MENT AND PROGRAM LOOPING
The HPC16083 has single-byte instructions that perform
multiple tasks. For example, the XS instruction will do the
following:
CUSTOMER SUPPORT
National Semiconductor’s Customer Response Center
(CRC) provides samples, literature, prices, product informa-
tion. The CRC’s engineering staff is prepared to answer
questions regarding specific design and application ques-
tions regarding specific design and application questions.
Call any weekday 7:00 AM to 7:00 PM central time (US) to
1-800-272-9959 or contact your regional business center.
1. Exchange A and memory pointed to by the B register
2. Increment or decrement the B register
3. Compare the B register to the K register
4. Generate a conditional skip if B has passed K
The value of this multipurpose instruction becomes evident
when looping through sequential areas of memory and exit-
ing when the loop is finished.
31
Development Support (Continued)
ment for accessing Dial-A-Helper is a Hayes compatible mo-
dem.
DIAL-A-HELPER
Dial-A-Helper is a service provided by the Microcontroller
Applications group. Dial-A-Helper is an Electronic Bulletin
Board Information system and additionally, provides the ca-
pability of remotely accessing the development system at a
customer site.
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
Order P/N: MDS-DIAL-A-HLP
INFORMATION SYSTEM
Information system package contains:
DIAL-A-HELPER Users Manual
Public Domain Communications Software
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be ac-
cessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Micro-
controller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities can be found. The minimum require-
FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
support.
Development Tools Selection Table
Description
Order
Manual
Number
Number
NSC
HPC-DEV-IBMA User’s manuals and disks for Assembler/Linker/Librarian package for the IBM PC
HPC-DEV-IBMC User’s manuals and disks for C Compiler and Assembler/Linker/Librarian package for the
IBM PC
424410836-001
424410883-001
424410836-001
HPC-DEV-HDB
User’s manuals and disks for Source Symbolic Debugger, C Compiler and Assembler/Linker/ 424421640-001
Librarian Package for the IBM PC
For use with the HP system only
424410883-001
424410836-001
Signum
USP-HPC
Base UnitÐUser’s manual and screen debugger
30 MHz POD and interface board for HPC46164
30 MHz POD and interface board for HPC46064
30 MHz POD and interface board for HPC46083
40 MHz POD and interface board for HPC46100
POD-HPC164
POD-HPC064
POD-HPC083
POD-HPC100
POD-HPC164-3 20 MHz 3.3V POD and interface board for HPC43164
POD-HPC064-3 20 MHz 3.3V POD and interface board for HPC43064
POD-HPC100-3 30 MHz 3.3V POD and interface board for HPC43100
Hewlett Packard
64700A
64706A
64775S
OPT006
64775G
64775H
64775J
64701A
Card cage
48 Channel Analyzer
Software interface
Software interface to IBM PC
HPC16083 Emulator with 128K RAM
HPC16064 Emulator with 128K RAM
HPC16400E Emulator with 128K RAM
LAN Interface (Optional)
Contact your local NSC sales office for ordering information
The Signum system comes with power supply, base unit software, RS232 link to host and emulator pod for the HPC Family member
ordered. It also includes an interface connector that fits between the POD and the Target board. This system does not support
deelopment of HPC46400E based systems. Source symbolic debug capability for both assembly and C language is included in the
screen debugger.
The HP model 64775 emulator/analyzer provides in system emulation up to 20 MHz, 0 wait state memory, and 30 MHz, 1 wait state
memory for al devices except the HPC46400E, which is 20 MHz, 1 wait state. A reverse assembler is also available.
The recommended configuration for the IBM PC compatible host is a 386 or higher running DOS 3.0 or higher with 4 MB of
extended memory. An RS232 serial port capable of running at 19.2K baud and a three button mouse is recommended for the
Signum System interface.
32
Development Support (Continued)
Voice: (408) 721-5582
Modem: (408) 739-1162
Baud: 300 or 1200 Baud
Set-Up: Length: 8-bit
Parity: None
Stop Bit: 1
Operation: 24 hrs, 7 days
DIAL-A-HELPER
TL/DD/8801–32
Part Selection
The HPC family includes devices with many different options and configurations to meet various application needs. The number
HPC16083 has been generically used throughout this datasheet to represent the whole family of parts. The following chart
explains how to order various options available when ordering HPC family members.
Note: All options may not currently be available.
TL/DD/8801–31
FIGURE 30. HPC Family Part Numbering Scheme
Examples
HPC46003V20
Ð ROMless, Commercial temp. (0 C to 70 C), PLCC
§
§
HPC16083XXX/U20Ð 8k masked ROM, Military temp. ( 55 C to 125 C), PGA
b
a
§
b
§
a
HPC26083XXX/V20 Ð 8k masked ROM, Automotive temp. ( 40 C to 105 C), PLCC
§
§
33
Physical Dimensions inches (millimeters)
Leaded Chip Carrier Package (EL)
Order Number HPC16083XXX/L20, HPC16083XXX/L30, HPC16003EL20, HPC26003EL20, HPC36003EL20,
HPC46003EL20, HPC16003EL30, HPC26003EL30, HPC36003EL30 or HPC46003EL30
NS Package Number EL68A
Pin Grid Array Pinout (U)
Order Number HPC16083XXX/U20, HPC16083XXX/U30, HPC16003U20 or HPC16003U30
NS Package Number U68A
34
Physical Dimensions inches (millimeters) (Continued)
Plastic Leaded Chip Carrier (V)
Order Number HPC16083XXX/V20, HPC26083XXX/V20, HPC36083XXX/V20, HPC46083XXX/V20, HPC16083XXX/V30,
HPC26083XXX/V30, HPC36083XXX/V30, HPC16083XXX/V30, HPC16003V20, HPC26003V20, HPC36003V20,
HPC46003V20, HPC16003V30, HPC26003V30, HPC36003V30 or HPC46003V30
NS Package Number V68A
35
Physical Dimensions inches (millimeters) (Continued)
80-Pin QFP Package (VF)
Order Number HPC46083XXX/F20, HPC46083XXX/F30, HPC46003VF20 or HPC46003VF30
NS Package Number VF80B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
HPC46083XXX/F20
IC 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP80, PLASTIC, QFP-80, Microcontroller
NSC
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