LF11333 [NSC]
Quad SPST JFET Analog Switches; 四通道SPST JFET模拟开关
| 型号： | LF11333 |
| 厂家： | 
National Semiconductor |
| 描述： | Quad SPST JFET Analog Switches |
| 文件： | 总18页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1995
LF11331/LF13331/LF11332/LF13332/LF11333/
LF13333/LF11201/LF13201/LF11202/LF13202
Quad SPST JFET Analog Switches
General Description
Features
n Analog signals are not loaded
These devices are a monolithic combination of bipolar and
JFET technology producing the industry’s first one chip quad
JFET switch. A unique circuit technique is employed to main-
tain a constant resistance over the analog voltage range of
±
n Constant “ON” resistance for signals up to 10V and
100 kHz
n Pin compatible with CMOS switches with the advantage
of blow out free handling
n Small signal analog signals to 50 MHz
n Break-before-make action: tOFF tON
n High open switch isolation at 1.0 MHz: −50 dB
n Low leakage in “OFF” state:
n TTL, DTL, RTL compatibility
n Single disable pin opens all switches in package on
LF11331, LF11332, LF11333
±
10V. The input is designed to operate from minimum TTL
levels, and switch operation also ensures
break-before-make action.
These devices operate from 15V supplies and swing a
a
<
±
±
10V analog signal. The JFET switches are designed for ap-
<
1.0 nA
plications where a dc to medium frequency analog signal
needs to be controlled.
n LF11201 is pin compatible with DG201
Test Circuit and Schematic Diagram
DS005667-2
FIGURE 1. Typical Circuit for One Switch
DS005667-12
FIGURE 2. Schematic Diagram (Normally Open)
© 1999 National Semiconductor Corporation
DS005667
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Dissipation (Note 3)
Molded DIP (N Suffix)
Cavity DIP (D Suffix)
500 mW
900 mW
Operating Temperature Range
LF11201, 2 and LF11331, 2, 3
LF13201, 2 and LF13331, 2, 3
Storage Temperature
(Note 2)
−55˚C to +125˚C
0˚C to +70˚C
Supply Voltage (VCC−VEE
Reference Voltage
Logic Input Voltage
Analog Voltage
)
36V
−65˚C to +150˚C
V
EE≤VR≤VCC
Soldering Information
VR−4.0V≤VIN≤VR+6.0V
N and D Package (10 sec.)
SO Package:
300˚C
V
EE≤VA≤VCC+6V;
VA≤VEE+36V
Vapor Phase (60 sec.)
Infrared (15 sec.)
215˚C
220˚C
<
|IA| 20 mA
Analog Current
Electrical Characteristics (Note 4)
LF11331/2/3
LF13331/2/3
LF13201/2
Min Typ Max Min Typ Max
Symbol
Parameter
Conditions
LF11201/2
Units
=
=
=
RON
“ON” Resistance
VA 0, ID 1 mA
TA 25˚C
150 200
200 300
150
200
10
250
350
50
Ω
Ω
=
RON Match
VA
“ON” Resistance Matching
Analog Range
TA 25˚C
5
20
Ω
±
±
±
±
10 11
10
11
V
=
=
=
±
IS(ON) +
ID(ON)
Leakage Current in “ON” Condition
Switch “ON,” VS VD 10V
TA 25˚C
0.3
3
5
100
5
0.3
3
10
30
10
30
10
30
nA
nA
nA
nA
nA
nA
V
=
=
IS(OFF)
Source Current in “OFF” Condition
Drain Current in “OFF” Condition
Switch “OFF,” VS +10V,
TA 25˚C
0.4
3
0.4
3
=
VD −10V
100
5
=
=
ID(OFF)
Switch “OFF,” VS +10V,
TA 25˚C
0.1
3
0.1
3
=
VD −10V
100
VINH
VINL
IINH
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
2.0
2.0
0.8
0.8
V
=
=
VIN 5V
TA 25˚C
3.6
10
25
3.6
40
100
µA
=
=
IINL
Logical “0” Input Current
VIN 0.8
TA 25˚C
0.1
1
0.1
1
µA
µA
ns
ns
ns
pF
pF
pF
=
=
±
tON
Delay Time “ON”
VS 10V, (Figure 3)
TA 25˚C
500
90
500
90
=
=
±
tOFF
Delay Time “OFF”
VS 10V, (Figure 3)
TA 25˚C
=
=
±
tON−tOFF
CS(OFF)
CD(OFF)
CS(ON) +
CD(ON)
ISO(OFF)
CT
Break-Before-Make
VS 10V, (Figure 3)
TA 25˚C
80
80
=
=
±
Source Capacitance
Drain Capacitance
Switch “OFF,” VS 10V
TA 25˚C
4.0
3.0
5.0
4.0
3.0
5.0
=
=
±
Switch “OFF,” VD 10V
TA 25˚C
=
=
=
TA 25˚C
Active Source and Drain Capacitance
Switch “ON,” VS VD 0V
=
“OFF” Isolation
Crosstalk
(Figure 4), (Note 5)
(Figure 4), (Note 5)
(Note 6)
TA 25˚C
−50
−65
50
−50
−65
50
dB
dB
=
TA 25˚C
=
SR
Analog Slew Rate
Disable Current
TA 25˚C
V/µs
mA
mA
mA
mA
mA
mA
mA
mA
=
IDIS
(Figure 5), (Note 7)
TA 25˚C
0.4
0.6
3.0
4.2
2.0
2.8
4.5
6.3
1.0
1.5
5.0
7.5
4.0
6.0
6.0
9.0
0.6
0.9
4.3
6.0
2.7
3.8
7.0
9.8
1.5
2.3
=
=
±
IEE
Negative Supply Current
Reference Supply Current
Positive Supply Current
All Switches “OFF,” VS 10V
TA 25˚C
7.0
10.5
5.0
=
=
±
IR
All Switches “OFF,” VS 10V
TA 25˚C
7.5
=
=
±
ICC
All Switches “OFF,” VS 10V
TA 25˚C
9.0
13.5
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2: Refer to RETSF11201X, RETSF11331X, RETSF11332X and RETSF11333X for military specifications.
Note 3: For operating at high temperature the molded DIP products must be derated based on a +100˚C maximum junction temperature and a thermal resistance
±
of +150˚C/W, devices in the cavity DIP are based on a +150˚C maximum junction temperature and are derated at 100˚C/W.
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2
Electrical Characteristics (Note 4) (Continued)
=
=
=
V 0V, and limits apply for −55˚C≤T ≤+125˚C for the LF11331/2/3 and the LF11201/2,
R
Note 4: Unless otherwise specified,
V
CC
+15V,
V
EE
−15V,
A
−25˚C≤T ≤+85˚C for the LF13331/2/3 and the LF13201/2.
A
Note 5: These parameters are limited by the pin to pin capacitance of the package.
Note 6: This is the analog signal slew rate above which the signal is distorted as a result of finite internal slew rates.
Note 7: All switches in the device are turned “OFF” by saturating a transistor at the disable node as shown in Figure 5. The delay time will be approximately equal
to the t
or t plus the delay introduced by the external transistor.
OFF
ON
Note 8: This graph indicates the analog current at which 1% of the analog current is lost when the drain is positive with respect to the source.
Note 9: (Typical) Thermal Resistance
θ
JA
Molded DIP (N)
Cavity DIP (D)
Small Outline (M)
85˚C/W
100˚C/W
105˚C/W
Connection Diagrams (Top View for SO and Dual-In-Line Packages) (All Switches Shown are For Logical “0”)
LF11331/LF13331 LF11332/LF13332
DS005667-13
DS005667-1
LF11333/LF13333
LF11201/LF13201
DS005667-15
DS005667-14
3
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Connection Diagrams (Top View for SO and Dual-In-Line Packages) (All Switches Shown are For Logical
“0”) (Continued)
LF11202/LF13202
DS005667-16
Order Number LF13201D, LF11201D, LF11201D/883, LF13202D, LF11202D, LF11202D/883, LF13331D, LF11331D,
LF11331D/883, LF13332D, LF11332D, LF11332D/883, LF13333D, LF11333D or LH11333D/883
See NS Package Number D16C
Order Number LF13201M, LF13202M, LF13331M, LF13332M or LF13333M
See NS Package Number M16A
Order Number LF13201N, LF13202N, LF13331N, LF13332N or LF13333N
See NS Package Number N16A
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4
Test Circuit and Typical Performance Curves Delay Time, Rise Time, Settling Time, and
Switching Transients
DS005667-18
DS005667-17
DS005667-20
DS005667-19
DS005667-21
DS005667-22
5
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Additional Test Circuits
DS005667-39
DS005667-40
FIGURE 3. tON, tOFF Test Circuit and Waveforms for a Normally Open Switch
DS005667-41
FIGURE 4. “OFF” Isolation, Crosstalk, Small Signal Response
Typical Performance Characteristics
“ON” Resistance
“ON” Resistance
“ON” Resistance
DS005667-23
DS005667-24
DS005667-25
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6
Typical Performance Characteristics (Continued)
Break-Before-Make Action
Switching Times
Crosstalk and “OFF”
Isolation vs Frequency
Using Test Circuit of
Figure 5
DS005667-27
DS005667-26
DS005667-28
Supply Current
Supply Current
Supply Current
DS005667-29
DS005667-31
DS005667-30
Switch Leakage Currents
Switch Leakage Current
Switch Capacitances
DS005667-33
DS005667-32
DS005667-34
7
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Typical Performance Characteristics (Continued)
Slew Rate of Analog
Voltage Above Which
Signal Loading Occurs
Maximum Accurate
Analog Current
vs Temperature
Small Signal Response
DS005667-36
DS005667-35
DS005667-37
Logical “1” Input Bias
Current
DS005667-38
the input voltage exceeds 6.0V or −4.0V with respect to VR,
a resistor in series with the input should be used to limit the
input current to less than 100µA.
Application Hints
GENERAL INFORMATION
These devices are monolithic quad JFET analog switches
with “ON” resistances which are essentially independent of
analog voltage or analog current. The leakage currents are
typically less than 1 nA at 25˚C in both the “OFF”and “ON”
switch states and introduce negligible errors in most applica-
tions. Each switch is controlled by minimum TTL logic levels
at its input and is designed to turn “OFF” faster than it will
turn “ON.” This prevents two analog sources from being tran-
siently connected together during switching. The switches
ANALOG VOLTAGE AND CURRENT
Analog Voltage
Each switch has a constant “ON” resistance (RON) for analog
voltages from (VEE+5V) to (VCC−5V). For analog voltages
greater than (VCC−5V), the switch will remain ON indepen-
dent of the logic input voltage. For analog voltages less than
(VEE+5V), the ON resistance of the switch will increase. Al-
though the switch will not operate normally when the analog
voltage is out of the previously mentioned range, the source
voltage can go to either (VEE+36V) or (VCC+6V), whichever
is more positive, and can go as negative as VEE without de-
struction. The drain (D) voltage can also go to either
(VEE+36V) or (VCC+6V), whichever is more positive, and can
go as negative as (VCC−36V) without destruction.
were
designed
for
applications
which
require
break-before-make action, no analog current loss, medium
speed switching times and moderate analog currents.
Because these analog switches are JFET rather than
CMOS, they do not require special handling.
LOGIC INPUTS
The logic input (IN), of each switch, is referenced to two for-
ward diode drops (1.4V at 25˚C) from the reference supply
(VR) which makes it compatible with DTL, RTL, and TTL
logic families. For normal operation, the logic “0” voltage can
range from 0.8V to −4.0V with respect to VR and the logic “1”
voltage can range from 2.0V to 6.0V with respect to VR, pro-
vided VIN is not greater than (VCC−2.5V). If the input voltage
is greater than (VCC−2.5V), the input current will increase. If
Analog Current
With the source (S) positive with respect to the drain (D), the
RON is constant for low analog currents, but will increase at
>
higher currents ( 5 mA) when the FET enters the saturation
region. However, if the drain is positive with respect to the
source and a small analog current loss at high analog cur-
rents (Note 6) is tolerable, a low RON can be maintained for
analog currents greater than 5 mA at 25˚C.
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8
one of these conditions occurs, the supplies would zener an
internal diode to an unlimited current; and result in a de-
stroyed device.
Application Hints (Continued)
LEAKAGE CURRENTS
The drain and source leakage currents, in both the ON and
the OFF states of each switch, are typically less than 1 nA at
25˚C and less than 100 nA at 125˚C. As shown in the typical
curves, these leakage currents are Dependent on power
supply voltages, analog voltage, analog current and the
source to drain voltage.
SWITCHING TRANSIENTS
When a switch is turned OFF or ON, transients will appear at
the load due to the internal transient voltage at the gate of
the switch JFET being coupled to the drain and source by
the junction capacitances of the JFET. The magnitude of
these transients is dependent on the load. A lower value RL
produces a lower transient voltage. A negative transient oc-
curs during the delay time ON, while a positive transient oc-
curs during the delay time OFF. These transients are rela-
tively small when compared to faster switch families.
DELAY TIMES
The delay time OFF (tOFF) is essentially independent of both
the analog voltage and temperature. The delay time ON
(tON) will decrease as either (VCC−VA) decreases or the tem-
perature decreases.
DISABLE NODE
POWER SUPPLIES
This node can be used, as shown in Figure 5, to turn all the
switches in the unit off independent of logic inputs. Normally,
the node floats freely at an internal diode drop (≈0.7V) above
VR. When the external transistor in Figure 5 is saturated, the
node is pulled very close to VR and the unit is disabled. Typi-
cally, the current from the node will be less than 1 mA. This
feature is not available on the LF11201 or LF11202 series.
The voltage between the positive supply (VCC) and either the
negative supply (VEE) or the reference supply (VR) can be as
much as 36V. To accommodate variations in input logic refer-
ence voltages, VR can range from VEE to (VCC−4.5V). Care
should be taken to ensure that the power supply leads for the
device never become reversed in polarity or that the device
is never inadvertently installed backwards in a test socket. If
DS005667-6
FIGURE 5. Disable Function
Typical Applications
Sample and Hold with Reset
DS005667-42
9
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Typical Applications (Continued)
Programmable Inverting Non-Inverting Operational Amplifier
DS005667-43
Programmable Gain Operational Amplifier
DS005667-44
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10
Typical Applications (Continued)
Demultiplexer
DS005667-45
Multiplexer/Mixer
DS005667-46
11
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Typical Applications (Continued)
8-Channel Analog Commutator with 6-Channel Select Logic
DS005667-47
Chopper Channel Amplifier
DS005667-48
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12
Typical Applications (Continued)
Self-Zeroing Operational Amplifier
DS005667-49
Programmable Integrator with Reset and Hold
DS005667-50
13
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Typical Applications (Continued)
Staircase Transfer Function Operational Amplifier
DS005667-51
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14
Typical Applications (Continued)
DSB Modulator-Demodulator
DS005667-11
15
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16
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number LF11201D, LF11201D/883, LF13201D, LF11202D, LF11202D/883, LF13202D, LF11331D,
LF11331D/883, LF13331D, LF11332D, LF11332D/883, LF13332D, LF11333D, LF11333D/883 or LF13333D
NS Package Number D16C
Order Number LF113201M, LF13202M,
LF13331M, LF13332M or LF13333M
NS Package Number M16A
17
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number LF13201N, LF13202N, LF13331N, LF13332N or LF13333N
NS Package Number N16A
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the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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