LF13509 [NSC]
8-Channel Analog Multiplexer; 8通道模拟多路复用器
| 型号： | LF13509 |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Channel Analog Multiplexer |
| 文件： | 总16页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1995
LF13508 8-Channel Analog Multiplexer
LF13509 4-Channel Differential Analog Multiplexer
General Description
The LF13508 is an 8-channel analog multiplexer which con-
nects the output to 1 of the 8 analog inputs depending on
the state of a 3-bit binary address. An enable control allows
disconnecting the output, thereby providing a package se-
lect function.
analog inputs to one of any 4 pairs of independent analog
outputs. The device has all the features of the LF13508
series and should be used whenever differential analog in-
puts are required.
Features
Y
This device is fabricated with National’s BI-FET technology
which provides ion-implanted JFETs for the analog switch
on the same chip as the bipolar decode and switch drive
circuitry. This technology makes possible low constant
‘‘ON’’ resistance with analog input voltage variations. This
device does not suffer from latch-up problems or static
charge blow-out problems associated with similar CMOS
parts. The digital inputs are designed to operate from both
TTL and CMOS levels while always providing a definite
break-before-make action.
JFET switches rather than CMOS
Y
No static discharge blow-out problem
Y
No SCR latch-up problems
Y
b
Analog signal range 11V, 15V
Constant ‘‘ON’’ resistance for analog signals between
Y
b
11V and 11V
Y
Y
Y
Y
Y
‘‘ON’’ resistance 380 X typ
Digital inputs compatible with TTL and CMOS
Output enable control
The LF13509 is a 4-channel differential analog multiplexer.
A 2-bit binary address will connect a pair of independent
e
e
2 ms typ
Break-before-make action: t
OFF
0.2 ms; t
ON
Lower leakage devices available
Functional Diagrams and Truth Tables
LF13508
SWITCH
ON
EN
A2
A1
A0
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
S1
S2
L
H
H
L
S3
L
H
L
S4
H
H
H
H
X
S5
L
H
L
S6
H
H
X
S7
H
X
S8
NONE
SWITCH
EN A1 A0
PAIR ON
L
H
H
H
H
X
L
X
L
None
S1
L
H
L
S2
H
H
S3
H
S4
TL/H/5668–1
C
1995 National Semiconductor Corporation
TL/H/5668
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation (P at 25 C)
§
D
(Notes 2 & 7)
Molded DIP (N)
Cavity DIP (D)
P
P
500 mW
900 mW
500 mW
D
D
D
b
b
V
EE
Positive Supply Negative Supply (V
CC
)
36V
Small Outline (SO) P
Positive Analog Input Voltage (Note 1)
Negative Analog Input Voltage (Note 1)
Positive Digital Input Voltage
V
CC
Maximum Junction Temperature (T
Operating Temperature Range
Storage Temperature Range
Lead Temperature
)
100 C
§
jMAX
b
V
EE
s
s
a
0 C
§
b
T
A
70 C
§
§
V
CC
a
65 C to 150 C
§
b
Negative Digital Input Voltage
Analog Switch Current
5V
k
I
10 mA
l
S
l
D Package (Soldering, 10 seconds)
N Package (Soldering, 10 seconds)
300 C
§
260 C
§
Surface Mount Package (SO)
Vapor Phase (60 seconds)
Infrared (15 seconds)
215 C
§
220 C
§
Electrical Characteristics (Note 3)
LF13508
LF13509
Symbol
Parameter
Conditions
Units
Min
Typ
380
500
Max
650
850
e
e
e
e
R
‘‘ON’’ Resistance
V
0V, I
100 mA
T
T
25 C
§
X
X
ON
OUT
S
A
A
s
s
e
b
a
e
DR
DR
ON
Swing
with Analog Voltage
10V
V
10V, I
100 mA
25 C
§
ON
Match
OUT
S
0.01
20
1
%
e
e
e
R
ON
R
Match Between Switches
V
OUT
0V, I
100 mA
T
T
25 C
§
25 C
§
150
5
X
ON
S
A
A
e
eb
eb
I
I
I
Source Current in ‘‘OFF’’
Condition
Switch ‘‘OFF’’, V
(Note 4)
11, V
11,
11,
nA
nA
nA
nA
nA
nA
V
S(OFF)
D(OFF)
D(ON)
S
D
D
0.09
0.6
1
50
e
e
e
Drain Current in ‘‘OFF’’
Condition
Switch ‘‘OFF’’, V
(Note 4)
11, V
T
25 C
§
20
S
A
A
500
20
e
Leakage Current in ‘‘ON’’
Condition
Switch ‘‘ON’’ V
11V, (Note 4)
T
25 C
§
D
500
V
V
I
Digital ‘‘1’’ Input Voltage
Digital ‘‘0’’ Input Voltage
Digital ‘‘0’’ Input Current
2.0
INH
0.7
30
40
30
40
V
INL
e
e
e
V
V
0.7V
T
T
25 C
§
1.5
1.2
mA
mA
mA
mA
ms
ms
ms
ms
dB
dB
INL
IN
A
e
EN
I
Digital ‘‘0’’ Enable Current
0.7V
25 C
§
INL(EN)
A
e
e
e
e
e
e
e
t
t
t
t
I
Switching Time of Multiplexer
Break-Before-Make
Enable Delay ‘‘ON’’
Enable Delay ‘‘OFF’’
‘‘OFF’’ Isolation
(Figure 1), (Note 5)
(Figure 3)
T
T
T
T
T
T
T
25 C
§
25 C
§
25 C
§
25 C
§
25 C
§
25 C
§
25 C
§
1.8
1.6
1.6
0.2
TRAN
A
A
A
A
A
A
A
OPEN
(Figure 2)
ON(EN)
OFF(EN)
(Figure 2)
b
b
(Note 6)
66
66
SO(OFF)
CT
Crosstalk
LF13509 Series, (Note 6)
e
C
Source Capacitance (‘‘OFF’’)
Switch ‘‘OFF’’, V
e
0V,
S(OFF)
OUT
2.2
pF
pF
V
0V
S
e
e
e
C
Drain Capacitance (‘‘OFF’’)
Positive Supply Current
Switch ‘‘OFF’’, V
e
0V,
T
25 C
§
D(OFF)
OUT
A
A
11.4
V
0V
S
I
All Digital Inputs Grounded
T
25 C
§
7.4
7.9
2.7
2.8
12
15
5
mA
mA
mA
mA
CC
e
I
Negative Supply Current
All Digital Inputs Grounded
T
25 C
§
EE
A
6
2
Electrical Characteristics (Continued)
Note 1: If the analog input voltage exceeds this limit, the input current should be limited to less than 10 mA.
Note 2: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by T
, i , and the ambient temperature,
jMAX jA
e
b
T
A
T
A
. The maximum available power dissipation at any temperature is P
(T
)/i or the 25 C P
, whichever is less.
DMAX
§
D
jMAX
jA
s
s
T
H
e
g
Note 3: These specifications apply for V
15V and over the absolute maximum operating temperature range (T
T
A
) unless otherwise noted.
S
L
Note 4: Conditions applied to leakage tests insure worse case leakages. Exceeding 11V on the analog input may cause an ‘‘OFF’’ channel to turn ‘‘ON’’.
Note 5: Lots are sample tested to this parameter. The measurement conditions of Figure 1 insure worse case transition time.
Note 6: ‘‘OFF’’ isolation is measured with all switches ‘‘OFF’’ and driving a source. Crosstalk is measured with a pair of switches ‘‘ON’’, driving channel A and
e
e
e
7 pF, V
S
e
3 Vrms, f 500 kHz.
measuring channel B. R
200, C
L
L
Note 7: Thermal Resistance i (Junction to Ambient)
jA
Molded DIP (N)
Cavity DIP (D)
150 C/W
§
100 C/W
§
Connection Diagrams
LF13508
Dual-In-Line (N or D) or Small Outline (SO) Packages
LF13509
Dual-In-Line (N or D) or Small Outline (SO) Packages
TL/H/5668–2
Order Number LF13509D
Order Number LF13508D
See NS Package Number D16C
Order Number LF13508M
See NS Package Number D16C
Order Number LF13509M
See NS Package Number M16A
Order Number LF13508N
See NS Package Number N16A
See NS Package Number M16A
Order Number LF13509N
See NS Package Number N16A
AC Test Circuits and Switching Time Waveforms
TL/H/5668–3
FIGURE 1. Transition Time
3
AC Test Circuit and Switching Time Waveforms (Continued)
TL/H/5668–4
FIGURE 3. Break-Before-Make
Transition Times and Transients
TL/H/5668–5
TL/H/5668–6
TL/H/5668–7
TL/H/5668–8
Test Circuit
TL/H/5668–10
TL/H/5668–9
4
Typical Performance Characteristics
‘‘ON’’ Resistance
‘‘ON’’ Resistance
‘‘ON’’ Resistance
TL/H/5668–11
5
Application Hints
The LF11508 series is an 8-channel analog multiplexer
which allows the connection of a single load to 1 of 8 differ-
ent analog inputs. These multiplexers incorporate JFETs in
a switch configuration which insures a constant ‘‘ON’’ resist-
ance over the analog voltage range of the device. Four TTL
compatible inputs are provided; a 3-bit binary decode to se-
lect a particular channel and an enable input used as a
package select. The switches operate with a break-before-
make action preventing the temporary connection of 2 ana-
log inputs during switching. Because these multiplexers are
fabricated with the BI-FET process rather than CMOS, they
do not require special handling.
LEAKAGE CURRENTS
Leakage currents will remain within the specified value as
long as the drain and source remain within the specified
analog voltage range. As the switch terminals exceed the
positive analog voltage range ‘‘ON’’ and ‘‘OFF’’ leakage
currents increase. The ‘‘ON’’ leakage increases due to an
internal clamp required by the switch structure. The ‘‘OFF’’
leakage increases because the gate to source reverse bias
has been decreased to the point where the switch becomes
active. Leakage currents vary slightly with analog voltage
and will approximately double for every 10 C rise in temper-
§
ature.
The LF11509 series is a 4-channel differential multiplexer
which allows two loads to be connected to 1 of 4 different
pairs of analog inputs. The LF11509 series also has all the
features of the LF11508.
SWITCHING TIMES AND TRANSIENTS
These multiplexers operate with
a break-before-make
switch action. The turn off time is much faster than the turn
on time to guarantee this feature over the full range of ana-
log input voltage and temperature. Switching transients are
introduced when a switch is turned ‘‘OFF’’. The amplitude of
these transients may be reduced by increasing the load ca-
pacitance or decreasing the load resistance. The actual
charge transfer in the transient may be reduced by operat-
ing on reduced power supplies. Examples of switching times
and transients are shown in the typical characteristic
curves. The enable function switching times are specified
separately from switch-to-switch transition times and may
be thought of as package-to-package transition times.
ANALOG VOLTAGE AND CURRENT
The ‘‘ON’’ resistance, R , of the analog switches is con-
ON
stant over a wide input range from positive (V ) supply to
CC
b
negative (
V ) supply.
EE
The analog input should not exceed either positive or nega-
tive supply without limiting the current to less than 10 mA;
otherwise the multiplexer may get damaged. For proper op-
eration, however, the positive analog voltage should be kept
b
equal to or less than V
CC
4V as this will increase the
switch leakage in both ‘‘ON’’ and ‘‘OFF’’ state and it may
also cause a false turn ‘‘ON’’ of a normally ‘‘OFF’’ switch.
This limit applies over the full temperature range.
LOGIC INPUTS AND ENABLE INPUT
Switch selection in the LF11508 series is accomplished by
using a 3-bit binary decode while the LF11509 series uses a
2-bit decode. These binary logic inputs are compatible with
both TTL and CMOS logic voltage levels. The maximum
The maximum allowable switch ‘‘ON’’ voltage (the drop
g
across the switch in the ‘‘ON’’ condition) is 0.4V over tem-
perature. If this number is to exceed the input current should
be limited to 10 mA.
positive voltage applied to these inputs may exceed V but
CC
The ‘‘ON’’ resistance of the multiplexing switches varies
slightly with analog current because they are JFETs running
at 0V gate to source. The JFET characteristics shown in
b
a
should not exceed
V
EE
36V. The maximum negative
voltage should not be less than 4V below ground as this will
cause an internal device to zener and all the switches will
turn ‘‘ON’’.
Figure 4 indicates how R
lower R
ON
tends to vary with current. A
ON
is possible when the source voltage is negative
As shown in the schematic diagram, the logic low bias cur-
rent will flow until the PNP input is raised above the 3 diode
&
reference ( 2.1V). Above this voltage the input device be-
comes reverse biased and the input current drops to the
with respect to the drain voltage because the JFET be-
comes enhanced. Caution should be used when operating
in this mode as this may forward-bias an internal transistor
and cause high currents to flow in the switches. Thus, the
drain voltage should never be greater than 0.4V positive
with respect to the source voltage without limiting the drain
current to less than 10 mA.
k
leakage of the reverse biased junction ( 0.1 mA).
TL/H/5668–12
FIGURE 4. JFET Characteristics
6
Typical Applications
DATA ACQUISITION SYSTEM
A SIMPLIFIED SYSTEM DISCUSSION
TABLE I.
BITS
Analog multiplexers (MUX) are usually used for multi-chan-
nel Data Acquisition Units (DAU). Figure 5 shows a system
in which 8 different analog inputs are sampled and convert-
ed into digital words for further processing. The sample and
hold circuit is optional, depending on input speed require-
ments and on A/D converter speed.
t (ON)
s
ERROR %
TO 1/2 LSB
0.2
0.05
8
6.2t
7.6t
9t
10
12
16
0.01
Parameters characterizing the system are:
0.0008
11.8t
System Channels: The number of multiplexer channels.
Accuracy: The conversion accuracy of each individual sam-
ple with the system operating at the throughput rate.
e
a
R )
t
C
S
(R
R
ll IN
ON
S
Speed or Throughput Rate: Number of samples/second/
channel the system can handle.
t
: is the time it takes to discharge C within
S
s(OFF)
a tolerable error. The ‘‘OFF’’ settling time should
be taken into account for bipolar inputs where its
effects will appear as a worse case of doubling
For a discussion on system structure, addressing mode and
processor interfacing, see application note AN-159.
of the t
.
s(ON)
A. ACCURACY CONSIDERATIONS
2. Sample and Hold Influence on System Accuracy
1. Multiplexer’s Influence on System Accuracy (Figure 6).
a. The error, (E), caused by the finite ‘‘ON’’ resist-
The sample and hold, if used, also introduces errors into
the system accuracy due to:
ance, R , of the multiplexing switches is given
ON
by:
Offset voltage of sample and hold
Droop rate in the Hold mode
T : Aperture time or time delay between the time of a
#
#
#
A
digital Hold command and the actual Hold occurance
Taq: Acquisition time or time it takes to acquire an
100
e
E(%)
where:
#
a
a
a
R DR
1
R
IN
/(R
)
ON
ON
S
analog input and settle within a predetermined error
band
Hold step: Error created during the Sample to Hold
e
R
IN
following stage input impedance
#
e
negligible for JFET switches like the LF11508
DR
‘‘ON’’ resistance modulation which is
ON
mode caused by an undesirable charge injected into
the Hold capacitor C .
h
e
e
e
0, R 0, T
Example: Let R
ON
450 X, DR
e
ON
0.01% which is equivalent
to 1/2 LSB in a 12-bit system:
S
A
For more details on sample and hold errors, see the
LF198/LF298/LF398 data sheet.
e
25 C and allowable E
§
3. A/D Converter Influence on System Accuracy
The ‘‘accuracy’’ of the A/D converter is the best possible
system accuracy. In most data acquisition systems, the
A/D converter is the most expensive single component,
so its error will often dominate system error. Care should
be taken that MUX, S/H and input source errors do not
exceed system error requirements when added to A/D
errors. For instance, if an 8-bit accuracy system is desired
and an 8-bit A/D converter is used, the accuracy of the
MUX and S/H should be far better than 8 bits.
b
(100 E)
R
ON
e
e
4.5 MX
R
IN
E
À
min
Note that if temperature effects are included, some
gain (or full scale) drift will occur; but effects on linearity
are small.
b. Multiplexer settling time (t ):
s
t
: is the time required for the MUX output to
s(ON)
settle within a predetermined accuracy, as
For details on A/D converter specifications, see AN-156.
shown in Table I.
a
C
(Figure 6): MUX output capacitance
a
fol-
any stray ca-
S
lowing stage input capacitance
pacitance at this node.
TL/H/5668–13
FIGURE 5. Random-Addressed, Multiplexed DAU
FIGURE 6. 8-Channel MUX
7
Typical Applications (Continued)
where T is the aperture time of the S/H. This repre-
A
sents an input slew rate improvement by a factor: T /
B. SPEED CONSIDERATIONS
C
In the system of Figure 5 with the S/H omitted, if n-bit accu-
racy is desired, the change of the analog input voltage
T . Here again, the slew rate error is not affected by
A
the acquisition time of the Sample and Hold since con-
version will start after the S/H has settled. An impor-
tant thing to notice is that the sample and hold errors
will add to the total system error budget; therefore, the
g
should be less than 1/2 LSB over the A/D conversion
time T . In other words, the analog input slew rate, (rate of
C
change of input voltage), will cause a slew-induced error
and its magnitude, with respect to the total system error, will
depend on the particular application.
inequality of the DV /Dt expression should become
IN
more stringent.
e
e
e
e
8: T /T 80
A
Example: T
40 ms, T
0.5 ms, n
C
A
C
g
DV
1/2 LSB
V
FS
IN
k
e
So the use of a S/H allows a speed improvement by
nearly two orders of magnitude.
n
c
T
C
Dt
T
C
2
À
IN
max
where V
is the full scale voltage of the A/D. Note that
slew induced errors are not affected by the MUX switch time
since we can let the unit settle before starting conversion.
The maximum throughput rate can be calculated by:
1
Th. R
FS
e
a
a
T )
8(T
Taq
À
max
A
C
e
e
10V and n
Example: Let T
8.
40 ms (MM4357), V
C
FS
Notice that T
nor the throughput rate of the system since it may be
does not affect the DV /Dt expression
MUX
IN
e
switched and settled while the Sample and Hold is in the
Hold mode. This is true, provided that: T
DV
1mV
k
a
T .
C
k
T
A
MUX
Dt
ms
À
max
C. SYSTEM EXAMPLE(Figure 7)
which is a very small number. A 10 Vp-p sine wave of a
frequency greater than 32 Hz will have higher slew rate
than this. The maximum throughput rate of the above 8-
channel system would be calculated using both the A/D
conversion time and the sum of MUX switch ‘‘ON’’ time
and settling time, i.e.:
The LF398 S/H with a 1000 pF hold capacitor, has an ac-
quisition time of 4 ms to 0.1% (1/4 LSB error for 8 bits) and
an aperture time of less than 200 ms. On the other hand,
after the hold command, the output will settle to 0.05 mV
in 1 ms. This, together with the acquisition time, introduces
g
g
approximately a 1/4 LSB error. Allowing another 1/4 LSB
error for hold step and gain non-linearity, the maximum slew
1
error (DV /Dt) should not exceed 1/4 LSB or:
IN
e
e
Th. R
3k samples/sec/
channel
a
8(T
T
)
MUX
À
max
C
DV
1
4
1
1
IN
s
c
c
&
5mV/ms
e
a
T
S(ON)
T
T
MUX
ON
Dt
256
T
A
(which is the maximum slew rate of a 5 V peak sine wave.
Also notice that, due to the above input slew restrictions,
the analog delay caused by the finite BW of the S/H and the
digital delay caused by the response time of the controller
will be negligible. The maximum throughput rate of the sys-
tem is:
Also notice that Nyquist sampling criteria would allow
each channel to have a signal bandwidth of 1.5 kHz max,
while the slew limit dictates a maximum frequency of 32
Hz. If the input signal has a peak-to-peak voltage less
than 10V, the allowable maximum input frequency can be
calculated by:
1
e
e
2800 samples/sec/ch.
Th. R
b
6
40)10
(Slew Rate)max
a
8(5
À
max
e
f
MAX
q Vp-p
If the system speed requirements are relaxed, but the A/D
converter is still too slow, then an inexpensive S/H can be
built by using just a capacitor and a low cost FET input op
amp as shown in Figure 8.
On the other hand, if the input voltage is not band-limited a
low pass filter with an attenuation of 30 dB or better at 1.5
kHz, should be connected in front of the MUX.
1. Improving System Speed with a Sample and Hold
The system speed can be improved by using the
S/H shown in Figure 5. This allows a much greater
rate of change of V
.
IN
DV
V
FS
IN
k
n
c
Dt
2
T
A
À
max
8
Typical Applications (Continued)
sion
TL/H/5668–14
FIGURE 7b. Timing Diagram
9
Typical Applications (Continued)
An alternate way to increase the system channel is shown
in Figure 10, where the enable pins are used to disable one
MUX while the other is sampling. With this method, many 8-
channel multiplexers can be connected, but the parasitic
capacitance at the common output node will keep increas-
D. DOUBLING THE SYSTEM CHANNEL CAPABILITY
This is done in two different ways. First, we can use second
level multiplexing with speed benefits, as shown in Figure 9.
A fast 2-channel multiplexer, made by the dual analog
switch AM182, accepts the outputs of each 8-channel MUX,
LF13508, and then feeds them sequentially into an 8-bit
successive approximation A/D converter. With this tech-
nique, the throughput rate of the system can again be made
independent of the LF13508 speed. Looking at the timing
diagram, when the A/D converter converts the analog value
of an upper multiplexer channel, we switch channels in the
lower multiplexer for the next conversion. This can be done
provided that:
ing and will eventually degrade the settling time, t
.
s(ON)
Also, the MUX speed will now affect the system throughput.
If, for instance, this method was used instead of second
level multiplexing, the system of Figure 9 will lose half of its
speed. If, however, speed is not the prime system require-
ment, the approach of Figure 10 is more cost effective.
E. DIFFERENTIAL INPUT SYSTEMS
Systems operating in industrial environments may require
an instrumentation amplifier to separate the desired analog
signal from any common-mode signal present. The
LF11509 was designed to provide 4 pairs of differential in-
put signals to the input of an instrumentation amplifier for
further process.
s
a
1 CP
T
MUX
T
C
The LF356 connected as unity gain buffers are used be-
cause of the low input impedance of the A/D; they are con-
nected between multiplexers for speed optimization. With a
maximum clock frequency of 4.5 MHz:
6
10
e
e
Th. R
31.25k samples/sec/channel
c
16
2
and
DV
10
1
IN
Dt
k
c
e
19.5 mV/ms for 10V
FS
256 2ms
À
max
TL/H/5668–15
The acquisition time, T , of the Sample and Hold depends upon: R , I
A
of switches, Z
of switches
OUT
#
#
#
#
ON DSS
j
e
40 kX
I
1.5 mA, Z
OUT
DSS
e
e
e
1000 pF, T
A
V
10V, C
20 ms to 0.1%
IN
h
j
b
Error created by charge injection during Hold mode: DV
10 pF (14.5V
V )/C
IN h
E
FIGURE 8. Inexpensive Sample and Hold
10
Typical Applications (Continued)
TL/H/5668–16
FIGURE 9b. Timing Diagram
11
Typical Applications (Continued)
TL/H/5668–17
FIGURE 10. A 16-Channel Multiplexer with Sequential Multiplexing
12
Schematic Diagrams
LF13508
13
Schematic Diagrams (Continued)
LF13509
14
Physical Dimensions inches (millimeters)
Dual-In-Line Package (D)
Order Number LF13508D or LF13509D
NS Package D16C
16-Lead (0.150 Wide) Molded Small Outline Package, JEDEC (SO)
×
Order Number LF13508M or LF13509M
NS Package Number M16A
15
Physical Dimensions inches (millimeters) (Continued)
Dual-In-Line Package (N)
Order Number LF13508N or LF13509N
NS Package N16A
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support device or system whose failure to perform can
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