LF298MX/NOPB [NSC]
IC SAMPLE AND HOLD AMPLIFIER, 20 us ACQUISITION TIME, PDSO14, ROHS COMPLIANT, SOIC-14, Sample and Hold Circuit;型号: | LF298MX/NOPB |
厂家: | National Semiconductor |
描述: | IC SAMPLE AND HOLD AMPLIFIER, 20 us ACQUISITION TIME, PDSO14, ROHS COMPLIANT, SOIC-14, Sample and Hold Circuit 放大器 光电二极管 |
文件: | 总13页 (文件大小:519K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
July 2000
LF198/LF298/LF398, LF198A/LF398A
Monolithic Sample-and-Hold Circuits
General Description
Features
±
±
n Operates from 5V to 18V supplies
n Less than 10 µs acquisition time
n TTL, PMOS, CMOS compatible logic input
n 0.5 mV typical hold step at Ch = 0.01 µF
n Low input offset
The LF198/LF298/LF398 are monolithic sample-and-hold
circuits which utilize BI-FET technology to obtain ultra-high
dc accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, dc gain accuracy is
0.002% typical and acquisition time is as low as 6 µs to
0.01%. A bipolar input stage is used to achieve low offset
voltage and wide bandwidth. Input offset adjust is accom-
plished with a single pin, and does not degrade input offset
drift. The wide bandwidth allows the LF198 to be included in-
side the feedback loop of 1 MHz op amps without having sta-
bility problems. Input impedance of 1010Ω allows high
source impedances to be used without degrading accuracy.
n 0.002% gain accuracy
n Low output noise in hold mode
n Input characteristics do not change during hold mode
n High supply rejection ratio in sample or hold
n Wide bandwidth
n Space qualified, JM38510
P-channel junction FET’s are combined with bipolar devices
in the output amplifier to give droop rates as low as 5 mV/min
with a 1 µF hold capacitor. The JFET’s have much lower
noise than MOS devices used in previous designs and do
not exhibit high temperature instabilities. The overall design
guarantees no feed-through from input to output in the hold
mode, even for input signals equal to the supply voltages.
Logic inputs on the LF198 are fully differential with low input
current, allowing direct connection to TTL, PMOS, and
CMOS. Differential threshold is 1.4V. The LF198 will operate
±
±
from 5V to 18V supplies.
An “A” version is available with tightened electrical
specifications.
Typical Connection and Performance Curve
Acquisition Time
DS005692-32
DS005692-16
Functional Diagram
DS005692-1
© 2000 National Semiconductor Corporation
DS005692
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Hold Capacitor Short
Circuit Duration
10 sec
Lead Temperature (Note 4)
H package (Soldering, 10 sec.)
N package (Soldering, 10 sec.)
M package:
260˚C
260˚C
±
Supply Voltage
18V
Power Dissipation (Package
Limitation) (Note 2)
Operating Ambient Temperature Range
LF198/LF198A
Vapor Phase (60 sec.)
215˚C
220˚C
500 mW
Infrared (15 sec.)
Thermal Resistance (θJA) (typicals)
H package 215˚C/W (Board mount in still air)
85˚C/W (Board mount in
400LF/min air flow)
−55˚C to +125˚C
−25˚C to +85˚C
0˚C to +70˚C
LF298
LF398/LF398A
Storage Temperature Range
−65˚C to +150˚C
N package
M package
115˚C/W
106˚C/W
Input Voltage
Equal to Supply Voltage
Logic To Logic Reference
Differential Voltage (Note 3)
Output Short Circuit Duration
θJC (H package, typical) 20˚C/W
+7V, −30V
Indefinite
Electrical Characteristics
The following specifcations apply for −VS + 3.5V ≤ VIN ≤ +VS − 3.5V, +VS = +15V, −VS = −15V, TA = Tj = 25˚C, Ch = 0.01 µF,
RL = 10 kΩ, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified.
Parameter
Conditions
LF198/LF298
LF398
Typ
2
Units
Min
Typ
Max
Min
Max
7
Input Offset Voltage, (Note 5)
Input Bias Current, (Note 5)
Tj = 25˚C
1
3
5
mV
mV
nA
nA
Ω
Full Temperature Range
Tj = 25˚C
10
5
25
75
10
50
Full Temperature Range
Tj = 25˚C
100
Input Impedance
Gain Error
1010
1010
Tj = 25˚C, RL = 10k
Full Temperature Range
Tj = 25˚C, Ch = 0.01 µF
0.002 0.005
0.004 0.01
%
0.02
96
0.02
90
%
Feedthrough Attenuation Ratio
at 1 kHz
86
80
dB
Output Impedance
Tj = 25˚C, “HOLD” mode
Full Temperature Range
Tj = 25˚C, Ch = 0.01 µF, VOUT = 0
Tj≥25˚C
0.5
2
0.5
4
Ω
Ω
4
6
“HOLD” Step, (Note 6)
Supply Current, (Note 5)
Logic and Logic Reference Input
Current
0.5
4.5
2
2.0
5.5
10
1.0
4.5
2
2.5
6.5
10
mV
mA
µA
Tj = 25˚C
Leakage Current into Hold
Capacitor (Note 5)
Tj = 25˚C, (Note 7)
Hold Mode
30
100
30
200
pA
Acquisition Time to 0.1%
∆VOUT = 10V, Ch = 1000 pF
Ch = 0.01 µF
4
20
5
4
20
5
µs
µs
Hold Capacitor Charging Current
Supply Voltage Rejection Ratio
Differential Logic Threshold
VIN−VOUT = 2V
mA
dB
V
VOUT = 0
80
110
1.4
1
80
110
1.4
2
Tj = 25˚C
0.8
2.4
1
0.8
2.4
2
Input Offset Voltage, (Note 5)
Tj = 25˚C
mV
mV
nA
nA
Full Temperature Range
Tj = 25˚C
2
3
Input Bias Current, (Note 5)
5
25
75
10
25
50
Full Temperature Range
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2
Electrical Characteristics
The following specifcations apply for −VS + 3.5V ≤ VIN ≤ +VS − 3.5V, +VS = +15V, −VS = −15V, TA = Tj = 25˚C, Ch = 0.01 µF,
RL = 10 kΩ, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified.
Parameter
Conditions
LF198A
Typ
LF398A
Typ Max
Units
Min
Max
Min
Input Impedance
Tj = 25˚C
1010
1010
Ω
%
Gain Error
Tj = 25˚C, RL = 10k
0.002 0.005
0.004 0.005
Full Temperature Range
Tj = 25˚C, Ch = 0.01 µF
0.01
96
0.01
90
%
Feedthrough Attenuation Ratio
at 1 kHz
86
86
dB
Output Impedance
Tj = 25˚C, “HOLD” mode
Full Temperature Range
Tj = 25˚C, Ch = 0.01µF, VOUT = 0
Tj≥25˚C
0.5
1
4
0.5
1
6
Ω
Ω
“HOLD” Step, (Note 6)
Supply Current, (Note 5)
Logic and Logic Reference Input
Current
0.5
4.5
2
1
1.0
4.5
2
1
mV
mA
µA
5.5
10
6.5
10
Tj = 25˚C
Leakage Current into Hold
Capacitor (Note 5)
Tj = 25˚C, (Note 7)
Hold Mode
30
100
30
100
pA
Acquisition Time to 0.1%
∆VOUT = 10V, Ch = 1000 pF
Ch = 0.01 µF
4
20
5
6
4
20
5
6
µs
µs
mA
dB
V
25
25
Hold Capacitor Charging Current
Supply Voltage Rejection Ratio
Differential Logic Threshold
VIN−VOUT = 2V
VOUT = 0
Tj = 25˚C
90
110
1.4
90
110
1.4
0.8
2.4
0.8
2.4
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature, T . The maximum
A
JMAX JA
allowable power dissipation at any temperature is P = (T
− T )/θ , or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum
A JA
D
JMAX
junction temperature, T
, for the LF198/LF198A is 150˚C; for the LF298, 115˚C; and for the LF398/LF398A, 100˚C.
JMAX
Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without
causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the nega-
tive supply.
Note 4: See AN-450 “Surface Mounting Methods and their effects on Product Reliability” for other methods of soldering surface mount devices.
±
±
Note 5: These parameters guaranteed over a supply voltage range of 5 to 18V, and an input range of −V + 3.5V ≤ V ≤ +V − 3.5V.
S
IN
S
Note 6: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step
with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.
Note 7: Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can
be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range.
Note 8: A military RETS electrical test specification is available on request. The LF198 may also be procured to Standard Military Drawing #5962-8760801GA or to
MIL-STD-38510 part ID JM38510/12501SGA.
Typical Performance Characteristics
Aperture Time
(Note 9)
Dielectric Absorption
Error in Hold Capacitor
Dynamic Sampling Error
DS005692-19
DS005692-17
DS005692-18
Note 9: See Definition of Terms
3
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Typical Performance Characteristics (Continued)
Output Droop Rate
Hold Step
“Hold” Settling Time
(Note 10)
DS005692-21
DS005692-20
DS005692-22
Leakage Current into Hold
Capacitor
Phase and Gain (Input to
Output, Small Signal)
Gain Error
DS005692-25
DS005692-23
DS005692-24
Power Supply Rejection
Output Short Circuit Current
Output Noise
DS005692-27
DS005692-28
DS005692-26
Note 10: See Definition
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4
Typical Performance Characteristics (Continued)
Input Bias Current
Feedthrough Rejection Ratio
(Hold Mode)
Hold Step vs Input Voltage
DS005692-31
DS005692-29
DS005692-30
Output Transient at Start
of Sample Mode
Output Transient at Start
of Hold Mode
DS005692-12
DS005692-13
Logic Input Configurations
TTL & CMOS
3V ≤ VLOGIC (Hi State) ≤ 7V
DS005692-33
Threshold = 1.4V
DS005692-34
Threshold = 1.4V
*
Select for 2.8V at pin 8
5
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Logic Input Configurations (Continued)
CMOS
7V ≤ VLOGIC (Hi State) ≤ 15V
DS005692-35
+
Threshold = 0.6 (V ) + 1.4V
DS005692-36
+
Threshold = 0.6 (V ) − 1.4V
Op Amp Drive
DS005692-37
Threshold ≈ +4V
DS005692-38
Threshold = −4V
Application Hints
Hold Capacitor
reduced if the output of the LF198 is digitized quickly after
the hold mode is initiated. The hysteresis relaxation time
constant in polypropylene, for instance, is 10—50 ms. If
A-to-D conversion can be made within 1 ms, hysteresis error
will be reduced by a factor of ten.
Hold step, acquisition time, and droop rate are the major
trade-offs in the selection of a hold capacitor value. Size and
cost may also become important for larger values. Use of the
curves included with this data sheet should be helpful in se-
lecting a reasonable value of capacitance. Keep in mind that
for fast repetition rates or tracking fast signals, the capacitor
drive currents may cause a significant temperature rise in
the LF198.
DC and AC Zeroing
DC zeroing is accomplished by connecting the offset adjust
pin to the wiper of a 1 kΩ potentiometer which has one end
tied to V+ and the other end tied through a resistor to ground.
The resistor should be selected to give ≈0.6 mA through the
1k potentiometer.
A significant source of error in an accurate sample and hold
circuit is dielectric absorption in the hold capacitor. A mylar
cap, for instance, may “sag back” up to 0.2% after a quick
change in voltage. A long sample time is required before the
circuit can be put back into the hold mode with this type of
capacitor. Dielectrics with very low hysteresis are polysty-
rene, polypropylene, and Teflon. Other types such as mica
and polycarbonate are not nearly as good. The advantage of
polypropylene over polystyrene is that it extends the maxi-
mum ambient temperature from 85˚C to 100˚C. Most ce-
AC zeroing (hold step zeroing) can be obtained by adding an
inverter with the adjustment pot tied input to output. A 10 pF
±
capacitor from the wiper to the hold capacitor will give 4 mV
hold step adjustment with a 0.01 µF hold capacitor and 5V
logic supply. For larger logic swings, a smaller capacitor
<
(
10 pF) may be used.
Logic Rise Time
>
ramic capacitors are unusable with
1% hysteresis. Ce-
ramic “NPO” or “COG” capacitors are now available for
125˚C operation and also have low dielectric absorption. For
more exact data, see the curve Dielectric Absorption Error.
The hysteresis numbers on the curve are final values, taken
after full relaxation. The hysteresis error can be significantly
For proper operation, logic signals into the LF198 must have
a minimum dV/dt of 1.0 V/µs. Slower signals will cause ex-
cessive hold step. If a R/C network is used in front of the
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6
Application Hints (Continued)
Guarding Technique
logic input for signal delay, calculate the slope of the wave-
form at the threshold point to ensure that it is at least
1.0 V/µs.
Sampling Dynamic Signals
Sample error to moving input signals probably causes more
confusion among sample-and-hold users than any other pa-
rameter. The primary reason for this is that many users make
the assumption that the sample and hold amplifier is truly
locked on to the input signal while in the sample mode. In ac-
tuality, there are finite phase delays through the circuit creat-
ing an input-output differential for fast moving signals. In ad-
dition, although the output may have settled, the hold
capacitor has an additional lag due to the 300Ω series resis-
tor on the chip. This means that at the moment the “hold”
command arrives, the hold capacitor voltage may be some-
what different than the actual analog input. The effect of
these delays is opposite to the effect created by delays in the
logic which switches the circuit from sample to hold. For ex-
ample, consider an analog input of 20 Vp-p at 10 kHz. Maxi-
mum dV/dt is 0.6 V/µs. With no analog phase delay and 100
ns logic delay, one could expect up to (0.1 µs) (0.6V/µs)
= 60 mVerror if the “hold” signal arrived near maximum dV/dt
of the input. A positive-going input would give a +60 mV er-
ror. Now assume a 1 MHz (3 dB) bandwidth for the overall
analog loop. This generates a phase delay of 160 ns. If the
hold capacitor sees this exact delay, then error due to analog
delay will be (0.16 µs) (0.6 V/µs) = −96 mV. Total output error
is +60 mV (digital) −96 mV (analog) for a total of −36 mV. To
add to the confusion, analog delay is proportioned to hold
capacitor value while digital delay remains constant. A family
of curves (dynamic sampling error) is included to help esti-
mate errors.
DS005692-5
Use 10-pin layout. Guard around Chis tied to output.
A curve labeled Aperture Time has been included for sam-
pling conditions where the input is steady during the sam-
pling period, but may experience a sudden change nearly
coincident with the “hold” command. This curve is based on
a 1 mV error fed into the output.
A second curve, Hold Settling Time indicates the time re-
quired for the output to settle to 1 mV after the “hold” com-
mand.
Digital Feedthrough
Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier
is put into the hold mode. To minimize this problem, board
layout should keep logic lines as far as possible from the
analog input and the Ch pin. Grounded guarding traces may
also be used around the input line, especially if it is driven
from a high impedance source. Reducing high amplitude
logic signals to 2.5V will also help.
7
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Typical Applications
X1000 Sample & Hold
Sample and Difference Circuit
(Output Follows Input in Hold
Mode)
DS005692-40
V
= V + ∆V (HOLD MODE)
B IN
OUT
DS005692-39
*
For lower gains, the LM108 must be frequency compensated
Ramp Generator with Variable Reset Level
Integrator with Programmable Reset Level
DS005692-42
DS005692-43
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8
Typical Applications (Continued)
Output Holds at Average of Sampled Input
Increased Slew Current
DS005692-46
DS005692-47
Reset Stabilized Amplifier (Gain of 1000)
Fast Acquisition, Low Droop Sample & Hold
DS005692-49
DS005692-50
9
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Typical Applications (Continued)
Synchronous Correlator for Recovering
Signals Below Noise Level
2–Channel Switch
DS005692-53
A
B
±
±
0.2%
Gain
ZIN
1
0.02%
1
1010Ω
47 kΩ
BW
. 1 MHz
. 400 kHz
−90 dB
Crosstalk −90 dB
@
1 kHz
Offset
≤ 6 mV
≤ 75 mV
DS005692-52
DC & AC Zeroing
Staircase Generator
DS005692-59
DS005692-55
*
Select for step height
→
50k
1V Step
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10
Typical Applications (Continued)
Differential Hold
Capacitor Hysteresis Compensation
DS005692-56
**
Adjust for amplitude
DS005692-57
Definition of Terms
Hold Step: The voltage step at the output of the sample and
hold when switching from sample mode to hold mode with a
steady (dc) analog input voltage. Logic swing is 5V.
Hold Settling Time: The time required for the output to
settle within 1 mV of final value after the “hold” logic com-
mand.
Acquisition Time: The time required to acquire a new ana-
log input voltage with an output step of 10V. Note that acqui-
sition time is not just the time required for the output to settle,
but also includes the time required for all internal nodes to
settle so that the output assumes the proper value when
switched to the hold mode.
Dynamic Sampling Error: The error introduced into the
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that this
error term occurs even for long sample times.
Aperture Time: The delay required between “Hold” com-
mand and an input analog transition, so that the transition
does not affect the held output.
Gain Error: The ratio of output voltage swing to input volt-
age swing in the sample mode expressed as a per cent dif-
ference.
Connection Diagrams
Dual-In-Line Package
Small-Outline Package
Metal Can Package
DS005692-15
DS005692-11
Order Number LF298M or LF398M
See NS Package Number M14A
Order Number LF398N
or LF398AN
DS005692-14
See NS Package Number N08E
Order Number LF198H,
LF198H/883, LF298H,
LF398H, LF198AH or LF398AH
See NS Package Number H08C
(Note 8)
11
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Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
Order Number LF198H, LF298H, LF398H, LF198AH or LF398AH
NS Package Number H08C
Molded Small-Outline Package (M)
Order Number LF298M or LF398M
NS Package Number M14A
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12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number LF398N or LF398AN
NS Package Number N08E
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