LF6197CCJ [NSC]
160 ns Monolithic Sample-and-Hold Amplifier; 160 ns的单片采样保持放大器
| 型号： | LF6197CCJ |
| 厂家： | 
National Semiconductor |
| 描述： | 160 ns Monolithic Sample-and-Hold Amplifier |
| 文件： | 总12页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1992
LF6197 160 ns Monolithic Sample-and-Hold Amplifier
General Description
Features
Y
g
g
Operates with supply voltages from 5V to 18V
CMOS, TTL and ECL compatible logic input
Adjustable inverting or non-inverting gain
Internal hold capacitor
The LF6197 is a monolithic sample-and-hold (S/H) amplifier
that uses a proprietary ‘‘current-multiplexed sample-and-
hold’’ technique to offer extremely high speed while main-
taining 12 bits or higher accuracy. The device is built using
National’s advanced junction-isolated VIPTM (Vertically Inte-
grated PNP) and BI-FETTM process technologies.
Y
Y
Y
Y
High power-supply rejection in both sample and hold
modes
g
The LF6197 acquires a 10V step input to within 0.01% in
160 ns and has 10 mV hold step error when going from
sample to hold mode. The input offset voltage in the sample
mode is typically 3 mV. Even at extremely fast acquisition
speeds, no compromises are made in the droop rate, which
is 0.6 mV/ms. When configured for unity gain, the DC gain
error is 0.03%. The feedthrough attenuation in the hold
mode is 83 dB at DC and 77 dB at 100 kHz.
Key Specifications
Y
Acquisition time (10V step to 0.01%)
160 ns
50 ns
Y
Hold mode settling time (10V step to 0.01%)
Y
Droop rate
0.6 mV/ms
10 mV
Y
Hold step
Y
Aperture jitter
8 ps
rms
Y
Feedthrough attenuation at DC
83 dB
The LF6197 can be externally configured for either inverting
or non-inverting gains, thus offering additional flexibility to
the user. The device includes an internal 10 pF hold capaci-
tor.
Y
Small signal bandwidth
25 MHz
Applications
Y
High-speed data acquisition systems
Y
Automatic test equipment
BI-FETTM and VIPTM are trademarks of National Semiconductor Corporation.
Y
High-speed instrumentation
Y
Replaces expensive hybrid sample-and-hold amplifiers
Block Diagram
Connection Diagram
TL/H/11381–2
Top View
Ordering Information
Industrial
Package
k
k
a
(0 C
§
T
70 C)
§
A
LF6197CCJ
J14A
Ceramic DIP
TL/H/11381–1
C
1995 National Semiconductor Corporation
TL/H/11381
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1, 2)
Positive Supply Voltage (Va
Negative Supply Voltage (Vb
)
18V
a
Operating Ratings (Notes 1, 2)
b
)
18V
s
s
T
Temperature Range
LF6197CCJ
T
T
A
MIN
A
MAX
Va or Vb or 12.5V,
whichever is less
g
Analog Input Voltage
s
s
a
70 C
§
15.75V
0 C
T
§
s
a
s
a
a
Positive Supply Voltage
Negative Supply Voltage
4.75V
V
g
Logic Input to LR1 Differential Voltage
Power Dissipation (Note 3)
5V
b
s
s
b
b
15.75V
V
4.75V
1.2W
Duration of Output Short Circuit to GND
(Note 4)
ESD Susceptibility
All Pins except Pin 13 (Note 5)
Pin 13 only (Note 5)
2000V
1500V
Lead Temperature (Soldering, 10 sec.)
J Package
300 C
§
b
a
65 C to 150 C
Storage Temperature
§
§
Electrical Characteristics
b
Unless otherwise specified, the following specifications apply for Va
15V, V
15V,
12V
V
IN
12V,
s
s
a
e
a
e
b
b
l
s
k
e
0V and Logic Input Voltage 1.4V threshold, (Unit is in ‘‘sample’’
R
1 kX, C
40 pF, Logic Reference 2 (LR2) voltage
L
L
mode). V refers to the supply voltages, Va and Vb. Boldface limits apply for T
T
from T
MIN
to T ; all other limits
MAX
e
S
A
J
e
e
T
T
J
25 C.
§
A
Typical
(Note 6)
Limit
(Note 7)
Units
Symbol
INPUT CHARACTERISTICS
Parameter
Conditions
(Limit)
g
g
g
6.0
V
Input Offset Voltage
3.0
3.0
mV (max)
mV (max)
OS
e
g
V
V
5V, (Note 8)
S
DV /DT
OS
Input Offset Drift
15
mV/ C
§
R
Input Resistance (common mode)
Input Resistance (differential)
Common Mode Rejection Ratio
Positive Input Bias Current
Negative Input Bias Current
10
300
100
7
MX
IN, com
IN, dif
R
kX
e
g
CMRR
10V
80
17
dB (min)
mA (max)
mA (max)
CM
I
I
a
b
B
B
1
7.5
TRANSFER CHARACTERISTICS
e
e
1 kX
g
DC Open Loop Gain
V
V
12V, R
70
55
65
49
dB (min)
dB (min)
% (max)
% (max)
MHz (min)
OUT
L
e
e
g
g
DC Open Loop Gain (Note 8)
5V, V
OUT
2.5V
S
Gain Error (Note 9)
Gain Linearity Error
Gain Bandwidth Product
0.03
0.003
25
e
g
V
OUT
10V
0.0045
14
f
u
OUTPUT CHARACTERISTICS
R
Output Resistance
0.02
145
X
OUT
SR
Slew Rate
V/ms
b
b
Short Circuit Source Current
Short Circuit Sink Current
Maximum Capacitive Load
63
70
200
25
mA (min)
mA (min)
pF
25
C
L
No Oscillation
2
Electrical Characteristics (Continued)
b
Unless otherwise specified, the following specifications apply for Va
15V, V
15V,
12V
V
12V,
s
s
a
0V and Logic Input Voltage 1.4V threshold, (Unit is in ‘‘sample’’
e
a
e
k
b
b
IN
l
s
e
R
1 kX, C
40 pF, Logic Reference 2 (LR2) voltage
L
L
mode). V refers to the supply voltages, Va and Vb. Boldface limits apply for T
T
from T to T
; all other limits
e
S
A
J
MIN MAX
e
e
T
T
J
25 C.
§
A
Typical
(Note 6)
Limit
Units
Symbol
Parameter
Conditions
(Note 7)
(Limit)
SAMPLE/HOLD CHARACTERISTICS
t
Acquisition Time
to 0.1% (Note 10)
to 0.01% (Note 10)
ACQ
10V step
a
130
145
ns
10V step
240
260
240
ns (max)
ns (max)
ns (max)
ns (max)
b
10V step
160
260
t
t
Aperture Delay Time
4
8
ns
AD
Aperture Jitter
ps
rms
AJ
Droop Rate
0.6
10
80
mV/ms (max)
mV (max)
ns
g
V
HS
Hold Step (Note 11)
10
t
Hold Mode Settling Time to 0.01%
Feedthrough Attenuation (Note 12)
10V step
50
HMS
e
e
e
f
f
1 kHz, V
IN
20 V
p-p
83
77
dB (min)
dB
e
100 kHz, V
20 V
IN
p-p
DYNAMIC CHARACTERISTICS
e
e
e
b
b
THD
Total Harmonic Distortion
f
f
10 kHz, V
IN
20 V
83
78
dB
dB
p-p
e
150 kHz, V
20 V
IN
p-p
e
FPBW
Full Power Bandwidth (Note 13)
Small Signal Bandwidth
V
IN
20 V
p–p
2.3
MHz
MHz
25
DIGITAL LOGIC CHARACTERISTICS
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logic Input Current
2.0
0.8
20
5
V (min)
V (max)
IN(1)
IN(0)
6
3
mA (max)
mA (max)
Logic Reference 2 Input Current
Differential Logic Threshold
(Logic Input to LR1)
1.4
1.1
1.6
V(min)
V(max)
POWER SUPPLY CHARACTERISTICS
I
I
I
I
Positive Supply Current
Positive Supply Current
Negative Supply Current
Negative Supply Current
Power Supply Rejection Ratio
20
18.2
20
30
27
30
27
74
mA (max)
mA (max)
mA (max)
mA (max)
dB (min)
a
a
b
b
S
S
S
S
e
g
V
S
5V (Note 8)
5V (Note 8)
e
e
g
g
V
V
17.5
84
S
g
12V to 16V
PSRR
S
3
Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, H , and the ambient temperature T . The maximum
JA
Jmax
A
e
b
125 C/W. The Power Derating Curve shows the safe thermal operating area for this device.
e
150 C
Jmax
allowable power dissipation is P
e
(T
T
A
)/H or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
JA
§
D
Jmax
and i
§
Note 4: Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150 C.
JA
§
Note 5: Human body model, 100 pF capacitor discharged through a 1.5 kX resistor.
e
Note 6: Typicals are at T
25 C and represent the most likely parametric norm.
§
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
A
g
Note 8: Operation at 5V requires that pin 14 be forced to 2.5V.
Note 9: Gain error is calculated from the measured open loop gain.
b
Note 10: The acquisition time of the LF6197 has been measured when the device has been configured as an inverting amplifier with a gain of 1, feedback
resistor of 2 kX, feedback capacitor of 1 pF, and a total load resistor of 1 kX.
Note 11: Hold step is measured with the LF6197 configured as a unity gain follower and input connected to ground. A TTL pulse with 4 ns rise and fall times is
applied to the logic input; the hold step is dependent on the slew rate of the logic input pulse.
Note 12: See test circuit, Figure 1.
e
Note 13: Full power bandwidth is calculated using FPBW
SR/(2qV ); where SR is the measured slew rate and V is the peak voltage.
P P
4
Typical Performance Characteristics
Acquisition Time (to 0.01%)
vs Capacitive Load
Acquisition Time (to 0.01%)
vs Capacitive Load
Acquisition Time (to 0.01%)
vs Temperature
TL/H/11381–3
5
Typical Performance Characteristics (Continued)
Hold Step vs Logic
Input Rise Time
TL/H/11381–15
Power Derating Curve
TL/H/11381–16
6
Test Circuit
TL/H/11381–4
FIGURE 1. Circuit configuration for the measurement of feedthrough attenuation. Input is connected
to ground in sample mode and is connected to 20 V , 100 kHz sine wave in hold mode.
PP
Pin Descriptions
Va (12)
This is the positive power supply pin. A
a
LR1 (10)
This is the Logic Reference 1 input. By
applying the appropriate logic threshold
at this pin, the sample-and-hold amplifi-
er’s logic input can be made either CMOS
or ECL compatible. For TTL logic levels,
this pin should remain unconnected.
a
5V to 15V supply voltage should be
applied to this pin and bypassed to
ground with a 0.1 mF ceramic capacitor
in parallel with a 4.7 mF tantalum capaci-
tor.
Vb (4)
This is the negative power supply pin. A
b
applied to this pin and bypassed to
ground with a 0.1 mF ceramic capacitor
in parallel with a 4.7 mF tantalum capaci-
tor.
LR2 (13)
This is the Logic Reference 2 input. For
TTL logic levels, this pin should be con-
nected to ground; this sets the logic
threshold at the logic comparator’s invert-
ing pin at 1.4V. For CMOS or ECL logic
levels this pin should either remain un-
connected or connected to pin 10.
b
5V to 15V supply voltage should be
GND (9)
This is the ground reference pin. All sig-
nals are referenced to the potential at
this pin.
Logic Input (11) This is the logic control input pin. A logic
low at this pin will configure the amplifier
in the ‘‘sample’’ mode while a logic high
will configure the amplifier in the ‘‘hold’’
mode. The TTL, CMOS, or ECL logic
compatibility will be determined by the
voltage threshold set at the logic compar-
ator’s inverting input.
b
Input (1)
This is the inverting input of the ‘‘sam-
ple’’ amplifier. Connecting this pin
through a resistor to the output will con-
figure the sample-and-hold amplifier for
unity gain. Other inverting and non-in-
verting gains can be set by applying the
familiar op amp feedback topologies.
For stability reasons, stray capacitance
from the inverting input to ground should
be minimized.
Zener Reference For optimum acquisition and settling
times, this pin must be bypassed to
Output (14)
ground with a 0.01 mF capacitor. Further-
g
more, for 5V supply operation, this pin
must be biased at 2.5V from a low imped-
ance source.
a
Input (2)
This is the non-inverting input of the
‘‘sample’’ amplifier. This pin should be
driven from a low impedance source.
NC (3,6,7,8)
No connection.
Output (5)
This is the output of the sample-and-
hold amplifier.
7
Functional Description
The LF6197 uses a proprietary ‘‘current-multiplexed sam-
ple-and-hold’’ technique as depicted in the simplified block
diagram (Figure 2). The amplifier consists of two transcon-
booster in the output stage rapidly charges the hold capaci-
tor. A wide-bandwidth amplifier, high-current output stage
and fast current-switched hold-to-sample mode selection al-
lows for a slew rate of 145 V/ms and acquisition time of
under 200 ns.
ductance input stages g and g and a common gain and
m1 m2
output buffer stage A3. In the sample mode, internal current
switching is employed to connect the input stage g to the
m1
is discon-
When there is a change to the Hold mode, switches S2 and
S3 are quickly opened and switch S1 is effectively connect-
common output stage A3 while input stage g
m2
nected. Additionally, switches S2 and S3 are closed, there-
by shorting the internal dummy capacitor and connecting
one end of the hold capacitor to a low impedance ground.
Although the simplified schematic shows the switches S1
and S2 connected to ground, the switches are in fact con-
nected to a reference potential which appears as a common
ed to the output of g while input stage g is disconnect-
m2 m1
ed. The composite amplifier is now comprised of g
and
m2
A3 and the loop around the amplifier is closed by the hold
capacitor. Note that the opening of switch S3 causes
charge injection into the hold capacitor. However, an equal
amount of charge is injected into the dummy capacitor due
to the opening of a matched switch S2. The net effect is a
differential cancellation of charge and thus the pedestal er-
ror (hold step) is greatly reduced. Meanwhile, excellent
feedthrough attenuation is achieved because the input sig-
nal is isolated from the output by the inactive input stage
mode voltage at the two inputs of g
m2
For unity gain, the inverting input of g
.
is externally con-
m1
nected to the output through a resistor, thus closing the loop
around the amplifier. Conventional op-amp feedback topolo-
gies may be employed to configure the amplifier for invert-
ing and non-inverting gains. In the sample mode, a current
g
.
m1
TL/H/11381–5
FIGURE 2. Simplified Block Diagram of LF6197 Sample-and-Hold Amplifier, Connected for Unity Gain and TTL Logic
8
Application Hints
1.0 LOGIC CONFIGURATIONS
cations. Familiar op-amp feedback topologies are employed
to configure the LF6197 for non-inverting (Figure 8) or in-
verting (Figure 9) gains. Note that a feedback resistor of
value 1 kX or larger must be used for all gain settings, in-
cluding non-inverting unity gain. The feedback resistor is re-
quired to limit the current through LF6197’s internal clamp
diodes when the device is in the hold mode.
The LF6197 can be configured to interface with TTL,
CMOS, or ECL logic. The device is configured for the de-
sired logic using the two Logic Reference pins (LR1 and
LR2).
1.1 TTL Logic
To configure the device to operate with TTL logic, the LR1
pin should be left open and the LR2 pin should be grounded
(Figure 4). This will set the threshold of the logic comparator
at 1.4V.
4.0 POWER SUPPLY SEQUENCING
When power supply to the LF6197 is turned on, the nega-
tive supply must come on before the positive supply. Mean-
while, when the power supply is turned off, the positive sup-
ply must turn off before the negative supply. Improper power
supply sequencing may destroy the device. To protect the
device against improper power supply sequencing, anti-re-
versal diodes may be used across the supply pins
(Figure 10).
1.2 CMOS Logic
To configure the device to operate with CMOS logic (with a
2.5V threshold at the comparator), several options are avail-
able. The LR1 and LR2 pins can be tied together and con-
nected to a 2.5V reference (Figure 5); or LR2 can be set to
1.1V with a resistor diode network and LR1 can be by-
passed to ground with a 0.01 mF capacitor (Figure 6).
1.3 ECL Logic
b
To operate with ECL logic (threshold at 1.3V), set LR2 at
2.7V with a voltage divider from the negative supply and
b
bypass LR1 with a 0.01 mF capacitor (Figure 7).
2.0 ZENER REFERENCE OUTPUT
The LF6197 includes an internal zener diode to bias various
sections of the chip. The zener diode output is brought out
at pin 14; the voltage at this pin is typically 6.25V when the
g
device is powered from 15V supplies. For optimum device
performance, pin 14 must be bypassed to ground with a
TL/H/11381–7
g
0.01 mF capacitor. If the device is powered from 5V sup-
e
Threshold
1.4V
plies, then pin 14 must be biased at 2.5V from a low imped-
ance source (Figure 3).
FIGURE 4. TTL Logic
TL/H/11381–6
FIGURE 3. Biasing Pin 14 to 2.5V
g
for Operation from 5V Supplies
3.0 ADJUSTING GAIN
TL/H/11381–8
The LF6197 allows the user to amplify as well as to sample-
and-hold an input signal. This feature eliminates the need
for an amplifier preceding the S/H amplifier in many appli-
e
Threshold
2.5V
FIGURE 5. CMOS Logic
9
Application Hints (Continued)
TL/H/11381–9
TL/H/11381–10
e
e
1.3V
Threshold
2.5V
Threshold
FIGURE 6. Another Circuit for CMOS Logic
FIGURE 7. ECL Logic
TL/H/11381–12
TL/H/11381–13
FIGURE 8. LF6197 with Non-Inverting Gain
FIGURE 9. LF6197 with Inverting Gain
TL/H/11381–11
TL/H/11381–14
FIGURE 10. Using Anti-Reversal Diodes to Protect
LF6197 from Improper Power Supply Sequencing
FIGURE 11. Increasing Linearity to 16 Bits Using a
Negative Impedance Load at the Output of LF6197
10
11
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number LF6197CCJ
NS Package Number J14A
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